CN110413041B

CN110413041B - Chip clock circuit and control method thereof

Info

Publication number: CN110413041B
Application number: CN201910688603.8A
Authority: CN
Inventors: 黎俊辉; 聂玉庆
Original assignee: Gree Electric Appliances Inc of Zhuhai; Zhuhai Zero Boundary Integrated Circuit Co Ltd
Current assignee: Gree Electric Appliances Inc of Zhuhai; Zhuhai Zero Boundary Integrated Circuit Co Ltd
Priority date: 2019-07-29
Filing date: 2019-07-29
Publication date: 2020-11-17
Anticipated expiration: 2039-07-29
Also published as: CN110413041A

Abstract

The invention provides a chip clock circuit and a control method thereof. The chip clock circuit comprises a plurality of clocks, a clock switching module and a control module, wherein the clocks comprise a logic OR module, a clock generating module and a trigger module, clock clk signals generated by the clocks are obtained through the input end of the clock switching module, and one clock is selected as a main clock to be output; the control module monitors the state of each clock and controls the closing or opening of each clock. The state of the chip clock signal is monitored in real time through the control module, the clock signal is switched in time according to the actual monitoring result, the chip clock signal is ensured to have high reliability, the chip is in a stable and reliable working state, the chip system can be ensured to operate at a lower power consumption level through a computer readable storage program, one path of clock signal can be provided for the system selectively, and the flexibility of the chip system clock is improved.

Description

Chip clock circuit and control method thereof

Technical Field

The invention relates to the technical field of electronic circuits, in particular to a chip clock circuit and a control method thereof.

Background

The clock is the heart of the circuit, the stability and reliability of the clock are the basis for the stable operation of the circuit, almost all digital systems process signals according to the clock one beat, all parts of the system are made according to the beat, one or more clock signals are needed to enable all parts of the circuit to beat uniformly, and the final function failure or performance of a plurality of circuits cannot meet the initial design requirement, which is caused by the loss or abnormality of the clock and brings great loss to the circuit.

The common technique for solving the problem in the prior art is clock backup, that is, two crystal oscillators are simultaneously arranged in a communication system, and the two crystal oscillators are simultaneously in a working state to simultaneously generate two clocks, an external selection circuit automatically selects any one of the two crystal oscillators with a normal working state as a main clock to output the main clock to a load chip, and when a detection circuit detects that the main clock is in a failure state of 'no oscillation starting', the external selection circuit automatically controls switching of the main clock and the standby clock, and uses the other backup clock as a current output clock to continuously provide a normal clock signal of the load chip, so as to ensure normal operation of the system.

However, this clock backup method needs to keep both clocks in working state all the time, but the clock failure rate is low, so that one clock may be in an invalid working state for a long time, and a large amount of power consumption is wasted.

Disclosure of Invention

The invention aims to overcome the defects in the prior art and provide a chip clock circuit and a control method thereof, which ensure that a chip clock signal has high reliability through the cooperation of software and hardware, so that the chip is in a stable and reliable working state, invalid power consumption can not be generated, one path of clock signal can be provided for a system, and the flexibility of a chip system clock is improved.

The purpose of the invention is realized by the following technical scheme:

in a first aspect, the invention provides a chip clock circuit, comprising a plurality of clocks, a clock switching module and a control module, the clock comprises logic OR modules, a clock generation module and a trigger module, wherein the first input end of each logic OR module is connected with the input end of the trigger and the output end of the control module, the common end of the first input end of each logic OR module and the input end of the trigger module of each clock is respectively connected with different output ends of the control module, the second input end of each logic OR module is connected with the output end of the trigger, and the common end of the second input end of the logic OR module and the output end of the trigger is connected with the input end of the control module and the control end of the clock switching module, the output end of the logic OR module is connected with the enabling end of the clock generation module, and the output end of the clock generation module is connected with the clk control end of the trigger and the input end of the clock switching module; the input end of the clock switching module acquires clock clk signals generated by each clock, selects one clock as a main clock to be output, and closes other clocks as standby clocks; the control module monitors the state of each clock and controls the closing or opening of each clock.

Optionally, the clock generation module is implemented by one or more of an active crystal oscillator and a passive crystal oscillator.

Optionally, the clock switching module is implemented by a data selector.

Optionally, the data selector is specifically a mux21a two-to-one data selector.

Optionally, the switching module of the clock switching module is one of seamless switching and seam switching.

In a second aspect, the present invention provides a method for controlling a chip clock circuit in the first aspect, including:

when the circuit is started, the control module is used for carrying out initialization operation, simultaneously operating all clocks, and selecting one clock as a main clock to be output;

the control module closes all clocks except the main clock and takes the closed clocks as standby clocks;

and the control module monitors the state of the master clock in real time in the running process, and selects one of other clocks to start as the master clock when the master clock fails.

Optionally, the standby clock may be turned on to provide one clock for more circuits according to requirements.

Optionally, when the master clock fails, a backup clock is enabled as the master clock after delaying for one clock cycle.

The invention has the beneficial effects that: the state of the chip clock signal is monitored in real time through the control module, the clock signal is switched in time according to the actual monitoring result, the chip clock signal is ensured to have high reliability, the chip is in a stable and reliable working state, the chip system can be ensured to operate at a lower power consumption level by controlling the on or off of each clock, one path of clock signal can be provided for the system selectively, and the flexibility of the chip system clock is improved.

Drawings

The invention is further illustrated by means of the attached drawings, but the embodiments in the drawings do not constitute any limitation to the invention, and for a person skilled in the art, other drawings can be derived on the basis of the following drawings without inventive effort.

Fig. 1 is a topology structure diagram of a chip clock circuit according to an embodiment of the present invention.

Fig. 2 is a flowchart of a method for improving a chip clock circuit according to an embodiment of the present invention.

Detailed Description

Features and exemplary embodiments of various aspects of the present invention will be described in detail below, and in order to make objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. It will be apparent to one skilled in the art that the present invention may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present invention by illustrating examples of the present invention.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element. In digital circuits, the high and low of a voltage are represented by logic levels. The logic level includes both a high level and a low level. The digital circuits formed by different components have different logic levels corresponding to voltages. The logic level is defined by a threshold level, e.g., in a TTL gate circuit, a voltage greater than 3.5 volts (threshold high level) is defined as a logic high level, represented by the number 1; a voltage less than 0.3 volts (threshold low level) is defined as a logic low level, represented by the number 0. Thus, the threshold high level and the threshold low level (collectively referred to as threshold levels) define logic levels, and adjusting the logic levels is accomplished by adjusting the threshold levels.

Referring to fig. 1 and fig. 2, this embodiment provides a chip clock circuit, which includes two clocks, a clock switching module 7 and a control module 8, where the first clock includes a logic or module 1, a clock generating module 2 and a flip-flop module 3, the second clock includes a logic or module 4, a clock generating module 5 and a flip-flop module 6, the connection relationship below takes the first clock as a main clock, and the connection manner of the modules of the second clock is the same as that of the first clock, where the first input end of the logic or module 1 is connected to the input end D of the flip-flop 3 and the first output end of the control module 8, the second input end of the logic or module 1 is connected to the output end Q of the flip-flop 3, and the common end of the second input end of the logic or module 1, which is connected to the output end Q of the flip-flop 3, is connected to the input end of the control module 8 and the control end of the clock, the output end of the logic or module 1 is connected with the enabling end of the clock generation module 2, as long as one input end of the two input ends of the logic or module 1 is a high level, the high level is output, and only if all the input ends are low levels, the output end outputs the low level; the output end of the clock generation module 2 is connected with the control end of the trigger 3, the common end of the clock generation module 2 is connected with the input end of the clock switching module 7, the clock generation module 2 is controlled by the enable end, when the enable end is at a high level, the clock generation module 2 outputs a clk clock, and when the enable end is at a low level, the clock generation module 2 is turned off and stops outputting the clk signal; the trigger module 3 delays an input signal D by one clock cycle and transmits the input signal D to an output end Q under the drive of a clock clk signal; the input end of the clock switching module 7 acquires a clock clk signal generated by each clock, and selects one clock as a main clock to be output; the control module 8 monitors the state of each clock and controls the on/off of each clock.

Preferably, in the first clock and the second clock of this embodiment, the clock generating module 2 and the clock generating module 5 generate the clock signal clk1 through the 11.0592MHz passive crystal oscillator, the clock switching module 7 implements the slotted switching of the clocks through the simple two-to-one data selector mux21a, since the standard baud rate of serial port communication is commonly 9600 or 4800, the 11.0592MHz passive crystal oscillator is more favorable for the circuit to communicate as the clock signal, and the simple two-to-one data selector mux21a implements the slotted switching of the clocks, so that the circuit is simpler and the cost is lower.

The embodiment provides an improvement method of a chip clock circuit, which comprises the following steps: when the circuit is started, the control module is used for carrying out initialization operation, simultaneously operating all clocks, and selecting one clock as a main clock to be output; the control module closes all clocks except the main clock and takes the closed clocks as standby clocks which can be opened according to the circuit requirements; the control module monitors the state of the master clock in real time in the running process, and when the master clock fails, the control module selects one clock from other clocks to be started as the master clock after delaying one clock period.

The workflow of this embodiment is as follows:

when the circuit is started, the control module 8 performs initialization operation, and output signals clk1_ gen _ en and clk2_ gen _ en of two output ends of the control module 8 are both at a high level; the logic or module 1 and the logic or module 4 both have an input end with a high level, and therefore both output high levels; the enable terminals of the clock generation module 2 and the clock generation module 5 are both at a high level, the clock generation module 2 outputs a clock signal clk1, and the clock generation module 5 outputs a clock signal clk 2; the control ends of the flip-flop 3 and the flip-flop 6 are both provided with clock signals clk input, the output signal clk1_ gen _ en _ reg of the output end Q is high after the flip-flop 3 delays for one clock cycle, and the output signal clk2_ gen _ en _ reg of the output end Q is high after the flip-flop 6 delays for one clock cycle; the clock switching module 7 selects a first clock as a master clock output, and the master clock is selected according to the following table:

clk1_gen_en_reg	clk2_gen_en_reg	clk1	clk2	clk
					0	0	N	N	clk1
1	0	Y	N	clk1
					0	1	N	Y	clk2
1	1	Y	Y	clk1

the letter N indicates that the clock switching module 7 does not receive the clock signal, and Y indicates that the clock switching module 7 receives the clock signal, so that when neither clock outputs the clock signal, the circuit has no main clock; when the first clock has clock signal output, whether the second clock has clock signal output or not, the first clock is selected as the main clock; only when the clock has no clock signal output and the clock II has clock signal output, selecting the clock II as the main clock output; when the clock works normally, the control module 8 sets the output signal clk2_ gen _ en _ reg of the second output end to be low level, so that the output signal clk2_ gen _ en _ reg of the flip-flop 6 is low level, the output of the logic or module 4 is low level, the clock generation module 5 stops running, and no longer outputs a clk2 clock signal, so as to reduce energy consumption; when the clock 1 serving as the main clock fails to output the clock signal clk1, the flip-flop 3 cannot delay the input signal clk1_ gen _ en by one clock cycle and then output a signal clk1_ gen _ en _ reg at the output end Q, so that the output signal clk1_ gen _ en _ reg of the flip-flop 3 is pulled to be low, the control module 8 receives that clk1_ gen _ en _ reg is low, sets clk1_ gen _ en to be low, and sets 2_ gen _ en to be high, and at this time, the clock II replaces the clock I to become the main clock; according to the circuit requirement, under the condition that the first clock is used as the main clock, the second clock can still be started through the control module 8, and one path of clock is provided for the circuits.

Finally, it should be noted that the above embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the protection scope of the present invention, although the present invention is described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications or equivalent substitutions can be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A chip clock circuit is characterized by comprising a plurality of clocks, a clock switching module and a control module, the clock comprises logic OR modules, a clock generation module and a trigger module, wherein the first input end of each logic OR module is connected with the input end of the trigger and the output end of the control module, the common end of the first input end of each logic OR module and the input end of the trigger module of each clock is respectively connected with different output ends of the control module, the second input end of each logic OR module is connected with the output end of the trigger, and the common end of the second input end of the logic OR module and the output end of the trigger is connected with the input end of the control module and the control end of the clock switching module, the output end of the logic OR module is connected with the enabling end of the clock generation module, and the output end of the clock generation module is connected with the clk control end of the trigger and the input end of the clock switching module; the input end of the clock switching module acquires clock clk signals generated by each clock, selects one clock as a main clock to be output, and closes other clocks as standby clocks; the control module monitors the state of each clock and controls the closing or opening of each clock.

2. The chip clock circuit according to claim 1, wherein the clock generation module is implemented by one or more of an active crystal oscillator and a passive crystal oscillator.

3. The chip clock circuit according to claim 2, wherein the passive crystal oscillator is an 11.0592MHz crystal oscillator.

4. The chip clock circuit according to claim 1, wherein the clock switching module is implemented by a data selector.

5. The chip clock circuit as claimed in claim 4, wherein the data selector is a mux21a two-to-one data selector.

6. The chip clock circuit according to claim 1, wherein the switching module of the clock switching module is one of seamless switching or slotted switching.

7. A method for controlling a chip clock circuit according to any one of claims 1 to 5, comprising:

8. The method as claimed in claim 7, wherein the standby clock is turned on to provide one clock for more circuits as required.

9. The method as claimed in claim 7, wherein when the primary clock fails, a backup clock is enabled as the primary clock after a delay of one clock cycle.