CN110473910A - The horizontal dual pervasion field effect pipe of low gate charge - Google Patents

Abstract

The present invention provides a kind of horizontal dual pervasion field effect transistor of low gate charge, including the first conduction type doped substrate, first conduction type well region, first conduction type heavily doped region, the one the second conduction type heavily doped regions, second conduction type drift region, the two the second conduction type heavily doped regions, first oxide layer and the heavily doped polysilicon electrode wrapped up by the first oxide layer, second conduction type channel region upper surface is covered by gate oxide and heavily doped polysilicon grid, internal electrode of the present invention is connected with source electrode, gate leakage capacitance is decomposed into gate-source capacitance and drain source capacitance, substantially reduce the length of Miller platform, grid amount of charge needed for reducing unlatching, shorten the charging time, by adjusting buried structure, that is, internal electrode length, width, the depth adjustable charging time, and then it adjusts between grid charge and conducting resistance Equilibrium relation reduces drift region electric field since internal electrode connects low potential, to slow down hot carrier's effect.

Description

Lateral Double-diffused Field Effect Transistor with Low Gate Charge

technical field

The invention belongs to the technical field of semiconductors, and in particular relates to a lateral double-diffusion field-effect transistor with low gate charge.

Background technique

In recent years, in order to meet the needs of integrated circuits, power device technology has continued to develop, and integrated power devices represented by lateral double-diffused field effect transistors have become more and more important. At the same time, as the operating frequency of devices continues to increase, The influence of gate charge on devices is becoming more and more important, and has become an important indicator for evaluating the switching performance of devices. Gate charge is an important parameter to measure the dynamic characteristics of power MOSFET. This parameter directly affects the overall performance of the device. During the development, production and use of power MOSFET devices, higher requirements are put forward for the gate charge as a key parameter. In order to meet the increasing market demand, the research on the device structure of low gate charge power MOSFET is increasing day by day. A buried shielding gate structure is added in the drift region body, and the structure is connected to the source, which greatly reduces the charging time of the gate charge.

Contents of the invention

The purpose of the present invention is to add a buried shielding structure with a potential connected to the source in the drift region of the lateral double-diffused field effect transistor, that is, an internal electrode. This electrode can shield most of the gate-to-drain capacitance, thereby reducing the gate charge and charging time. decline.

In order to realize the foregoing invention object, the technical scheme of the present invention is as follows:

A low gate charge lateral double-diffused field effect transistor, comprising a first conductivity type doped substrate 11, a first conductivity type well region 12 on the left side above the first conductivity type doped substrate 11, located in the first conductivity type well The heavily doped region 14 of the first conductivity type on the left side above the region 12, the first heavily doped region 15 of the second conductivity type located on the right side of the heavily doped region 14 of the first conductivity type, located on the right side of the well region 12 of the first conductivity type The drift region 13 of the second conductivity type on the side, the second heavily doped region 18 of the second conductivity type located at the upper right of the drift region 13 of the second conductivity type, the first oxide layer 17 located inside the drift region 13 of the second conductivity type and the The heavily doped polysilicon electrode 16 wrapped by the first oxide layer 17 , the upper surface of the channel region of the second conductivity type is covered by the gate oxide layer 110 and the heavily doped polysilicon gate 19 .

As a preferred mode, the heavily doped polysilicon electrode 16 is a multi-layer structure separated from each other and connected to the source in the height direction, which are respectively the first heavily doped polysilicon electrode 1, the second heavily doped polysilicon electrode 2 ... the nth Heavily doped polysilicon electrode n.

As a preferred mode, the heavily doped polysilicon electrode 16 is a multi-layer structure separated from each other and connected to the source in the width direction, which are respectively the first heavily doped polysilicon electrode 1, the second heavily doped polysilicon electrode 2 ... the nth layer Doped polysilicon electrode n.

As a preferred manner, the potential of the heavily doped polysilicon electrode 16 is drawn out in the height direction and connected to the source.

As a preferred manner, holes or grooves are drilled on the surface of the heavily doped polysilicon electrode 16 so as to draw out the potential in the height direction and be connected to the source.

As a preferred manner, the first conductivity type is P type and the second conductivity type is N type; or the first conductivity type is N type and the second conductivity type is P type.

As a preferred manner, the low gate charge lateral double-diffused field effect transistor structure is planar or grooved.

The beneficial effects of the present invention are:

1. The electrode in the body is connected to the source, and the gate-drain capacitance is decomposed into gate-source capacitance and drain-source capacitance, which greatly reduces the length of the Miller platform, reduces the amount of gate charge required for turning on, and shortens the charging time.

2. By adjusting the length, width, and depth of the buried structure, that is, the electrodes in the body, the charging time can be adjusted, and then the balance between the gate charge and the on-resistance can be adjusted.

3. Since the electrodes in the body are connected to a low potential, the electric field in the drift region is reduced, thereby slowing down the hot carrier effect.

4. The relevant parameters of the present invention can be adjusted according to needs, which greatly increases the flexibility of device design.

Description of drawings

FIG. 1 is a schematic structural diagram of a low gate charge lateral double-diffused field effect transistor of the present invention.

FIG. 2 is a schematic structural diagram of a lateral double-diffused field effect transistor device in the prior art.

Figure 3 is a gate charge test circuit;

Fig. 4 is a schematic diagram comparing the gate charge curves of a low gate charge lateral double diffused field effect transistor of the present invention and a reference device;

Fig. 5 is the schematic diagram of embodiment 1 of the present invention;

Fig. 6 is a schematic diagram of Embodiment 2 of the present invention.

Wherein, 1 is the first heavily doped polysilicon electrode, 2 is the second heavily doped polysilicon electrode, n is the nth heavily doped polysilicon electrode; 11 is the first conductivity type substrate, 12 is the first conductivity type well region, 13 is the second conductivity type drift region, 14 is the first conductivity type heavily doped region, 15 is the first second conductivity type heavily doped region, 16 is the heavily doped polysilicon electrode, 17 is the first oxide layer, 18 is The second heavily doped region of the second conductivity type, 19 is a heavily doped polysilicon gate, and 110 is a gate oxide layer;

21 is the first conductivity type substrate, 22 is the first conductivity type well region, 23 is the second conductivity type drift region, 24 is the first conductivity type heavily doped region, 25 is the first and second conductivity type heavily doped region 28 is a heavily doped region of the second conductivity type, 29 is a heavily doped polysilicon gate, and 210 is a gate oxide layer.

Detailed ways

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

Example 1

As shown in FIG. 1 , a low gate charge lateral double-diffused field effect transistor includes a first conductivity type doped substrate 11, a first conductivity type well region 12 on the left side above the first conductivity type doped substrate 11, The first conductivity type heavily doped region 14 located on the left side above the first conductivity type well region 12, the first second conductivity type heavily doped region 15 located on the right side of the first conductivity type heavily doped region 14, located on the first The second conductivity type drift region 13 on the right side of the conductivity type well region 12, the second second conductivity type heavily doped region 18 located on the upper right of the second conductivity type drift region 13, the second conductivity type drift region 13 located inside the second conductivity type drift region 13 An oxide layer 17 and the heavily doped polysilicon electrode 16 wrapped by the first oxide layer 17 , and the upper surface of the channel region of the second conductivity type is covered by the gate oxide layer 110 and the heavily doped polysilicon gate 19 .

Preferably, the potential of the heavily doped polysilicon electrode 16 is drawn out in the height direction and connected to the source.

Preferably, holes or grooves are drilled on the surface of the heavily doped polysilicon electrode 16 to draw potentials in the height direction and be connected to the source.

Preferably, the first conductivity type is P type and the second conductivity type is N type; or the first conductivity type is N type and the second conductivity type is P type.

Preferably, the low gate charge lateral double-diffused field effect transistor structure is planar or grooved.

The length, width and height of the heavily doped polysilicon electrodes 16 in the body can be adjusted as required.

Working principle of the present invention is:

The lateral double-diffusion field effect transistor with low gate charge is embedded with a body electrode in the drift region, and the electrode is connected to the source to form a shielding layer, and the gate-drain capacitance is decomposed into gate-source capacitance and gate-drain capacitance, greatly The influence of the gate-drain capacitance in the charging process is reduced, and the Miller platform is shortened, thereby shortening the charging time. Moreover, the buried shielding structure of the lateral double-diffused field effect transistor with low gate charge, that is, the electrodes in the body are connected to a low potential, thereby reducing the electric field in the drift region, thereby slowing down the hot carrier effect in the drift region.

With the help of MEDICI simulation software, a low gate charge lateral double-diffusion field effect transistor as shown in Figure 1 and a traditional lateral double-diffusion transistor as shown in Figure 2 under the same conditions were simulated and compared.

Fig. 4 is a schematic diagram comparing the Vg-t curves of a low gate charge lateral double diffused field effect transistor provided by the present invention and the traditional lateral double diffused field effect transistor shown in Fig. 2 under the same conditions. It can be seen from Figure 4 that the Miller platform is significantly shortened, and the total charging time is significantly reduced.

Example 2

As shown in Figure 5, the difference between this embodiment and Embodiment 1 is that the heavily doped polysilicon electrode 16 is a multi-layer structure separated from each other and connected to the source in the height direction, which are respectively the first heavily doped polysilicon electrode 1 , The second heavily doped polysilicon electrode 2 ... the nth heavily doped polysilicon electrode n. In order to achieve better shielding effect.

Example 3

FIG. 6 is a top view of a lateral double-diffused transistor with a buried shield structure in this embodiment. The difference between this embodiment and Embodiment 1 is that the heavily doped polysilicon electrode 16 is a multilayer structure separated from each other and connected to the source in the width direction, which are the first heavily doped polysilicon electrode 1 and the second heavily doped polysilicon electrode 1 respectively. Electrode 2...the nth heavily doped polysilicon electrode n to achieve a better shielding effect.

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention shall still be covered by the claims of the present invention.

Claims (7)

1. A lateral double-diffused field-effect transistor with low gate charge, characterized in that: it comprises a first conductivity type doped substrate (11), and the first conductivity type doped substrate (11) on the left side of the first conductivity type The well region (12), the first conductivity type heavily doped region (14) on the left side above the first conductivity type well region (12), the first conductivity type heavily doped region (14) on the right side The second conductivity type heavily doped region (15), the second conductivity type drift region (13) located on the right side of the first conductivity type well region (12), the second conductivity type drift region (13) located on the upper right side of the second conductivity type drift region (13) The second conductivity type heavily doped region (18), the first oxide layer (17) inside the second conductivity type drift region (13) and the heavily doped polysilicon electrode (16) wrapped by the first oxide layer (17), The upper surface of the channel region of the second conductivity type is covered by a gate oxide layer (110) and a heavily doped polysilicon gate (19). 2. The lateral double-diffused field-effect transistor with low gate charge according to claim 1, characterized in that: the heavily doped polysilicon electrode (16) is a multilayer structure separated from each other and connected to the source electrode in the height direction , are respectively the first heavily doped polysilicon electrode (1), the second heavily doped polysilicon electrode (2) ... the nth heavily doped polysilicon electrode n. 3. A kind of lateral double-diffusion field effect transistor of low gate charge according to claim 1, it is characterized in that: the heavily doped polysilicon electrode (16) is the multilayer structure that is separated from each other and connected to the source in the width direction, They are the first heavily doped polysilicon electrode (1), the second heavily doped polysilicon electrode (2)...the nth heavily doped polysilicon electrode n. 4. A low gate charge lateral double-diffused field effect transistor according to claim 1, characterized in that: the potential of the heavily doped polysilicon electrode (16) is drawn out in the height direction and connected to the source. 5. The lateral double-diffused field-effect transistor of a kind of low gate charge according to claim 4, is characterized in that: in heavily doped polysilicon electrode (16) surface punches or cuts groove so as to draw potential on height direction, and Connect to source. 6. A low gate charge lateral double diffused field effect transistor according to any one of claims 1 to 5, characterized in that: the first conductivity type is P-type, and the second conductivity type is N-type; or the first The conductivity type is N type, and the second conductivity type is P type. 7 . The low gate charge lateral double diffused field effect transistor according to claim 1 , wherein the structure of the low gate charge lateral double diffused field effect transistor is planar or slot type. 7 .