CN110501695A - A Delay Line Circuit Based on Ka-band Phased Array Radar Application - Google Patents

Abstract

The present application discloses a delay line circuit layout based on Ka-band phased array radar application. High electron mobility transistors are arranged on a gallium arsenide substrate. The delay line based on the Ka-band phased array radar application is designed by a four-stage delay line unit, and the delay line unit is composed of a pair of single-pole double-throw switches connected in series with a reference branch and a delay branch. The SPDT switch consists of two pairs of high electron mobility transistors. The gate of the transistor is connected in series with a high-value resistor and connected to a DC voltage source to form a DC bias circuit. The single pole double throw switch controls the selection of the radio frequency path by changing the bias voltage through the bias circuit, so as to realize the purpose of high precision delay. The application also discloses an integrated circuit. The delay line based on the Ka-band phased array radar application provided by this application has the advantages of low loss, high delay accuracy and compact circuit size, and is suitable for the Ka-band phased array radar application.

Description

A Delay Line Circuit Based on Ka-band Phased Array Radar Application

technical field

The present application relates to the field of semiconductor integrated circuits, in particular to a delay line circuit layout based on Ka-band phased array radar applications.

Background technique

Ka-band phased array radar has important strategic significance in modern warfare; however, delay line, as a key technology in phased array radar, has also attracted more and more attention in recent years. Therefore, it is also of great significance to design a miniaturized delay line with low loss and high precision delay.

Contents of the invention

The invention provides a delay line circuit layout and an integrated circuit based on the Ka-band phased array radar application. The delay line is designed by a multi-stage delay line unit, which has the characteristics of low loss and high delay accuracy, and is suitable for Ka-band phased array radar applications.

To this end, the technical solution adopted by the present invention is: a delay line circuit layout based on the Ka-band phased array radar application, and high electron mobility transistors are arranged on the gallium arsenide substrate.

The delay line is designed by three-stage delay line units, and the delay line units are connected through an impedance matching network.

The delay line unit consists of a pair of single-pole double-throw switches connected in series with a reference branch and a delay branch.

The single-pole double-throw switch is composed of two symmetrical pairs of high electron mobility transistors. The gate of the high electron mobility transistor is connected in series with a high-value resistor, and is connected with a DC voltage source to form a DC voltage bias circuit; different bias voltages are realized by changing the bias voltage. The selection of the radio frequency channel, and then realize the purpose of signal delay output.

The single pole double throw switch in the delay line unit realizes the selection of different radio frequency channels by different DC bias voltages ( V _state1 , V _state2 ).

The reference branch in the delay unit is a simple transmission line or a "T" branch.

The delay branch uses a resonant unit composed of capacitors and inductors. Different numbers of resonant units will result in different delays. When designing different delay units, the corresponding delay purpose can be achieved by adjusting the number of resonant units.

A semiconductor integrated circuit, which includes the circuit layout based on the Ka-band phased array radar application.

The advantage of the invention is that the delay line of the invention can realize compact and miniaturized circuit design in the Ka band. At the same time, the use of high electron mobility transistors on GaAs substrates can achieve low loss and high delay accuracy. Compared with traditional metal oxide semiconductor field effect transistors, this delay line has better loss and delay performance, and is suitable for Ka-band phase Controlled array radar application.

Description of drawings

Figure 1 Delay Line Unit Design Circuit Schematic.

Figure 2 Schematic diagram of the single-pole double-throw switch circuit.

Figure 3 is a block diagram of the delay line design based on Ka-band phased array radar applications.

Figure 4. The implementation case of this application is based on the delay line layout of the Ka-band phased array radar application.

Detailed ways

In order to make the technical principles, features and technical effects of the technical solution of the present application clearer, the technical solution of the present application will be described in detail below in conjunction with specific implementation cases.

Fig. 1 is a circuit schematic diagram of the delay line unit design based on the application of the Ka-band phased array radar in the implementation case of the present application. The selection of the reference branch and the delay branch is realized through a pair of identical single-pole double-throw switches, so as to realize the purpose of signal delay output.

The SPDT switch shown in Figure 1 is composed of two symmetrical pairs of high electron mobility transistors, which are distributed on both sides of port P1 (shown in Figure ₂ ). The high electron mobility transistor realizes the selection of different radio frequency paths through different bias voltages ( V _stage1 , V _stage2 ), that is, the selection of radio frequency paths from port P ₁ to port P ₂ or port P ₁ to port P ₃ . The gate of the high electron mobility transistor is connected to a high-impedance resistor ( R _dc ) to realize the bias circuit design.

Figure 3 shows a block diagram of the delay line design based on Ka-band phased array radar applications. In order to achieve a finer delay purpose, a three-stage delay line design is adopted. The purpose of maximum power transmission is realized through an impedance matching network between the delay line units. The bias voltage of the delay line unit is separated on one side to meet the subsequent on-chip test requirements of the delay line performance based on Ka-band phased array radar applications.

Figure 4 shows the circuit layout of the delay line based on the application of the Ka-band phased array radar in the implementation case of this application. The bias circuit of the delay line unit is separated on one side of the layout, which is convenient for subsequent on-chip testing. The three-stage delay line units are connected to each other through an impedance matching circuit to achieve the purpose of compact circuit layout and miniaturization, and is suitable for Ka-band phased array radar applications.

The above is only a preferred implementation case of the application, and is not intended to limit the scope of protection of the application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the technical solution of the application should be Included within the protection scope of this application.

Claims (8)

1. A delay line circuit layout based on Ka band phased array radar application, characterized in that a high electron mobility transistor is arranged on a gallium arsenide substrate. 2. A kind of delay line circuit layout based on Ka band phased array radar application according to claim 1, is characterized in that, described delay line is designed by three-stage delay line unit, passes impedance matching network between delay line unit to connect. 3. The circuit layout of a delay line based on Ka-band phased array radar application according to claim 1, wherein the delay line unit is composed of a pair of single-pole double-throw switches connected in series with a reference branch and a delay branch. 4. A kind of delay line circuit layout based on Ka-band phased array radar application according to claim 1, it is characterized in that, SPDT switch is made of symmetrical two pairs of high electron mobility transistors, and high electron mobility transistor gate The electrode is connected in series with a high resistance resistor and connected with a DC voltage source to form a DC voltage bias circuit. 5. a kind of delay line circuit layout based on Ka band phased array radar application according to claim 1, is characterized in that, the SPDT switch in the delay line unit is respectively by different DC bias voltage ( V _state1 , V _state2 ) to realize the selection of different radio frequency channels. 6. The circuit layout of a delay line based on Ka-band phased array radar application according to claim 1, wherein the reference branch in the delay unit is a simple transmission line or a "T" branch. 7. A kind of delay line circuit layout based on Ka band phased array radar application according to claim 1, it is characterized in that, delay branch selects the resonant unit that electric capacity and inductance form for use, and described resonant unit can be a plurality of; When designing different delay units, the corresponding delay purpose is achieved by adjusting the number of resonance units. 8. A semiconductor integrated circuit, characterized in that the semiconductor integrated circuit comprises a circuit layout based on the Ka-band phased array radar application according to any one of claims 1 to 7.