CN110534415A - A kind of more size grids and its manufacturing method - Google Patents

Abstract

The present invention provides a multi-size gate and its manufacturing method. In the multi-size gate manufacturing method, when forming a patterned gate film layer, a patterned first hard mask layer and a patterned The second hard mask layer is a mask, and the etching process is performed on the first region and the second region at the same time, so that the polymer material produced during the entire etching process is exactly the same, so these polymers have no effect on the subsequently formed gate. The shape of the process is affected, which reduces the difficulty of the process and improves the stability of the process.

Description

A multi-size grid and its manufacturing method

technical field

The invention relates to a method for manufacturing a semiconductor integrated circuit, in particular to a multi-size gate and a method for manufacturing the same.

Background technique

With the development of semiconductor technology, advanced logic chip technology has reached the technology process below 28nm node. Gate technology is the core technology of advanced logic chip technology. After entering the 28nm technology node, the gate technology has changed from a traditional polysilicon gate to a metal gate (MG) with a high dielectric constant (HK) gate dielectric layer, usually referred to as HKMG. . In the formation process of HKMG, it is necessary to generate a polysilicon dummy gate first, and then remove the polysilicon after filling the silicon oxide isolation layer, then fill it with metal, and finally form a multi-size gate (that is, gate last technology). The whole process is very complicated.

With the further shrinking of the chip size, for example, after entering the 14nm Finfet (Fin Field Effect Transistor) technology node, especially starting from the 12/10nm node, the pattern cycle of the polysilicon dummy gate shape has exceeded the traditional photolithography machine (such as is the exposure limit of the 193 immersion lithography machine), so the self-aligned double imaging technology (SADP: SelfAligned Double Patterning) was introduced to define the line pattern of the gate. However, the gate pattern formed by this technology The size of the electrode lines is single, and other process steps must be used to form gates of different sizes to meet the requirements of various devices on the chip. For example, in typical design methods, the gate line width and pattern period of the device area are the smallest. , and the gate line width required by the logic area is twice the gate line width of the device area, and the pattern period required by the logic area is also twice the pattern period of the device area. Therefore, in order to obtain gate lines of different sizes, SADP is usually used to form silicon oxide hard mask lines in the densely patterned device area, and then an organic composite barrier layer (tri-layer mask) is used to form an organic composite mask line pattern in the logic area. Then transfer the pattern to the silicon nitride hard mask layer by dry etching, and then use the silicon nitride hard mask layer as a mask to form final gate lines of different sizes, and finally form multi-size gates. The whole process has the following problems:

a. The process steps are more complicated;

b. The critical size of the gate in the logic area fluctuates greatly, which is not conducive to poor process stability;

c. The process is difficult, so that the gate pattern cannot be accurately copied, resulting in a narrow process window of the entire process, which is not conducive to process stability.

Contents of the invention

The purpose of the present invention is to provide a multi-size gate and its manufacturing method, which can optimize the process, improve the stability of the key dimensions of the gate in the logic region, reduce the difficulty of the process, and increase the process window, thereby reducing costs and improving process stability. .

In order to solve the above problems, the present invention provides a method for manufacturing a multi-size gate, comprising the following steps:

A substrate is provided, the substrate includes a first region and a second region, a gate film layer, a silicon material layer and a patterned first photoresist layer are formed on the substrate, and the patterned first photoresist layer The adhesive layer has a first pattern in the first area, a second pattern in the second area, the first pattern has a first opening, and the second pattern has a second opening;

Etching the silicon material layer using the patterned first photoresist layer as a mask, and copying the first pattern and the second pattern into the silicon material layer;

Forming a first hard mask layer on the substrate, the first hard mask layer covers the surface of the silicon material layer, and the sidewalls of the first opening and the second opening, and then etching the The first hard mask layer on the surface of the silicon material layer to form a patterned first hard mask layer;

Forming a patterned second photoresist layer on the substrate, and using the patterned second photoresist layer as a mask, etching and removing the first hard mask on the sidewall of the second opening Floor;

Form a second hard mask layer on the substrate, the second hard mask layer covers the surface of the silicon material layer, and the sidewalls of the first opening and the second opening, and then etch the the second hard mask layer on the surface of the silicon material layer to form a patterned second hard mask layer; and

Using the patterned first hard mask layer and the patterned second hard mask layer as a mask, sequentially etch the silicon material layer and the gate film layer, and stop the gate film layer at a partial depth In order to form a patterned gate film layer.

Optionally, a first hard mask layer is formed on the substrate, the first hard mask layer covers the surface of the silicon material layer and the sidewalls of the first opening and the second opening, and then Etching the first hard mask layer on the surface of the silicon material layer to form a patterned first hard mask layer includes the following steps:

Depositing a first hard mask layer with a uniform thickness on the substrate by using an ALD atomic layer deposition process, the first hard mask layer covers the surface of the silicon material layer, and the first opening and the second opening side walls of the

The first hard mask layer on the surface of the silicon material layer is etched by a dry etching process to form a patterned first hard mask layer.

Further, a patterned second photoresist layer is formed on the substrate, and the first hard layer on the sidewall of the second opening is etched and removed by using the patterned second photoresist layer as a mask. The mask layer includes the following steps:

Forming a second photoresist layer on the substrate

Using a KRF lithography machine to perform photoetching on the second photoresist layer using a double photolithography method to form a patterned second photoresist layer;

Using the patterned second photoresist layer as a mask, using a wet etching process to etch and remove the first hard mask layer on the sidewall of the second opening; and

The remaining second photoresist layer is removed by ashing and cleaning processes.

Further, a second hard mask layer is formed on the substrate, the second hard mask layer covers the surface of the silicon material layer, and the sidewalls of the first opening and the second opening, and then Etching the second hard mask layer on the surface of the silicon material layer to form a patterned second hard mask layer comprises the following steps:

Depositing a second hard mask layer with a uniform thickness on the substrate by using an ALD atomic layer deposition process, the second hard mask layer covers the surface of the silicon material layer, and the first opening and the second opening side walls of the

The second hard mask layer on the surface of the silicon material layer is etched by a dry etching process to form a patterned second hard mask layer.

Further, the thickness of the first hard mask layer is 16nm-20nm; the thickness of the second hard mask layer is 16nm-20nm.

Further, the first hard mask layer and the second hard mask layer have the same thickness.

Further, the material of the first hard mask layer includes silicon oxide and silicon oxynitride; the material of the second hard mask layer includes silicon oxide and silicon oxynitride.

Further, the first hard mask layer and the second hard mask layer are made of the same material.

Further, using the patterned first hard mask layer and the patterned second hard mask layer as masks, sequentially etch the silicon material layer and the gate film layer, and stop the gate at a partial depth. In the pole film layer, to form a patterned gate film layer specifically includes:

In the first region, using the patterned first hard mask layer and the patterned second hard mask layer as a mask, sequentially etch the silicon material layer and the gate film layer, and stop in the gate film layer at a partial depth; at the same time, in the second region, using the patterned second hard mask layer as a mask, sequentially etch the silicon material layer and the gate film layer, and stop in the gate film layer at a partial depth to form a patterned gate film layer.

The present invention also provides a multi-size grid, which is prepared by the above-mentioned manufacturing method.

Compared with the prior art, there are the following beneficial effects:

The present invention provides a multi-size gate and its manufacturing method. In the multi-size gate manufacturing method, when forming a patterned gate film layer, a patterned first hard mask layer and a patterned The second hard mask layer is a mask, and the etching process is performed on the first region and the second region at the same time, so that the materials of the polymers produced during the entire etching process are exactly the same, so these polymers have no effect on the subsequently formed gate. The morphology is affected, which reduces the difficulty of the process and improves the stability of the process.

Further, in the manufacturing method of the multi-size gate, the first hard mask layer and the second hard mask layer are formed by an ALD atomic layer deposition process, which can improve the first hard mask layer and the second hard mask layer. The uniformity of the mold layer, and when forming the patterned gate film layer, the first region uses the patterned first hard mask layer and the patterned second hard mask layer as a mask to perform an etching process, wherein , the material of the first hard mask layer and the second hard mask layer is the same, which reduces the difficulty of the etching process, and at the same time, the critical dimension of the gate subsequently formed in the first region is relatively stable, thereby improving the process quality . In addition, the patterned first photoresist layer is obtained by exposing the immersion photolithography exposure system, and the patterned second photoresist layer is obtained by using a KRF photolithography machine using a double photolithography method. Compared with the prior art Compared with the exposure process of the immersion lithography exposure system which adopts twice in the present invention, the process cost is lower.

Description of drawings

1a-1g are structural schematic diagrams in each step of a manufacturing method of a multi-size gate;

2 is a schematic flowchart of a method for manufacturing a multi-size gate according to an embodiment of the present invention;

3a-3j are structural schematic diagrams in each step of a method for manufacturing a multi-size gate according to an embodiment of the present invention.

Explanation of reference signs:

In Figures 1a-1g:

I-logic area; II-device area; 10-silicon substrate; 11-first polysilicon layer; 12-first oxide layer; 13-silicon nitride layer; 14-second polysilicon layer; 20- The second oxide layer; 30-the second composite organic layer barrier layer; 40-the second photoresist layer; a-opening;

In Figures 3a-3j:

I-first zone; II-second zone; a-first opening; b-second opening;

100-substrate; 110-gate film layer; 120-initial hard mask layer; 130-silicon material layer; 140-organic composite layer; 150-first photoresist layer;

200 - a first hard mask layer;

300-the second photoresist layer;

400 —Second hard mask layer.

Detailed ways

A conventional method for manufacturing a multi-size gate includes the following steps:

Step S11: Referring to FIG. 1a, a silicon substrate 10 is provided, and a first polysilicon layer 11, a first oxide layer 12, a silicon nitride layer 13, and a second polysilicon layer are sequentially formed on the silicon substrate 10. layer 14, a first composite organic layer barrier layer and a patterned first photoresist layer, the silicon substrate 10 includes a logic region I and a device region II, and the patterned first photoresist layer is in the Device region II has a second pattern, using the patterned first photoresist layer as a mask, sequentially etching the first composite organic barrier layer and the second polysilicon layer 14, and copying the second pattern into the second polysilicon layer 14 to form a patterned second polysilicon layer 14, and the patterned second polysilicon layer 14 has a second pattern at the device region II Opening a, and exposing the second polysilicon layer 14 in the logic region I, wherein the patterned first photoresist is exposed by using an immersion photolithography exposure system;

Step S12: Referring to FIG. 1b, a second oxide layer 20 is formed on the second polysilicon layer 14, and the second oxide layer 20 also covers the bottom and sidewall of the opening a;

Step S13: Referring to FIG. 1c, etch the second oxide layer 20 and the second polysilicon layer 14 in sequence, and retain the second oxide layer 20 on the sidewall of the opening a to form a second pattern, and forming a patterned second oxide layer 20;

Step S14: Please refer to FIG. 1d, forming a second composite organic layer barrier layer 30 on the silicon nitride layer 13, and forming a patterned second photolithography layer on the second composite organic layer barrier layer 30 in the logic region I. A glue layer 40, the second composite organic layer barrier layer 30 covers the second oxide layer 20, and the patterned second photoresist layer 40 has a first pattern in the logic region I;

Step S15: Please refer to FIG. 1e, use the patterned second photoresist layer 40 as a mask to etch the second composite organic layer barrier layer 30, and copy the first pattern to the second composite organic layer barrier layer 30 to form a patterned second composite organic barrier layer 30 while exposing the first pattern, wherein the patterned second photoresist layer 40 is obtained by exposure using an immersion photolithography exposure system;

Step S16: Please refer to FIG. 1f. In the logic region I, the silicon nitride layer 13 is further etched using the patterned second photoresist layer 40 and the second composite organic barrier layer 30 as a mask, and the The second pattern is copied to the silicon nitride layer 13, and in the device region II, the silicon nitride layer 13 is further etched using the second oxide layer 20 as a mask, and the first pattern is copied to In the silicon nitride layer 13, a patterned silicon nitride layer 13 is formed to expose the first oxide layer 12, and then the second oxide layer 20 and the second composite organic layer barrier layer 30 are removed; and

Step S17: Please refer to FIG. 1g, use the patterned silicon nitride layer 13 as a mask to further etch the first oxide layer 12 and the first polysilicon layer 11, and stop the etching at the first polysilicon layer In the polysilicon layer 11, the first pattern and the second pattern are copied to the first polysilicon layer 11 to form a gate pattern, and finally form a multi-size gate.

The inventors have found that, in the above-mentioned manufacturing method, two exposure processes using an immersion photolithography exposure system are required, and the process cost is relatively high. In the logic area of step S16, further etching with the patterned second photoresist layer and the composite organic barrier layer as a mask determines the critical dimension (CD, Critical Dimension) of the gate, due to its etching resistance Poor, so that the lateral etching rate is easily affected by the surrounding environment, resulting in large fluctuations in the critical dimension of the gate of the logic region, resulting in poor process stability. Simultaneously, in the logic region of step S16, in the further etching process using the patterned second photoresist layer and the composite organic barrier layer as a mask, the mask material is an organic material; The oxide layer is used as a mask for further etching. The mask material in this process is oxide. The polymer materials produced in the two regions during the entire etching process are completely different. These completely different polymers increase the transfer of pattern accuracy. The degree of difficulty (including precise size and vertical sidewall morphology) makes the size of the gate pattern inaccurate and/or the gate pattern has an inclination angle in the vertical direction, resulting in a narrow process window for the entire process and stable process Sex is poor.

Based on the above research, the present invention provides a multi-size gate and its manufacturing method. The core idea of the present invention is that, in the multi-size gate manufacturing method, when forming a patterned gate film layer, the patterned The first hard mask layer and the patterned second hard mask layer are masks, and the etching process is performed on the first region and the second region at the same time, so that the polymer material produced during the entire etching process is exactly the same, so , these polymers do not affect the morphology of the subsequently formed gate, which reduces the difficulty of the process and improves the stability of the process.

Further, in the manufacturing method of the multi-size gate, the first hard mask layer and the second hard mask layer are formed by an ALD atomic layer deposition process, which can improve the first hard mask layer and the second hard mask layer. The uniformity of the mold layer, and when forming the patterned gate film layer, the first region uses the patterned first hard mask layer and the patterned second hard mask layer as a mask to perform an etching process, wherein , the material of the first hard mask layer and the second hard mask layer is the same, which reduces the difficulty of the etching process, and at the same time, the critical dimension of the gate subsequently formed in the first region is relatively stable, thereby improving the process quality . In addition, the patterned first photoresist layer is obtained by exposing the immersion photolithography exposure system, and the patterned second photoresist layer is obtained by using a KRF photolithography machine using a double photolithography method. Compared with the prior art Compared with the exposure process of the immersion lithography exposure system which adopts twice in the present invention, the process cost is lower.

A multi-size gate and its manufacturing method of the present invention will be further described in detail below. The invention will now be described in more detail with reference to the accompanying drawings, in which preferred embodiments of the invention are shown, it being understood that those skilled in the art may modify the invention described herein and still achieve the advantageous effects of the invention. Therefore, the following description should be understood as the broad knowledge of those skilled in the art, but not as a limitation of the present invention.

In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions and constructions are not described in detail since they would obscure the invention with unnecessary detail. It should be appreciated that in the development of any actual embodiment, numerous implementation details must be worked out to achieve the developer's specific goals, such as changing from one embodiment to another in accordance with system-related or business-related constraints. Additionally, it should be recognized that such a development effort might be complex and time consuming, but would nevertheless be merely a routine undertaking for those skilled in the art.

In order to make the purpose and features of the present invention more comprehensible, the specific implementation manners of the present invention will be further described below in conjunction with the accompanying drawings. It should be noted that the drawings are all in a very simplified form and use imprecise ratios, which are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

This embodiment provides a method for manufacturing a multi-size gate. FIG. 2 is a schematic flowchart of a method for manufacturing a multi-size gate in this embodiment. As shown in Figure 2, the manufacturing method comprises the following steps:

Step S21: providing a substrate, the substrate includes a first region and a second region, a gate film layer, a silicon material layer and a patterned first photoresist layer are formed on the substrate, and the patterned first A photoresist layer has a first pattern in the first area, a second pattern in the second area, the first pattern has a first opening, and the second pattern has a second opening;

Step S22: using the patterned first photoresist layer as a mask, etching the silicon material layer, and copying the first pattern and the second pattern into the silicon material layer;

Step S23: forming a first hard mask layer on the substrate, the first hard mask layer covers the surface of the silicon material layer, and the sidewalls of the first opening and the second opening, and then engraving etching the first hard mask layer on the surface of the silicon material layer to form a patterned first hard mask layer;

Step S24: forming a patterned second photoresist layer on the substrate, and using the patterned second photoresist layer as a mask, etching and removing the first layer on the sidewall of the second opening. hard mask layer;

Step S25: forming a second hard mask layer on the substrate, the second hard mask layer covers the surface of the silicon material layer and the sidewalls of the first opening and the second opening, and then engraving etching the second hard mask layer on the surface of the silicon material layer to form a patterned second hard mask layer; and

Step S26: Using the patterned first hard mask layer and the patterned second hard mask layer as masks, sequentially etch the silicon material layer and the gate film layer, and stop the gate at a partial depth. In the pole film layer, to form a patterned gate film layer.

The manufacturing method of the multi-size gate of the present invention will be described in detail below with reference to specific embodiments and FIGS. 3a-3j.

As shown in FIG. 3a, step S21 is first performed to provide a substrate 100, which includes a first region I and a second region II, and a gate film layer 110, a silicon material layer 130 and a pattern are formed on the substrate 100. A patterned first photoresist layer 150, the patterned first photoresist layer 150 has a first pattern in the first region I, a second pattern in the second region II, and the first pattern has a first opening a , the second pattern has a second opening b. An initial hard mask layer 120 and a composite organic barrier layer 140 are also formed on the substrate 100, the initial hard mask layer 120 is located between the gate film layer 110 and the silicon material layer 130, and the composite organic layer A layer blocking layer 140 is formed between the silicon material layer 130 and the patterned first photoresist layer 150 .

This step specifically includes the following steps:

Specifically, firstly, a substrate 100 is provided, and a gate film layer 110 , an initial hard mask layer 120 , a silicon material layer 130 and an organic composite layer 140 are sequentially formed on the substrate 100 . In this embodiment, the substrate 100 is a planar substrate, and the material of the substrate 100 is a silicon substrate, a silicon-germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, glass substrate or a III-V compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate, etc.). In another embodiment, the base includes a substrate and a fin located on the surface of the substrate, and may further include: an isolation layer located on the surface of the base, the isolation layer covers part of the sidewalls of the fin, and the isolation The surface of the layer is lower than the top surface of the fin. The subsequently formed gate film covers the top surface and the sidewall surface of the fin, and the gate film also covers the surface of the isolation layer.

The substrate 100 includes several first regions I and several second regions II. The first regions I are, for example, logic regions with relatively sparse patterns, and the second regions II are, for example, device regions with relatively dense patterns, such as memory storage area, etc. The gate film layer 110 provides a process basis for the subsequent gate formation; the material of the gate film layer 110 is polysilicon or doped polysilicon; the gate film layer 110 adopts chemical vapor deposition method, physical vapor deposition method Or formed by atomic layer deposition. There is also a gate dielectric film (not shown in the figure) on the substrate 100, and the gate dielectric film is used for subsequent formation of a gate dielectric layer; the material of the gate dielectric film is silicon oxide, silicon nitride or silicon oxynitride. The initial hard mask layer 120 and the silicon material layer 130 provide a process basis for the subsequent formation of a gate pattern layer. The material of the initial hard mask layer 120 is one or a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride or amorphous carbon; the silicon material layer 130 The material is monocrystalline silicon, polycrystalline silicon or amorphous silicon. In this embodiment, the initial hard mask layer 120 includes a silicon oxide layer and a silicon nitride layer sequentially formed on the gate film layer 110; the material of the silicon material layer 130 is polysilicon. The thickness of the silicon oxide layer is The thickness of the silicon nitride layer is The thickness of the silicon material layer 130 is The organic composite layer 140 includes, but is not limited to, an organic material layer (Spin-on-Coating, SOC) and a silicon-containing anti-reflective coating (Silicon_Containing-Anti_Reflective-Coating-Layer, SiARC). The thickness of the organic material layer is The thickness of the silicon-containing anti-reflection coating is

Next, form a first photoresist layer 150 on the organic composite layer 140, and expose the first photoresist layer 150 using an immersion photolithography exposure system to form a patterned first photoresist layer 150 . The patterned first photoresist layer 150 has a first pattern in the first region I and a second pattern in the second region II, the first pattern has a first opening a, and the second pattern has a second opening b.

Wherein, the thickness of the first photoresist layer 150 is

As shown in FIG. 3b, step S22 is then performed, using the patterned first photoresist layer 150 as a mask to sequentially etch the composite organic barrier layer 140 and the silicon material layer 130, and the first A pattern and a second pattern are replicated into the silicon material layer 130 .

In this step, the patterned silicon material layer 130 exposes the initial hard mask layer 120 directly under the first opening a and the second opening b.

Next, the remaining organic composite layer 140 is removed by ashing and cleaning processes.

As shown in FIG. 3c and FIG. 3d, step S23 is then performed to form a first hard mask layer 200 on the substrate 100, the first hard mask layer 200 covers the surface of the silicon material layer 130, and The sidewalls of the first opening a and the second opening b, and then etch the first hard mask layer 200 on the surface of the silicon material layer 130 to form a patterned first hard mask layer 200 .

This step specifically includes the following steps:

As shown in FIG. 3c, first, a first hard mask layer 200 with a uniform thickness is deposited on the substrate 100 using an ALD (Atomic Layer Deposition) atomic layer deposition process, that is, the formed first hard mask layer 200 is formed at different positions. The thickness deviation of the first hard mask layer 200 is relatively small, for example, less than 3%, and this process can improve the uniformity of the first hard mask layer 200, so that the critical dimension of the subsequently formed gate is relatively stable. It can be seen that at this time, the first hard mask layer 200 not only covers the upper surface of the silicon material layer 130 , but also covers the sidewalls and bottoms of the opening a and the second opening b. Wherein, the material of the first hard mask layer 200 includes, for example, one or a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride or amorphous carbon. The thickness of the first hard mask layer 200 is 16nm-20nm.

As shown in FIG. 3 d , next, the first hard mask layer 200 on the surface of the silicon material layer 130 is etched by a dry etching process to form a patterned first hard mask layer 200 .

In this step, the first hard mask layer 200 on the surface of the silicon material layer 130 is etched, and the surface of the silicon material layer 130 covered by the first hard mask layer 200 is exposed, and the Out of the initial hard mask layer 120 at the groove bottom of the first opening a and the second opening b, part of the height of the first hard mask on the side walls of the first opening a and the second opening b is reserved. mold layer 200 .

As shown in FIG. 3e and FIG. 3f, step S24 is then performed to form a patterned second photoresist layer 300 on the substrate 100, and use the patterned second photoresist layer 300 as a mask to etch etch the first hard mask layer 200 on the sidewall of the second opening b, and retain the silicon material layer 130 in the second region II.

This step specifically includes:

First, as shown in FIG. 3e, a second photoresist layer 300 is formed on the substrate 100, the second photoresist layer 300 is KRF photoresist, and the thickness of the second photoresist layer 300 is

Next, for example, the second photoresist layer 300 is photoetched using a KRF photolithography machine using a double photolithography method to form a patterned second photoresist layer 300. Compared with the exposure process of the immersion lithography exposure system, its process cost is lower. At this time, the patterned second photoresist layer 300 exposes the second region II and covers the first region I.

Next, as shown in FIG. 3f, using the patterned second photoresist layer 300 as a mask, for example, wet etching the first hard mask layer 200 of the second region II by using DHF solution, to The first hard mask layer 200 on the sidewall of the second opening b in the second region II is removed. Since the DHF solution hardly consumes the silicon material layer 130 and the initial hard mask layer 120 , the morphology of the second opening b is hardly affected. At this time, the first hard mask layer 200 of the second region II is removed, and the first hard mask layer 200 of the first region I remains.

Next, the remaining second photoresist layer 300 is removed by ashing and cleaning processes.

As shown in FIG. 3g and FIG. 3h, step S25 is then performed to form a second hard mask layer 400 on the substrate 100, the second hard mask layer 400 covers the surface of the silicon material layer 130, and The sidewalls of the first opening a and the second opening b are then etched to form the second hard mask layer 400 on the surface of the silicon material layer 130 to form a patterned second hard mask layer 400 .

In this step, as shown in FIG. 3g, first, a second hard mask layer 400 with a uniform thickness is deposited on the substrate 100 by using an ALD (Atomic Layer Deposition) atomic layer deposition process, which can improve the second hard mask. The uniformity of the layer 400 further makes the critical dimension of the subsequently formed gate more stable. It can be seen that at this time, the second hard mask layer 400 not only covers the upper surface of the silicon material layer 130 , but also covers the sidewalls and bottoms of the opening a and the second opening b. Wherein, the material of the second hard mask layer 400 includes, for example, one or a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride or amorphous carbon. The thickness of the second hard mask layer 400 is 16nm-20nm. Preferably, the first hard mask layer 200 and the second hard mask layer 400 have the same thickness, so that the thickness of the first hard mask layer 200 and the second hard mask layer 400 on the sidewall of the opening a The total thickness is twice the thickness of the second hard mask layer 400 on the sidewall of the second opening b, so that the gate line width formed under the sidewall of the opening a is equal to that formed under the sidewall of the second opening b. 2 times the width of the gate line. The first hard mask layer 200 and the second hard mask layer 400 are made of the same material, such as silicon oxide or silicon oxynitride.

Next, as shown in FIG. 3h , the second hard mask layer 400 on the surface of the silicon material layer 130 is etched by a dry etching process to form a patterned second hard mask layer 400 .

In this step, the second hard mask layer 400 on the surface of the silicon material layer 130 is etched, and the surface of the silicon material layer 130 covered by the second hard mask layer 400 is exposed, and the The initial hard mask layer 120 protrudes from the groove bottom of the first opening a and the second opening b, and part of the height of the first hard mask layer 200 and the second hard mask layer 200 on the sidewall of the first opening a are reserved Two hard mask layers 400, and part of the height of the second hard mask layer 400 on the sidewall of the second opening b.

As shown in FIG. 3i and FIG. 3j, step S26 is then performed, using the patterned first hard mask layer 200 and the patterned second hard mask layer 400 as masks to etch the silicon material layer 130 , the initial hard mask layer 120 and the gate film layer 110, and stop in the gate film layer at a partial depth to form a patterned gate film layer. It can be seen that in this step, since the first hard mask layer 200 and the second hard mask layer 400 are made of silicon, the materials of the polymers produced during this etching process are the same, so these polymers have no effect on the subsequent formation. The shape of the gate is affected, which reduces the difficulty of the process and improves the stability of the process.

In this step, in the first region I, the silicon material layer is etched using the patterned first hard mask layer 200 and the patterned second hard mask layer 400 as masks. 130. Initial hard mask layer 120 and gate film layer 110; in the second region II, using the patterned second hard mask layer 400 as a mask, etch the silicon material layer 130, initial hard mask layer 120 and gate film layer 110 .

This step specifically includes: as shown in FIG. 3i, first, etching and removing the silicon material layer 130; as shown in FIG. 3j, then, using the first hard mask layer 200 and the second hard mask layer 400 as mask, etch the initial hard mask layer 120 and the gate film layer 110, and stop in the gate film layer at a partial depth to form a patterned gate film layer.

This embodiment also provides a multi-size gate, which is prepared by the above-mentioned manufacturing method.

In summary, the present invention provides a multi-size gate and its manufacturing method. The manufacturing method of the multi-size gate includes the following steps: providing a substrate, the substrate includes a first region and a second region, the A gate film layer, a silicon material layer, and a patterned first photoresist layer are formed on the substrate, and the patterned first photoresist layer has a first pattern in the first region and a first pattern in the second region. Two patterns, the first pattern has a first opening, and the second pattern has a second opening; using the patterned first photoresist layer as a mask, etch the silicon material layer, and place the first pattern and the second pattern are copied into the silicon material layer; a first hard mask layer is formed on the substrate, the first hard mask layer covers the surface of the silicon material layer, and the first opening and the sidewall of the second opening, and then etch the first hard mask layer on the surface of the silicon material layer to form a patterned first hard mask layer; form a patterned first hard mask layer on the substrate Two photoresist layers, and using the patterned second photoresist layer as a mask, etch to remove the first hard mask layer on the sidewall of the second opening; form a second hard mask layer on the substrate A hard mask layer, the second hard mask layer covers the surface of the silicon material layer, and the sidewalls of the first opening and the second opening, and then etches the silicon material layer on the surface second hard mask layer to form a patterned second hard mask layer; and using the patterned first hard mask layer and the patterned second hard mask layer as masks to etch the silicon in sequence material layer and the gate film layer, and stop in the gate film layer at a partial depth to form a patterned gate film layer. The present invention uses the patterned first hard mask layer and the patterned second hard mask layer as masks to simultaneously etch the first region and the second region when forming the patterned gate film layer The process makes the materials of the polymers produced in the whole etching process exactly the same, therefore, these polymers do not affect the morphology of the subsequently formed gate, which reduces the difficulty of the process and improves the stability of the process.

Further, in the manufacturing method of the multi-size gate, the first hard mask layer and the second hard mask layer are formed by an ALD atomic layer deposition process, which can improve the first hard mask layer and the second hard mask layer. The uniformity of the mold layer, and when forming the patterned gate film layer, the first region uses the patterned first hard mask layer and the patterned second hard mask layer as a mask to perform an etching process, wherein , the material of the first hard mask layer and the second hard mask layer is the same, which reduces the difficulty of the etching process, and at the same time, the critical dimension of the gate subsequently formed in the first region is relatively stable, thereby improving the process quality . In addition, the patterned first photoresist layer is obtained by exposing the immersion photolithography exposure system, and the patterned second photoresist layer is obtained by using a KRF photolithography machine using a double photolithography method. Compared with the prior art Compared with the exposure process of the immersion lithography exposure system which adopts twice in the present invention, the process cost is lower.

In addition, it should be noted that, unless otherwise specified or pointed out, the descriptions of the terms "first", "second", etc. in the specification are only used to distinguish each component, element, step, etc. in the specification, rather than to express The logical relationship or sequential relationship between various components, elements, and steps, etc.

It can be understood that although the present invention has been disclosed above with preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or be modified to be equivalent to equivalent changes. Example. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention, which do not deviate from the technical solution of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims (10)

1. A method for manufacturing a multi-size gate, comprising the following steps: A substrate is provided, the substrate includes a first region and a second region, a gate film layer, a silicon material layer and a patterned first photoresist layer are formed on the substrate, and the patterned first photoresist layer The adhesive layer has a first pattern in the first area and a second pattern in the second area, the first pattern has a first opening, and the second pattern has a second opening; Using the patterned first photoresist layer as a mask, etching the silicon material layer, and copying the first pattern and the second pattern into the silicon material layer; Forming a first hard mask layer on the substrate, the first hard mask layer covers the surface of the silicon material layer, and the sidewalls of the first opening and the second opening, and then etching the The first hard mask layer on the surface of the silicon material layer to form a patterned first hard mask layer; Forming a patterned second photoresist layer on the substrate, and using the patterned second photoresist layer as a mask, etching and removing the first hard mask on the sidewall of the second opening Floor; Form a second hard mask layer on the substrate, the second hard mask layer covers the surface of the silicon material layer, and the sidewalls of the first opening and the second opening, and then etch the the second hard mask layer on the surface of the silicon material layer to form a patterned second hard mask layer; and Using the patterned first hard mask layer and the patterned second hard mask layer as a mask, sequentially etch the silicon material layer and the gate film layer, and stop the gate film layer at a partial depth In order to form a patterned gate film layer. 2. The manufacturing method according to claim 1, wherein a first hard mask layer is formed on the substrate, the first hard mask layer covers the surface of the silicon material layer, and the The sidewalls of the first opening and the second opening, and then etching the first hard mask layer on the surface of the silicon material layer to form a patterned first hard mask layer include the following steps: Depositing a first hard mask layer with a uniform thickness on the substrate by using an ALD atomic layer deposition process, the first hard mask layer covers the surface of the silicon material layer, and the first opening and the second opening side walls of the The first hard mask layer on the surface of the silicon material layer is etched by a dry etching process to form a patterned first hard mask layer. 3. The manufacturing method according to claim 2, wherein a patterned second photoresist layer is formed on the substrate, and the patterned second photoresist layer is used as a mask for etching Removing the first hard mask layer on the sidewall of the second opening comprises the following steps: Forming a second photoresist layer on the substrate Using a KRF lithography machine to perform photoetching on the second photoresist layer using a double photolithography method to form a patterned second photoresist layer; Using the patterned second photoresist layer as a mask, using a wet etching process to etch and remove the first hard mask layer on the sidewall of the second opening; and The remaining second photoresist layer is removed by ashing and cleaning processes. 4. The manufacturing method according to claim 3, wherein a second hard mask layer is formed on the substrate, the second hard mask layer covers the surface of the silicon material layer, and the The sidewalls of the first opening and the second opening, and etching the second hard mask layer on the surface of the silicon material layer to form a patterned second hard mask layer include the following steps: Depositing a second hard mask layer with a uniform thickness on the substrate by using an ALD atomic layer deposition process, the second hard mask layer covers the surface of the silicon material layer, and the first opening and the second opening side walls of the The second hard mask layer on the surface of the silicon material layer is etched by a dry etching process to form a patterned second hard mask layer. 5. The manufacturing method according to claim 2 or 4, wherein the thickness of the first hard mask layer is 16nm-20nm; the thickness of the second hard mask layer is 16nm-20nm. 6. The manufacturing method according to claim 5, wherein the first hard mask layer and the second hard mask layer have the same thickness. 7. The manufacturing method according to claim 6, wherein the material of the first hard mask layer comprises silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride or One or a combination of amorphous carbon; the material of the second hard mask layer includes one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride or amorphous carbon species or combinations. 8. The manufacturing method according to claim 7, wherein the first hard mask layer and the second hard mask layer are made of the same material. 9. The manufacturing method according to claim 8, wherein, using the patterned first hard mask layer and the patterned second hard mask layer as a mask, the silicon material layer and the gate layer are sequentially etched. Pole film layer, and stop in the described gate film layer of partial depth, to form patterned gate film layer specifically include: In the first region, using the patterned first hard mask layer and the patterned second hard mask layer as a mask, sequentially etch the silicon material layer and the gate film layer, and stop in the gate film layer at a partial depth; at the same time, in the second region, using the patterned second hard mask layer as a mask, sequentially etch the silicon material layer and the gate film layer, and stop in the gate film layer at a partial depth to form a patterned gate film layer. 10. A multi-size grid, characterized in that it is prepared by the manufacturing method according to any one of claims 1-9.