CN110543439B - Signal processing system - Google Patents

Abstract

The invention discloses a signal processing system, comprising: an input interface, a field programmable gate array module, and at least two output interfaces; the field programmable gate array module receives an input signal of external equipment through an input interface; the field programmable gate array module is used for detecting the interface type of the input signal, converting the input signal into a standard signal in a preset format if the interface type is a preset type, and outputting the standard signal through the first output interface; and if the interface type is a non-preset type, outputting an input signal through the second output interface. According to the technical scheme, the input signals are selectively processed according to the interface types, the input signals of the interfaces of the preset type are output after being converted, the input signals of the interfaces of the non-preset type are directly output from different output interfaces, the input signals of the two types of interfaces are respectively processed, and the efficiency of signal format conversion is improved.

Description

a signal processing system

technical field

Embodiments of the present invention relate to the technical field of signal processing, and in particular, to a signal processing system.

Background technique

In the process of collecting and integrating signals from different devices, the signals from different devices are required to have the same format for easy identification and processing. However, in practical applications, the formats of signals of different devices are usually inconsistent. For example, when signals from eye trackers and motion capture devices are input to the EEG for integration, the signals input from the eye tracker and motion capture devices have their own formats and time stamps. For example, the input signals may include cyclic signals, frequency Fixed continuous clock signals, continuous high-level signals, etc. These input signals in different formats cannot be directly recognized and used by the EEG, but need to be converted into standard format signals before further processing.

The existing signal format conversion method converts all the collected signals, and cannot selectively process the input signal, resulting in high delay and low efficiency of signal format conversion.

Contents of the invention

The invention provides a signal processing system to improve the efficiency of signal format conversion.

An embodiment of the present invention provides a signal processing system, including:

An input interface, a field programmable gate array module and at least two output interfaces, the field programmable gate array module is connected to the input interface and the output interface respectively; the field programmable gate array module passes through the input interface Receive input signals from external devices;

The field programmable gate array module is used to detect the interface type of the input signal, if the interface type is a preset type, convert the input signal into a standard signal in a preset format, and pass the first output interface Outputting the standard signal; if the interface type is not a preset type, outputting the input signal through a second output interface.

The field programmable gate array module is specifically used to detect whether the input signal matches a preset format, and if not, mark the interface type of the input interface as a preset type.

Further, there are at least two input interfaces, and the field programmable gate array module includes:

an interface identification identification unit, configured to identify the interface identification of the input interface corresponding to the input signal;

An interface type identifying unit, configured to determine the interface type according to the mapping relationship between the interface identifier and the interface type.

Further, the field programmable gate array module also includes:

a signal extraction unit, configured to extract the high level that appears for the first time in the input signal;

a signal adjustment unit, configured to adjust the duration of the high level to a preset duration to obtain the standard signal;

The first signal output unit is configured to output the standard signal through the first output interface.

Further, the input signal includes at least two level signals, and the field programmable gate array module further includes:

A signal decoding unit, configured to decode the input signal into at least two parallel standard signals in a preset format;

The second signal output unit is configured to output parallel standard signals through the first output interface.

Further, the signal decoding unit is specifically used for:

Extracting the high level that appears for the first time in each level signal in the input signal;

The duration of each high level is adjusted to a preset duration to obtain the standard signal.

An embodiment of the present invention provides a signal processing system, including: an input interface, a field programmable gate array module and at least two output interfaces, the field programmable gate array module is connected to the input interface and the output interface respectively; The module receives the input signal of the external device through the input interface; the field programmable gate array module is used to detect the interface type of the input signal, if the interface type is the preset type, the input signal is converted into a standard signal of the preset format, and passed through the first An output interface outputs a standard signal; if the interface type is a non-preset type, the input signal is output through the second output interface. The above technical solution selectively processes the input signal according to the interface type, converts the input signal of the preset type interface and outputs it, and directly outputs the input signal of the non-preset type interface from different output interfaces, realizing the realization of the two types of interface The separate processing of the input signal improves the efficiency of signal format conversion.

Description of drawings

FIG. 1 is a schematic structural diagram of a signal processing system provided by Embodiment 1 of the present invention;

FIG. 2 is a schematic diagram of the principle of a signal processing system provided by Embodiment 1 of the present invention;

FIG. 3 is a schematic structural diagram of a signal processing system provided by Embodiment 2 of the present invention;

FIG. 4 is a schematic diagram of an input signal in Embodiment 2 of the present invention;

FIG. 5 is a schematic diagram of output signals in Embodiment 2 of the present invention.

Detailed ways

The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, but not to limit the present invention. In addition, it should be noted that, for the convenience of description, only some structures related to the present invention are shown in the drawings but not all structures.

Embodiment one

FIG. 1 is a schematic structural diagram of a signal processing system provided by Embodiment 1 of the present invention. This embodiment is applicable to the situation where the input signal of the external device is processed to ensure that it conforms to a standard format for direct identification and utilization by other devices. Specifically, as shown in Figure 1, the system includes: an input interface 10, a field programmable gate array module 20 and at least two output interfaces 30, and the field programmable gate array module 20 is connected to the input interface 10 and the output interface 30 respectively; Field programmable gate array module 20 receives the input signal of external equipment through input interface 10; Field programmable gate array module 20 is used for detecting the interface type of input signal, if interface type is preset type, then input signal is converted into preset format, and output the standard signal through the first output interface 31; if the interface type is not a preset type, then output the input signal through the second output interface 32.

Specifically, the interface type is the preset type means that the input signal input by the interface does not conform to the preset format and needs to be output after format conversion; the non-preset type means that the input signal input by the interface conforms to the preset format. format, which can be output directly. It should be noted that there may be one or more first output interfaces 31 and second output interfaces 32 respectively. In this embodiment, the first output interface 31 refers to a type of interface for outputting converted standard signals, and the second output interface 32 refers to a type of interface for directly outputting an input signal input by an interface of a non-preset type.

In this embodiment, the first output interface 31 and the second output interface 32 can be soft-defined. For example, without dismantling the device, which output interfaces are the first output interface 31 and which output interfaces are the second output interface 32 can be predefined by means of soft definition, which can be specifically defined according to actual needs. In this case, the system also includes an interface for upgrading the firmware.

Optionally, there are at least two input interfaces 10, and the system can be used to synchronously process the trigger signal (Trigger Signal) of each input interface 10.

Optionally, the field programmable gate array module 20 is specifically used to detect whether the input signal matches the preset format, and if not, mark the interface type of the input interface 10 as the preset type.

Specifically, the interface type of the input interface 10 may be marked by the field programmable gate array module 20 . For example, there are five input interfaces in the signal processing system, and input interface 1 has received an input signal provided by an external device. At this time, the field programmable gate array module 20 detects that the input signal does not match the preset format, and the input interface 101 is marked as a preset type, and the input signal of the interface of the preset type is converted into a standard signal of the preset format and output through the first output interface 31 . As another example, input interface 2 receives an input signal provided by an external device, and the field programmable gate array module 20 detects that the input signal matches a preset format, then marks input interface 2 as a non-preset type, and for a non-preset type The input signal of the interface is directly output through the second output interface 32.

Optionally, the interface type of the input interface 10 may also be preset. After detecting the input signal, the FPGA module 20 identifies the interface type of the input interface 10 where the input signal is located for signal processing. For example, the input interface 3 is a preset type of interface. When the FPGA module 20 detects the input signal of the input interface 3 , it converts it into a standard signal and outputs it from the first output interface 31 .

Optionally, when there are few types of external equipment, commonly used equipment, and the types of input signals are relatively fixed, the interface type can be preset, and various input signals are input from the corresponding input interface 10, and the field programmable gate array module 20 After receiving the input signal, there is no need to judge the format of the input signal. The interface type can be determined by identifying the number and logo of the interface, and the signal processing is performed accordingly to improve the conversion efficiency. When there are many types of external devices, which are not commonly used, and the types of input signals are complex and changeable, the interface type of the input interface 10 is marked by the field programmable gate array module 20 according to the actually received input signal, and the actually received input If the signal does not match the preset format, it will be marked as the preset type and format converted, otherwise it will be marked as the non-preset type, so that for various input signals, it can ensure that every signal that does not match the preset format can be identified and improved. reliability.

FIG. 2 is a schematic diagram of a signal processing system provided by Embodiment 1 of the present invention. As shown in Figure 2, the input interface can be multiple; the field programmable gate array (Field-Programmable Gate Array, FPGA) module is used as the control module of signal processing; the output interface can be multiple, wherein, Parallel 1 to n are used for Output a separate signal, Serial 1-1 to 1-n can be used to output multiple parallel signals obtained after decoding a data packet. It should be noted that when there is only one input interface, the interface type is not preset, but the FPGA module identifies the interface type of the input interface after each input signal is detected.

Embodiment 1 of the present invention provides a signal processing system. Detect the interface type of the input signal through the field programmable gate array module, convert the input signal of the interface of the preset type into a standard signal of the preset format, and output it through the first output interface, and convert the input signal of the interface of the non-preset type The input signal is directly output through the second output interface, which reduces the delay of signal processing; the input signal is selectively processed according to the interface type, realizing the separate processing of the input signals of the two types of interfaces, and improving the efficiency of signal format conversion.

Embodiment two

FIG. 3 is a schematic structural diagram of a signal processing system provided by Embodiment 2 of the present invention. This embodiment is optimized on the basis of the above embodiments, and specifically describes the interface type for detecting the input signal and the conversion process of the input signal. For technical details not exhaustively described in this embodiment, reference may be made to any of the foregoing embodiments.

As shown in FIG. 3 , there are at least two input interfaces 10 . The FPGA module 20 includes: an interface identification unit 21 for identifying the interface identification of the input interface corresponding to the input signal; an interface type identification unit 22 for determining the interface type according to the mapping relationship between the interface identification and the interface type.

Specifically, in this embodiment, the interface type of the input interface 10 is preset, and the mapping relationship data between the interface identifier and the interface type is stored in the system. After the input signal is detected, the interface identification is identified by the interface identification identification unit 21, and the corresponding interface type is determined by reading the mapping relation data by the interface type identification unit 22.

Further, the field programmable gate array module 20 also includes: a signal extraction unit 23, which is used to extract the first high level in the input signal; a signal adjustment unit 24, which is used to adjust the duration of the high level to a predetermined Set the duration to obtain a standard signal; the first signal output unit 25 is configured to output the standard signal through the first output interface 31 .

Specifically, the signal extraction unit 23 and the signal adjustment unit 24 are used to convert the input signal into a standard signal conforming to a preset format. In this embodiment, the preset format can be that the first high level in the input signal lasts for 1 second, that is, the standard signal only has a high level for 1 second, corresponding to the first high level in the input signal. Flat position, so as to realize the conversion of the signal format to meet the requirements of a unified time format. For example, after the input signals from different external devices are converted into standard signals, the position (or time) where the first high level appears in the signal source can be directly identified according to the standard signals and the corresponding data can be read.

Further, the input signal includes at least two level signals, and the field programmable gate array module 20 also includes: a signal decoding unit 26, which is used to decode the input signal into at least two parallel standard signals in a preset format; the second signal The output unit 27 is configured to output parallel standard signals through the first output interface 31 .

Specifically, the input signal is a data packet including at least two level signals, and the signal decoding unit 26 is used to decode the data packet into a standard signal of a parallel preset format during the format conversion process, and the second signal output unit 27 uses These parallel standard signals are output from different first output interfaces 31 to obtain multiple output signals, and the decoding and conversion are performed synchronously to improve the efficiency of format conversion.

Further, the signal decoding unit 26 is specifically used to: extract the high level that appears for the first time in each level signal in the input signal; adjust the duration of each high level to a preset duration to obtain a parallel standard signal . In this embodiment, the signal decoding unit 26 respectively converts each level signal in the data packet to obtain parallel standard signals.

The signal processing process is described below through an example. Table 1 is a mapping relationship between input signals and output signals. As shown in Table 1, the input signals corresponding to different input interfaces may be different, and the corresponding output interfaces may also be different. Among them, the input signals from Parallel 1 to Parallel n are separate level signals, while the input signals of Serial 1 and Serial n If the signal is a data packet, in the process of converting the signal in the data packet into a standard signal with a preset format, it is decoded to obtain a parallel signal, which is output in parallel from multiple output interfaces. The rule of converting to the preset format is to collect the first high level and last for 1 second.

Table 1 Mapping relation between input signal and output signal

It should be noted that the preset format can be set according to actual needs. The function of the signal processing system is to process the input signals provided by various external devices, and output standard signals conforming to the preset format, which can be recognized and processed by specific devices. , this embodiment does not limit the specific content and setting method of the preset rule.

FIG. 4 is a schematic diagram of input signals in Embodiment 2 of the present invention. As shown in Figure 4, the input signals corresponding to the input interfaces Parallel 1 to Parallel n are all separate level signals, and the input signals corresponding to Serial 1 and Serial n are data packets.

FIG. 5 is a schematic diagram of output signals in Embodiment 2 of the present invention. Take the input signal of Parallel 1 in Figure 4 as an example. The input signal is a cycle signal with a high level for 1 second and a low level for 9 seconds. The second has a high level of 1 second, corresponding to the position of the first high level in the original input signal, so as to realize the conversion of the signal format. For the packet input signal shown in Serial 1 in Figure 4, after conversion, the parallel signals shown in Serial 1-1 to 1-n in Figure 5 are obtained.

Optionally, the field programmable gate array module 20 is constituted by an FPGA minimum system. FPGA minimum system includes: chip, power supply, external clock, reset circuit, download and debug circuit, and memory. The minimum system configuration of the FPGA is that the input signal conforming to the preset format will be directly output, and the input signal not conforming to the preset format will be output from the corresponding output interface after being converted. At the same time, the serial signal can be decoded into multiple channel parallel signals.

The signal processing system provided by the second embodiment of the present invention is optimized on the basis of the above-mentioned embodiment, and the interface type of the input signal is detected by the FPGA module, which can realize the rapid judgment and selection of the input signal, and the preset type The input signal input by the interface is converted, and the input signal input by other interface is directly output, and the serial signal can be decoded into a parallel signal during the conversion process, and the conversion and decoding can be realized by using fewer digital devices, and the signal format conversion is improved. s efficiency.

Note that the above are only preferred embodiments of the present invention and applied technical principles. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, rearrangements and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and can also include more other equivalent embodiments without departing from the concept of the present invention, and the present invention The scope is determined by the scope of the appended claims.

Claims (4)

1. A signal processing system, characterized in that, comprising: an input interface, a Field Programmable Gate Array module and at least two output interfaces, and the Field Programmable Gate Array module is connected to the input interface and the output interface respectively ; The field programmable gate array module receives an input signal from an external device through the input interface; wherein, there are at least two input interfaces; The field programmable gate array module is used to detect the interface type of the input signal, if the interface type is a preset type, convert the input signal into a standard signal in a preset format, and pass the first output interface Outputting the standard signal; if the interface type is a non-preset type, outputting the input signal through a second output interface; Wherein, the field programmable gate array module includes: an interface identification identification unit, configured to identify the interface identification of the input interface corresponding to the input signal; An interface type identification unit, configured to determine the interface type according to the mapping relationship between the interface identifier and the interface type; a signal extraction unit, configured to extract the high level that appears for the first time in the input signal; a signal adjustment unit, configured to adjust the duration of the high level to a preset duration to obtain the standard signal; The first signal output unit is configured to output the standard signal through the first output interface. 2. The system according to claim 1, wherein the field programmable gate array module is specifically used to detect whether the input signal matches a preset format, and if not match, the interface of the input interface Types are marked as preset types. 3. The system according to claim 1 or 2, wherein the input signal comprises at least two level signals, and the field programmable gate array module further comprises: A signal decoding unit, configured to decode the input signal into at least two parallel standard signals in a preset format; The second signal output unit is configured to output parallel standard signals through the first output interface. 4. The system according to claim 3, wherein the signal decoding unit is specifically used for: Extracting the high level that appears for the first time in each level signal in the input signal; The duration of each high level is adjusted to a preset duration to obtain parallel standard signals.

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