CN110581708B - Frequency Locked Loop Full Digital Frequency Synthesizer - Google Patents

Abstract

The application relates to a frequency-locked loop type all-digital frequency synthesizer. The method comprises the following steps: the device comprises a frequency discriminator module, a frequency integration module and a frequency tuning module; the frequency discriminator module, frequency integral module and frequency tuning module connect gradually, and the output end signal feedback of the output of frequency tuning module is to the frequency discriminator module, and the frequency discriminator module includes: the variable frequency counter is used for comparing with the frequency control word to obtain an integer frequency error; the time-to-digital converter is used for obtaining fractional frequency errors, the frequency discriminator module is also used for adding the integer frequency errors and the fractional frequency errors to obtain system frequency errors, the frequency integration module is used for obtaining system phase errors, and the frequency tuning module is used for receiving the system phase errors and processing the system phase errors to obtain output end signals and output the output end signals. The invention can avoid the problem of incapability of locking caused by fuzzy phase error while realizing all functions of the phase-locked loop type all-digital frequency synthesizer.

Description

Frequency-locked ring type all-digital frequency synthesizer

technical field

The present application relates to the technical field of integrated circuits, in particular to a frequency-locked loop-type all-digital frequency synthesizer.

Background technique

Limited by the poor matching and non-ideal characteristics of analog circuit modules, the analog frequency synthesizer based on the charge pump phase-locked loop structure has high requirements on the stability of the loop. At the same time, with the gradual development of integrated circuit technology, The matching and non-ideal characteristics of the device will become more obvious, and the advanced technology will also bring about further reduction of the power supply voltage, circuit design margin and voltage-controlled oscillator (VCO, Voltage-Controlled Oscillator) single sub-band frequency tuning The range is further compressed. In addition, the design method of frequency synthesizer based on analog circuit has poor portability and high design complexity, especially under the condition of wide frequency range, there are many factors that need to be considered in compromise.

The solution to the above problems is the digital design of analog circuits, that is, the use of an all-digital frequency synthesizer (ADFS, All-Digital Frequency Synthesizer) structure. The concept of ADFS was first proposed and designed by Dr. R.B. Staszewski of TI in 2003. , mainly to solve a series of above-mentioned design problems faced by the frequency synthesizer under the deep submicron CMOS process and realize the efficient integration of the frequency synthesizer in the system on chip (SoC, System on Chip), the birth of this design technology is greatly accelerated With the digitization process of frequency synthesizer, most of the high-performance ADFS currently designed can be compared with the performance of analog frequency synthesizer, but it has a simpler design process, smaller area and lower power consumption.

Up to now, all ADFS circuit structures are realized based on phase-locked loop architecture, but the system structure faces an unavoidable design problem: variable phase accumulator (VPA, Variable Phase Accumulator) and reference phase accumulator (RPA, Reference Phase Accumulator) is a continuous digital phase accumulator. Since the bit length of the digital accumulator is limited, when the initial output frequency of the digital control oscillator (DCO, Digital-Control Oscillator) differs greatly from the expected output frequency, and When the loop bandwidth of the phase-locked loop is small (the scale factor and the integral factor in the proportional integral filter are set small, resulting in a small feedback rate of the system), the two accumulators have asynchronous overflow (for the accumulation of a bit device, the fuzzy value is 2 ^a , if multiple asynchronous overflows occur within one system synchronous clock cycle, the fuzzy value is 2 ^ab , where b is the number of asynchronous overflows), resulting in the existence of the difference between the two (phase error) In the case of ambiguity, large pulse fluctuations are introduced into the loop, which prolongs the locking time of the loop, and even causes the loop to lose lock in severe cases. For the case of a single asynchronous overflow, the fuzzy compensation unit can usually be used (the working principle of the fuzzy compensation unit is to judge according to the input system phase error and the preset threshold, and then compensate the system phase error according to the fuzzy value and output the actual system phase error) to avoid the generation of pulse fluctuations in the system phase error, but the bit width of the accumulator and the coefficient of the loop filter must be carefully designed to use this compensation method, and it must be verified by multiple simulations of edge conditions to avoid synchronization in a system There are multiple asynchronous overflows of the accumulator within the clock cycle, otherwise the fuzzy compensation unit still cannot completely avoid the generation of pulse fluctuations in the system phase error, which will undoubtedly greatly increase the workload of the design, especially in the design of a wide frequency output range. when an all-digital frequency synthesizer.

Contents of the invention

Based on this, it is necessary to address the above-mentioned technical problems and provide a frequency-locked loop all-digital frequency synthesizer that can solve the problem of ambiguity in the phase difference value in the all-digital frequency synthesizer based on the phase-locked loop architecture, which causes the loop locking time to be prolonged or even the loop cannot be locked. frequency synthesizer.

A frequency-locked ring type all-digital frequency synthesizer, comprising:

A frequency discriminator module, a frequency integration module and a frequency tuning module;

The frequency discriminator module, the frequency integration module and the frequency tuning module are connected in sequence, and the output signal of the output terminal of the frequency tuning module is fed back to the frequency discriminator module;

The discriminator module includes:

A variable frequency counter, the variable frequency counter is connected to the output terminal of the frequency tuning module, and counts the output frequency of the signal at the output terminal, and compares it with the frequency control word to obtain an integer frequency error;

A time-to-digital converter, the time-to-digital converter is used to respectively calibrate the time amount of the input reference frequency signal at the current time and the previous time at the rising edge of the system synchronization signal ahead of the output signal, according to the difference of the time amount The period of the output signal is normalized to obtain a fractional frequency error;

The frequency discriminator module is also used to add the integer frequency error and the decimal frequency error to obtain a system frequency error;

The frequency integration module is used to receive the system frequency error, accumulate and limit the system frequency error, and obtain the system phase error;

The frequency tuning module is used to receive the system phase error and process the system phase error to obtain an output signal and output it.

In one of the embodiments, the variable frequency counter includes: an m-stage prescaler and a serial carry binary counter;

The m-stage prescaler reduces the frequency of the output signal by 2 ^m times, and provides the counting result of the high bit; the serial carry binary counter is to the m-stage prescaler The output frequency signal is accumulated and a low-bit technical result is provided.

In one of the embodiments, the internal flip-flop of the variable frequency counter is a true one-way clock structure flip-flop.

In one of the embodiments, the true unidirectional clock structure flip-flop is a true unidirectional clock D flip-flop with a trigger reset function; the true unidirectional clock D flip-flop also includes: an inverter and an AND gate, the output The terminal signal is input to the inverter for inversion and delay operation, and the output terminal of the inverter is connected to the input terminal of the AND gate; An AND operation is performed in the AND gate to generate a high-level reset pulse, and the high-level reset pulse is used to reset the true one-way clock D flip-flop.

In one of the embodiments, the internal trigger of the variable frequency counter is realized by using a current mode logic structure.

In one of the embodiments, the frequency discriminator module further includes: a retiming unit, the retiming unit is used to generate a frequency consistent with the frequency of the input reference frequency signal according to the output signal and the input reference frequency signal of the system synchronization signal.

In one of the embodiments, the frequency integration module includes: a limit accumulator, and the limit accumulator is used to integrate and limit the system frequency error to obtain the system phase error.

In one of the embodiments, the frequency tuning module includes: a digital loop filter and a digitally controlled oscillator connected in sequence; the digital loop filter receives the system phase error and performs filtering processing on the system phase error Generate an integer digital frequency tuning word and a decimal digital frequency tuning word; the numerically controlled oscillator tunes the output frequency of the output signal according to the integer digital frequency tuning word and the decimal digital frequency tuning word, and completes locking .

The above-mentioned frequency-locked loop type all-digital frequency synthesizer, under the condition that the functions and performances are the same as those of the traditional phase-locked loop type full-digital frequency synthesizer, the frequency-locked loop type full-digital frequency synthesizer utilizes The variable frequency counter replaces the continuous phase accumulators (VPA and RPA) in the phase-locked loop type all-digital frequency synthesizer, which can completely avoid the asynchronous overflow of VPA and RPA in the phase-locked loop type full-digital frequency synthesizer, and completely eliminate the phase-locked loop The generation of pulse fluctuations during the locking process of the type all-digital frequency synthesizer increases the stability of the loop locking and has higher reliability.

Description of drawings

Fig. 1 is a schematic structural diagram of a frequency-locked ring type all-digital frequency synthesizer in an embodiment;

Fig. 2 is a working principle diagram of a time-to-digital converter in an embodiment;

Fig. 3 is a schematic structural diagram of a variable frequency counter in an embodiment;

Fig. 4 is a structural schematic diagram of a true unidirectional clock D flip-flop with a trigger reset function in an embodiment;

Fig. 5 is the structural representation of frequency-locked ring type all-digital frequency synthesizer in another embodiment;

Fig. 6 is a simulation diagram of the counting result of the variable frequency counter and the frequency error in one embodiment.

Detailed ways

In order to make the purpose, technical solution and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present application, and are not intended to limit the present application.

In one embodiment, a schematic structural diagram of a frequency-locked loop type all-digital frequency synthesizer is provided. As shown in FIG. 1 , the frequency-locked loop type full-digital frequency synthesizer includes a frequency discriminator module 100, a frequency integration module 200 and frequency tuning module 300 three modules, frequency discriminator module 100, frequency integration module 200 and frequency tuning module 300 are connected in sequence, and the output signal of the output terminal of frequency tuning module 300 is fed back to the frequency discriminator module 100.

Specifically, the frequency discriminator module 100 mainly includes a variable frequency counter 110 and a time-to-digital converter 120. The variable frequency counter 110 is connected to the output terminal of the frequency tuning module 300, and counts the output frequency of the output terminal signal, and compares it with the frequency The control word is compared to get the integer frequency error.

The time-to-digital converter 120 is used to calibrate the time amount of the input reference frequency signal at the current moment and the last moment ahead of the output signal at the rising edge of the system synchronization signal, and normalize the period of the output signal according to the time difference , to get the fractional frequency error.

It is worth noting that, compared with the time-to-digital converter of the traditional phase-locked loop type all-digital frequency synthesizer, the time-to-digital converter 120 adds a differential function (the digital domain is differential), and its working method and structure are shown in Figure 2 .

The frequency discriminator module 100 is also used to add the integer frequency error and the fractional frequency error to obtain the system frequency error.

The frequency integration module 200 is used to receive the system frequency error, accumulate the system frequency error, and obtain the system phase error.

The frequency tuning module 300 is used to receive the system phase error and process the system phase error to obtain and output the output signal.

In this embodiment, the frequency tuning of the output signal can complete the locking, and all the functions of the frequency-locked ring type all-digital frequency synthesizer have been completed so far.

The above-mentioned frequency-locked loop type all-digital frequency synthesizer, under the condition that the functions and performances are the same as those of the traditional phase-locked loop type full-digital frequency synthesizer, the frequency-locked loop type full-digital frequency synthesizer utilizes The variable frequency counter replaces the continuous phase accumulators (VPA and RPA) in the phase-locked loop type all-digital frequency synthesizer, which can completely avoid the asynchronous overflow of VPA and RPA in the phase-locked loop type full-digital frequency synthesizer, and completely eliminate the phase-locked loop The generation of pulse fluctuations during the locking process of the type frequency synthesizer increases the stability of the loop locking and has higher reliability.

It is worth noting that the detection of the phase error of the system by the phase-locked loop type all-digital frequency synthesizer is mainly realized by integrating the frequency, and the frequency-locked loop can be equivalent to first differentiating and then integrating the frequency integration. It is equivalent in the domain model, so the frequency-locked loop type all-digital frequency synthesizer and the phase-locked loop type all-digital frequency synthesizer have exactly the same function and performance.

In one embodiment, the variable frequency counter includes: an m-stage prescaler and a serial carry binary counter;

The m-stage prescaler reduces the frequency of the output signal by 2 ^m times, and provides the counting result of the high bit; the serial carry binary counter is to the m-stage prescaler The output frequency signal is accumulated, and the counting result of the low bit is provided.

Specifically, as shown in Figure 3, the variable frequency counter is an n-bit counter, and the output signal is expressed as CKV. The frequency of the output signal is reduced by 2 ^m times, which greatly eases the speed requirements for the subsequent serial carry binary counter. Every time the clock arrives at a rising edge, the serial carry binary counter performs an operation of adding 1, and its final count output is Out[0:n-1].

In one embodiment, the internal flip-flop of the variable frequency counter is a true one-way clock structure flip-flop.

In another embodiment, in order to cope with higher frequencies, the true unidirectional clock structure flip-flop can be implemented by using a current mode logic structure.

In a specific embodiment, the true unidirectional clock structure flip-flop is a true unidirectional clock D flip-flop with a trigger reset function, and the true unidirectional clock D flip-flop also includes: an inverter and an AND gate, and the signal input of the output terminal is reversed. The phaser performs inversion and delay operations, the output terminal of the inverter is connected to the input terminal of the AND gate, and the output signal and the signal output by the output terminal of the inverter are ANDed in the AND gate to generate a high-level reset pulse. A high reset pulse is used to reset the true unidirectional clocked D flip-flop.

Specifically, as shown in Figure 4, a schematic structural diagram of a reset true unidirectional clock D flip-flop is provided. In the figure, after an inverter and an AND gate are combined, an RST reset of a reset true unidirectional clock D flip-flop is generated. Signal. It can be seen from the figure that when the next rising edge of the CKV clock signal arrives, the counting will be restarted to complete the frequency detection function of the output signal.

In another embodiment, the delay time of the inverter is adjustable and can be determined according to specific simulation results.

In one embodiment, the frequency discriminator module further includes: a retiming unit, configured to generate a system synchronization signal having a frequency consistent with the input reference frequency signal according to the output signal and the input reference frequency signal.

In one of the embodiments, the frequency integration module includes: a limiting accumulator. The limiting accumulator is used to integrate the system frequency error and avoid the inversion of the accumulator through limiting to obtain the system phase error.

In one of the embodiments, the frequency tuning module includes: a digital loop filter and a numerically controlled oscillator connected in sequence, the digital loop filter receives the system phase error, and generates an integer digital frequency tuning word and Decimal digital frequency tuning word; the numerical control oscillator tunes the output frequency of the output signal according to the integer digital frequency tuning word and the decimal digital frequency tuning word to complete locking.

In a specific embodiment, as shown in Figure 5, a schematic structural diagram of a specific frequency-locked ring type all-digital frequency synthesizer is provided, wherein, TDC represents a time-to-digital converter, DFF represents a D-type flip-flop, and retiming f _ref represents the retiming unit, DLF represents the digital loop filter, where the input parameters α and β represent the proportional coefficient and integral coefficient of the proportional-integral filter respectively, λ _i , i=1,2,... , n represents the filter coefficient of the infinite impulse response filter, f _ref represents the input reference frequency signal, CKV represents the output signal, CKR represents the system synchronization signal, T _v represents the cycle of the output signal, FCW(N) represents the frequency division ratio is The frequency control word of N, R _v [k] represents the counting result of the variable frequency counter at the rising edge of the k-th system synchronous clock, ε[k] represents the fractional frequency error at the rising edge of the k-th system synchronous clock, R _e [k] represents the system frequency error at the rising edge of the kth system synchronous clock, OTW_I represents the integer digital frequency tuning word, OTW_F represents the fractional digital frequency tuning word, and the DCO output is the output signal, which is consistent with CKV.

In this embodiment, the number of digits of the variable frequency counter only needs to cover the maximum frequency division ratio. Compared with the VPA, it has a lower number of digits. At the same time, the limiter function is used to replace the full digital Fuzzy compensation unit in the frequency synthesizer, the design complexity is lower. The integral module in the proportional-integral filter is also implemented by a limiting accumulator with the same function as in the frequency integral module to avoid value reversal during the locking process.

During the locking process of the frequency-locked loop type all-digital frequency synthesizer shown in Figure 5, the counting results of the variable frequency counter and the simulation results of the frequency error are shown in Figure 6, where the loop bandwidth is set to 250kHz, and the DCO initial The difference between the frequency and the expected output frequency is 2GHz, and the frequency control word is 192.3077. Since the variable frequency counter has a period clearing function, and both the frequency integration module and the integration module in the loop filter have added a limiter function, Therefore, it can be concluded that the frequency-locked loop structure can completely eliminate the asynchronous overflow of the phase-locked loop structure, and has higher reliability than the phase-locked loop-type all-digital frequency synthesizer.

The technical features of the above embodiments can be combined arbitrarily. To make the description concise, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, they should be It is considered to be within the range described in this specification.

The above-mentioned embodiments only express several implementation modes of the present application, and the description thereof is relatively specific and detailed, but should not be construed as limiting the scope of the patent for the invention. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the scope of protection of the patent application should be based on the appended claims.

Claims (8)

1. A frequency-locked loop type all-digital frequency synthesizer, comprising:

the device comprises a frequency discriminator module, a frequency integration module and a frequency tuning module;

the frequency discriminator module, the frequency integration module and the frequency tuning module are sequentially connected, and an output end signal of an output end of the frequency tuning module is fed back to the frequency discriminator module;

the frequency discriminator module comprises:

the variable frequency counter is connected with the output end of the frequency tuning module, counts the output frequency of the output end signal and compares the output frequency with a frequency control word to obtain an integer frequency error;

the time-to-digital converter is used for respectively calibrating the time quantum of the input reference frequency signal at the current moment and the time quantum of the input reference frequency signal at the last moment, which leads the output end signal at the rising edge moment of the system synchronizing signal, and normalizing the period of the output end signal according to the difference value of the time quantum to obtain a fractional frequency error;

the frequency discriminator module is also used for adding the integer frequency error and the decimal frequency error to obtain a system frequency error;

the frequency integration module is used for receiving the system frequency error, accumulating the system frequency error and limiting amplitude to obtain a system phase error;

and the frequency tuning module is used for receiving the system phase error, processing the system phase error, obtaining and outputting an output end signal.

2. The frequency-locked loop type all-digital frequency synthesizer according to claim 1, wherein the variable frequency counter comprises: m-stage pre-frequency dividers and serial carry binary counters;

the m-stage prescaler reduces the frequency of the output end signal by 2 ^m Multiplying and providing a counting result of high bits; and the serial carry binary counter accumulates the output frequency signals of the m-stage pre-frequency dividers and provides a counting result of a low bit.

3. The frequency-locked loop type all-digital frequency synthesizer according to claim 1, wherein the internal flip-flop of the variable frequency counter is a true one-way clock structure flip-flop.

4. The frequency-locked loop type all-digital frequency synthesizer according to claim 1, wherein the internal flip-flop of the variable frequency counter is implemented using a current-mode logic structure.

5. The frequency-locked loop type all-digital frequency synthesizer according to claim 3, wherein the true one-way clock structure flip-flop is a true one-way clock D flip-flop with a trigger reset function;

the true unidirectional clock D flip-flop further comprises: the output end signal of the inverter is input into the inverter to carry out inversion and delay operation, and the output end of the inverter is connected with the input end of the AND gate;

and the output end signal and the signal output by the output end of the phase inverter are subjected to AND operation in the AND gate to generate a high-level reset pulse, and the high-level reset pulse is used for resetting the true unidirectional clock D trigger.

6. The frequency-locked loop type all-digital frequency synthesizer according to any one of claims 1 to 4, wherein the discriminator module further comprises:

a retiming unit to generate the system synchronization signal in frequency correspondence with the input reference frequency signal from the output end signal and the input reference frequency signal.

7. The frequency-locked loop type all-digital frequency synthesizer according to any one of claims 1 to 4, wherein the frequency integration module comprises:

and the amplitude limiting accumulator is used for integrating and limiting the system frequency error to obtain a system phase error.

8. The frequency-locked loop type all-digital frequency synthesizer according to any one of claims 1 to 4, wherein the frequency tuning module comprises:

a digital loop filter and a digital controlled oscillator which are connected in sequence;

the digital loop filter receives the system phase error, and generates an integer digital frequency tuning word and a decimal digital frequency tuning word after filtering the system phase error;

and the numerically controlled oscillator tunes the output frequency of the output end signal according to the integer digital frequency tuning word and the decimal digital frequency tuning word to complete locking.

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