CN110598369B - Clock circuit structure - Google Patents
Clock circuit structure Download PDFInfo
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- CN110598369B CN110598369B CN201910992946.3A CN201910992946A CN110598369B CN 110598369 B CN110598369 B CN 110598369B CN 201910992946 A CN201910992946 A CN 201910992946A CN 110598369 B CN110598369 B CN 110598369B
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
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Abstract
The invention relates to a clock circuit structure, which comprises one or more than one input unit, an output selector and an output inverter; the input unit comprises an input selector and an input inverter; the input end of the input selector is used for receiving an original clock pulse signal, the output end of the input selector is connected with the input end of the input inverter, the output end of the input inverter is connected with the input end of the output selector, the output end of the output selector is connected with the input end of the output inverter, and the output end of the output inverter is used for outputting the offset clock pulse signal. The invention solves the problem that the clock is shifted to one direction when the clock circuit is selected in multiple ways, and ensures that the duty ratio of the clock is 50%.
Description
Technical Field
The invention relates to the technical field of clock circuits, in particular to a clock circuit structure.
Background
In all chip designs, a complex clock structure exists, a plurality of paths of clocks or even more than ten paths of clocks are input, and a proper path of clocks is finally selected for use, but an unreasonable clock selection circuit is extremely easy to cause the problem of duty ratio, the duty ratio of a clock signal can not be ensured to be 50%, and certain clock duty ratio sensitive modules work abnormally; therefore, the demand cannot be satisfied.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a clock circuit structure.
In order to achieve the above purpose, the present invention adopts the following technical scheme:
A clock circuit structure comprises one or more input units, an output selector and an output inverter; the input unit comprises an input selector and an input inverter; the input end of the input selector is used for receiving an original clock pulse signal, the output end of the input selector is connected with the input end of the input inverter, the output end of the input inverter is connected with the input end of the output selector, the output end of the output selector is connected with the input end of the output inverter, and the output end of the output inverter is used for outputting the offset clock pulse signal.
The further technical scheme is as follows: the input selector is used for receiving one or more than one original clock pulse signals.
The further technical scheme is as follows: the offset route of the original clock pulse signal comprises: the positive shift occurs on the input selector, the negative shift occurs on the input inverter, the negative shift occurs on the output selector, the positive shift occurs on the output inverter, and finally the shifted clock pulse signal is equal to the original clock pulse signal.
The further technical scheme is as follows: the input selector is the same as the output selector in model number.
The further technical scheme is as follows: the input selector is CLKMUX in type.
The further technical scheme is as follows: the input inverter and the output inverter are the same in model.
The further technical scheme is as follows: the input inverter is CLKINV.
A clock circuit structure comprises one or more input/output units and an output selector; the input/output unit comprises one or more input inverters, an input selector and an output inverter; the input end of the input inverter is used for receiving an original clock pulse signal, the output end of the input inverter is connected with the input end of the input selector, the output end of the input selector is connected with the input end of the output inverter, the output end of the input inverter is connected with the input end of the output selector, and the output end of the output selector is used for outputting the offset clock pulse signal.
The further technical scheme is as follows: the input selector is used for receiving one or more than one path of original clock pulse signals, and each path of original clock pulse signal corresponds to the input inverter.
The further technical scheme is as follows: the offset route of the original clock pulse signal comprises: the reverse offset occurs on the input inverter, the reverse offset occurs on the input selector, the forward offset occurs on the output inverter, the forward offset occurs on the output selector, and finally the offset clock pulse signal is equal to the original clock pulse signal.
Compared with the prior art, the invention has the beneficial effects that: the problem that the clock is shifted to one direction when multiplexing in the clock circuit is solved, and the duty ratio of the clock is ensured to be 50%.
The invention is further described below with reference to the drawings and specific embodiments.
Drawings
FIG. 1 is a schematic diagram of a prior art two-input clock selection circuit;
FIG. 2 is a schematic diagram of a two-input clock selection circuit offset;
FIG. 3 is a schematic diagram of a conventional four-way clock selection circuit;
FIG. 4 is a diagram of a four-way clock selection circuit offset;
FIG. 5 is a control schematic block diagram of a first embodiment of a clock circuit structure according to the present invention;
FIG. 6 is a schematic diagram of a selection circuit according to the first embodiment;
FIG. 7 is a schematic diagram of a selection circuit offset according to the first embodiment;
FIG. 8 is a schematic diagram of a selection refinement circuit according to the first embodiment;
FIG. 9 is a schematic diagram of a bias circuit of a selection refinement in accordance with a first embodiment;
FIG. 10 is a control schematic block diagram of a second embodiment of a clock circuit structure according to the present invention;
fig. 11 is a schematic diagram of a selection refinement circuit of the second embodiment.
Detailed Description
For the purpose of illustrating the concepts and objects of the invention, the invention is further described in connection with the drawings and detailed description that follow.
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that, in the embodiments of the present invention, all directional indicators (such as up, down, left, right, front, and back) are merely used to explain the relative positional relationship, movement conditions, and the like between the components in a specific posture (as shown in the drawings), if the specific posture is changed, the directional indicators correspondingly change, and the connection may be a direct connection or an indirect connection.
Furthermore, descriptions such as those referred to as "first," "second," and the like, are provided for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implying an order of magnitude of the indicated technical features in the present disclosure. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present invention.
Unless otherwise indicated, "/" herein means "or".
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms should not be understood as necessarily being directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, one skilled in the art can combine and combine the different embodiments or examples described in this specification.
In the specific embodiment shown in fig. 1 to 11, fig. 1 to 4 are prior art, in which, as shown in fig. 1 to 2, two input selectors are taken as examples, CLK0 and CLK1 are taken as inputs, a suitable clock is selected as an output according to a selection requirement, and CLK is the final output; assuming that CLK0 is selected by this clock selector, clk=clk0 is based on the logical relationship of MUX (selector), CLK is also high if CLK0 is high, CLK0 and CLK are both shifted toward one direction, indicated by the rising arrow, that is, CLK0 jumps from low to high, CLK also jumps from low to high after Cell delay by MUX itself, so that the shift directions of CLK and CLK0 are identical.
If, as shown in fig. 3 to 4, four clocks (CLK 0/CLK1/CLK2/CLK 3) participate in the selection, and if CLK0 is still selected as the final output, that is, clk=clk0, then the clock shift conditions are as shown in fig. 4, CLK0 and CLK are both shifted toward one direction, and if one arrow represents one shift, then the four-way clock selection circuit clock is shifted toward one direction 2 times, which can lead to the conclusion that when a conventional selector is used as the clock for selection, the clock is shifted toward one direction, the more the number of times of the selection is, the more the number of times of the shift is; in the practical chip design, several paths of clock inputs exist, even more than ten paths of clock inputs are selected as output, so that the more the number of times of shifting to one direction is, the difference exists between the rising edge time and the falling edge time, the more the number of MUX stages is, the larger the difference is, the duty ratio is finally less than 50%, and certain modules sensitive to the duty ratio of the clock work abnormally.
As shown in fig. 5 to 9, the first embodiment of a clock circuit structure is disclosed, and includes one or more input units 10, an output selector 20, and an output inverter 30; the input unit 10 includes an input selector 11 and an input inverter 12; the input end of the input selector 11 is used for receiving an original clock pulse signal, the output end of the input selector is connected with the input end of the input inverter 12, the output end of the input inverter 12 is connected with the input end of the output selector 20, the output end of the output selector 20 is connected with the input end of the output inverter 30, and the output end of the output inverter 30 is used for outputting the offset clock pulse signal.
The input selector 11 is configured to receive one or more original clock signals.
Wherein, the offset route of the original clock pulse signal comprises: the forward shift occurs at the input selector 11, the reverse shift occurs at the input inverter 12, the reverse shift occurs at the output selector 20, the forward shift occurs at the output inverter 30, and finally the shifted clock signal is made equal to the original clock signal.
Wherein the input selector 11 is the same as the output selector 20 in model number.
Further, the input selector 11 is CLKMUX.
Wherein the input inverter 12 is the same type as the output inverter 30.
Further, the input inverter 12 is CLKINV.
In the specific embodiment shown in fig. 6 to 9, the clock is shifted forward when passing through Mux1, and shifted backward when passing through Mux 4; mux4 in the figure is refined and decomposed into 3 Inverters (INV) and one selector (Mux), again assuming CLK0 is still selected, i.e. clk=clk0; the specific analysis result of clock offset can be obtained through analysis, after the clock offset is subjected to Mux1 forward offset (solid arrow), after the clock offset is subjected to INV0, the signal is reversed and is reversed offset (dotted arrow), after the clock offset is subjected to Mux5 reverse offset (dotted arrow), the signal is reversed and is changed into forward offset (solid arrow) after the clock offset is subjected to INV 2; it can be seen that the difference between the rising and falling edges is exactly opposite in the two muxes, one forward offset and one reverse offset; two INV, one forward offset and one reverse offset, the number of the forward and reverse offsets is the same, and finally CLK is output, clk=clk0.
As shown in fig. 10 to 11, the present invention discloses a second embodiment of a clock circuit structure,
Comprises one or more input/output units 40, and an output selector 50; the input-output unit 40 includes one or more input inverters 41, an input selector 42, and an output inverter 43; the input end of the input inverter 41 is used for receiving an original clock pulse signal, the output end of the input inverter 41 is connected with the input end of the input selector 42, the output end of the input selector 42 is connected with the input end of the output inverter 43, the output end of the input inverter 43 is connected with the input end of the output selector 50, and the output end of the output selector 50 is used for outputting the offset clock pulse signal.
The input selector 42 is configured to receive one or more original clock signals, and each original clock signal corresponds to the input inverter 41.
Wherein, the offset route of the original clock pulse signal comprises: the reverse offset occurs in the input inverter 41, the reverse offset occurs in the input selector 42, the forward offset occurs in the output inverter 43, the forward offset occurs in the output selector 50, and finally the offset clock signal is made equal to the original clock signal.
In other embodiments, when ten or more clocks are selected, the above structure is adopted, and the input and output of the MUX in the 2 nd, 4 th, 6 … th even columns are added to the circuit structure of the inverter or the input and output of the MUX in the 1 st, 3 rd, 5 th … th odd columns are added to the circuit structure of the inverter, so that the duty ratio of the clock signal can be ensured to be 50%; the MUX in this patent uses a two-input MUX as an example, but a three-input MUX or other input MUX can be used as well, and the circuit is a clock selection circuit, so that the selector and the inverter used in the circuit are CLKMUX and CLKINV with equal rising edges and falling edges.
In summary, the invention solves the problem that the clock is shifted to one direction when multiplexing in the clock circuit, and ensures that the duty ratio of the clock is 50%.
The foregoing examples are provided to further illustrate the technical contents of the present invention for the convenience of the reader, but are not intended to limit the embodiments of the present invention thereto, and any technical extension or re-creation according to the present invention is protected by the present invention. The protection scope of the invention is subject to the claims.
Claims (10)
1. A clock circuit structure is characterized by comprising one or more than one input unit, an output selector and an output inverter; the input unit comprises an input selector and an input inverter; the input end of the input selector is used for receiving an original clock pulse signal, the output end of the input selector is connected with the input end of the input inverter, the output end of the input inverter is connected with the input end of the output selector, the output end of the output selector is connected with the input end of the output inverter, and the output end of the output inverter is used for outputting the offset clock pulse signal.
2. A clock circuit arrangement as claimed in claim 1, wherein the input selector is arranged to receive one or more primary clock signals.
3. A clock circuit arrangement as claimed in claim 1, wherein the offset path of the original clock signal comprises: the positive shift occurs on the input selector, the negative shift occurs on the input inverter, the negative shift occurs on the output selector, the positive shift occurs on the output inverter, and finally the shifted clock pulse signal is equal to the original clock pulse signal.
4. A clock circuit arrangement as claimed in claim 1, wherein the input selector is of the same type as the output selector.
5. The clock circuit structure of claim 4 wherein said input selector is CLKMUX.
6. A clock circuit arrangement as claimed in claim 1, wherein the input inverter is of the same type as the output inverter.
7. The clock circuit structure of claim 6 wherein said input inverter is CLKINV.
8. A clock circuit structure is characterized by comprising one or more than one input/output unit and an output selector; the input/output unit comprises one or more input inverters, an input selector and an output inverter; the input end of the input inverter is used for receiving an original clock pulse signal, the output end of the input inverter is connected with the input end of the input selector, the output end of the input selector is connected with the input end of the output inverter, the output end of the input inverter is connected with the input end of the output selector, and the output end of the output selector is used for outputting the offset clock pulse signal.
9. The clock circuit structure of claim 8, wherein the input selector is configured to receive one or more primary clock signals, each primary clock signal corresponding to the input inverter.
10. A clock circuit structure as recited in claim 8, wherein the offset path of the original clock signal comprises: the reverse offset occurs on the input inverter, the reverse offset occurs on the input selector, the forward offset occurs on the output inverter, the forward offset occurs on the output selector, and finally the offset clock pulse signal is equal to the original clock pulse signal.
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| CN201910992946.3A CN110598369B (en) | 2019-10-18 | 2019-10-18 | Clock circuit structure |
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| CN201910992946.3A CN110598369B (en) | 2019-10-18 | 2019-10-18 | Clock circuit structure |
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| CN110598369B true CN110598369B (en) | 2024-09-27 |
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| CN114519031A (en) * | 2021-11-19 | 2022-05-20 | 中科亿海微电子科技（苏州）有限公司 | Programmable interconnect channel structure and FPGA chip that can maintain duty cycle |
| CN114167264B (en) * | 2021-12-03 | 2024-03-15 | 中国人民解放军国防科技大学 | Device for detecting digital circuit hold time violations in nuclear radiation environment |
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| CN210270901U (en) * | 2019-10-18 | 2020-04-07 | 深圳忆联信息系统有限公司 | Clock circuit structure |
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| JP2000311028A (en) * | 1999-04-28 | 2000-11-07 | Hitachi Ltd | Phase control circuit, semiconductor device, and semiconductor memory |
| CN1801691A (en) * | 2004-12-31 | 2006-07-12 | 晨星半导体股份有限公司 | A quadrature phase signal generating device and data recovery circuit |
| US7839192B1 (en) * | 2005-10-26 | 2010-11-23 | Altera Corporation | Duty cycle correction methods and circuits |
| JP2009124532A (en) * | 2007-11-16 | 2009-06-04 | Nec Electronics Corp | Semiconductor integrated circuit |
| CN101789774B (en) * | 2009-01-22 | 2011-11-30 | 中芯国际集成电路制造(上海)有限公司 | all-digital pulse width control circuit |
| US8493107B2 (en) * | 2010-07-27 | 2013-07-23 | Mediatek Inc. | Clock generator for generating output clock having non-harmonic relationship with input clock and related clock generating method thereof |
| CN103050146B (en) * | 2013-01-11 | 2015-09-16 | 昆山慧凝微电子有限公司 | High duty ratio DDR2 digital delay chain circuit |
| CN103248341B (en) * | 2013-05-06 | 2016-01-20 | 复旦大学 | On a kind of VLSI of being applicable to sheet, the deflection of clock system detects and removes skew adjustments circuit |
| US9336865B1 (en) * | 2015-06-02 | 2016-05-10 | M31 Technology Corporation | Multi-port SRAM module and control method thereof |
| CN106330174B (en) * | 2016-08-16 | 2019-02-12 | 深圳市华星光电技术有限公司 | The electronic device of CMOS inverter and the application CMOS inverter |
| JP6929812B2 (en) * | 2018-03-15 | 2021-09-01 | キオクシア株式会社 | Semiconductor devices and memory systems |
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| CN210270901U (en) * | 2019-10-18 | 2020-04-07 | 深圳忆联信息系统有限公司 | Clock circuit structure |
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