CN110611989A - Circuit board and electronic device - Google Patents
Circuit board and electronic device Download PDFInfo
- Publication number
- CN110611989A CN110611989A CN201911036548.0A CN201911036548A CN110611989A CN 110611989 A CN110611989 A CN 110611989A CN 201911036548 A CN201911036548 A CN 201911036548A CN 110611989 A CN110611989 A CN 110611989A
- Authority
- CN
- China
- Prior art keywords
- circuit board
- trace
- substrate layer
- layer
- electrically connected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000012360 testing method Methods 0.000 claims abstract description 65
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 239000004020 conductor Substances 0.000 claims abstract description 22
- 239000000463 material Substances 0.000 claims abstract description 17
- 229910000679 solder Inorganic materials 0.000 claims description 21
- 230000000149 penetrating effect Effects 0.000 claims description 4
- 230000010354 integration Effects 0.000 abstract description 10
- 239000010410 layer Substances 0.000 description 99
- 238000005452 bending Methods 0.000 description 7
- 239000004642 Polyimide Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229920000139 polyethylene terephthalate Polymers 0.000 description 2
- 239000005020 polyethylene terephthalate Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- BXLICFUSUZPSHT-UHFFFAOYSA-N 1-(4-chlorophenyl)-3-fluoropropan-2-amine Chemical compound FCC(N)CC1=CC=C(Cl)C=C1 BXLICFUSUZPSHT-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- -1 Polyethylene terephthalate Polymers 0.000 description 1
- 239000002519 antifouling agent Substances 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical class [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000002355 dual-layer Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 239000011796 hollow space material Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
- H05K1/0268—Marks, test patterns or identification means for electrical inspection or testing
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
The invention provides a circuit board and an electronic device using the same. The circuit board comprises a first substrate layer, a plurality of first wires, a plurality of second wires, a conductive body and a test pad. The first substrate layer has a first surface and a second surface opposite to each other. The circuit board is defined with a via hole, and the via hole penetrates through the first base material layer along the direction from the first surface to the second surface. The first trace is located on the first surface. The second trace is located on the second surface. The electric conductor is positioned in the through hole to electrically connect one first wire and one second wire. The test pad covers and is electrically connected with the conductor. Because the test pads of the circuit board are arranged at the through holes, each test pad does not occupy the area of the circuit board independently any more, and the integration level of the circuit board is improved.
Description
Technical Field
The present invention relates to printed circuit technologies, and in particular, to a circuit board and an electronic device using the same.
Background
With the increase of integration of electronic products, the density of electronic components and wiring on a circuit board per unit area is increasing, and the requirements for signal quality are becoming more stringent. Test pads are typically provided on the circuit board to perform signal measurements on the electronic components on the circuit board.
Currently, the method of providing the test pad is to provide a pad (pad) on the original trace for testing or to pull an additional trace for testing. However, each pad or trace occupies a certain area of the circuit board, and the area of the circuit board is limited, so that there is a problem that the circuit board does not have enough space to be used as a test pad.
Disclosure of Invention
One aspect of the present invention provides a circuit board, including:
the circuit board is provided with a first base material layer and a second base material layer, wherein the first base material layer is provided with a first surface and a second surface which are opposite to each other, a through hole is defined in the circuit board, and the through hole penetrates through the first base material layer along the direction from the first surface to the second surface;
the first routing wires are positioned on the first surface;
a plurality of second routing lines positioned on the second surface;
the electric conductor is positioned in the through hole so as to electrically connect one first wire and one second wire; and
and the test pad covers and is electrically connected with the conductor.
In the embodiment of the invention, the test pads of the circuit board are arranged at the through holes, so that each test pad does not occupy the area of the circuit board independently, and the layer change of the first routing and the second routing on different routing layers can be realized at the through holes, and the function of the test pads is also realized. Therefore, the space of the circuit board is saved, and the integration level of the circuit board is improved.
The invention further provides an electronic device, which includes a first electronic component, a second electronic component, and a circuit board electrically connected to the first electronic component and the second electronic component, where the circuit board is the above circuit board, the first electronic component is electrically connected to the first trace, and the second electronic component is electrically connected to the second trace.
The circuit board has the advantage of high integration level, so that the structure of the electronic device applying the circuit board is more compact.
Drawings
Fig. 1 is a schematic diagram of a circuit board according to a first embodiment of the present invention.
Fig. 2 is a schematic sectional view taken along the line II-II in fig. 1.
Fig. 3, 4 and 5 are projection views of the conductor on the first base material layer according to the modified embodiment of the circuit board of the present invention.
Fig. 6 and fig. 7 are schematic views of a first trace, a second trace and a test pad according to an alternative embodiment of the circuit board of the invention.
Fig. 8 is a cross-sectional view of a second embodiment of the circuit board of the present invention.
Fig. 9 is a cross-sectional view of a third embodiment of the circuit board of the present invention.
Fig. 10 is a block diagram of an electronic device according to an embodiment of the invention.
Description of the main elements
The following detailed description will further illustrate the invention in conjunction with the above-described figures.
Detailed Description
As shown in fig. 1, a circuit board 100 according to a first embodiment of the present invention includes a first substrate layer 10, a plurality of first traces 12, a plurality of second traces 13, a plurality of vias 11, and a plurality of test pads 16.
As shown in fig. 2, the first substrate layer 10 has a first surface 10a and a second surface 10b opposite to each other. The first surface 10a and the second surface 10b are two surfaces that are substantially parallel and opposite.
In an embodiment, the Circuit board 100 is a Flexible Circuit board, such as an integrated Flexible Circuit board (FPCA). The first substrate layer 10 is made of a flexible organic material, such as Polyimide (PI) or Polyethylene terephthalate (PET), and the like. In other embodiments, the circuit board 100 may be a rigid circuit board, such as a Printed Circuit Board (PCBA).
Referring to fig. 1 and fig. 2, a plurality of first traces 12 are disposed on the first surface 10 a. A plurality of second traces 13 are located on the second surface 10 b. Each via hole 11 penetrates through the first substrate layer 10 in a direction from the first surface 10a to the second surface 10 b. The circuit board 100 also includes an electrical conductor 15 located within the via 11. Each via hole 11 is electrically connected to a first trace 12 and a second trace 13 through a conductive body 15 located therein, so that the first trace 12 and the second trace 13 located on different film layers are electrically connected. The test pad 16 covers and electrically connects the electrical conductor 15 within the via 11.
In one embodiment, each of the first traces 12 is used for electrically connecting the first electronic component 60 (shown in fig. 10), and each of the second traces 13 is used for electrically connecting the second electronic component 70 (shown in fig. 10). One first trace 12 and one second trace 13 are electrically connected to realize the transmission of signals between the first electronic component 60 and the second electronic component 70.
When the circuit board 100 fails and needs to be detected, a probe of a testing instrument can be connected to the testing pad 16 to obtain signals transmitted between the first trace 12 and the second trace 13. According to whether the signals transmitted between the first trace 12 and the second trace 13 obtained by the test instrument meet the specification, the position of the circuit board 100 with a fault can be determined.
By arranging the test pads 16 at the via holes 11, each test pad 16 does not occupy the area of the circuit board 100 alone, and the positions of the via holes 11 can realize layer changing of the first routing lines 12 and the second routing lines 13 on different routing layers and have the function of the test pads 16. Compared with the mode that the via holes and the test pads are separately arranged and respectively occupy the area of the circuit board 100 in the prior art, the space of the circuit board 100 is saved, and the integration level of the circuit board 100 is improved.
With reference to fig. 1, the first substrate layer 10 defines a signal input area a1, a test area a2, a bending area A3 and a signal output area a4 sequentially connected along a first direction D1. The signal input region a1 and the test region a2 are approximately the same width along the second direction D2. The widths of the bending region A3 and the signal output region a4 in the second direction D2 are substantially the same. The second direction D2 intersects the first direction D1.
The signal input area a1 is provided with a plurality of input pins 17. The test pad 16 is located in the test zone a 2. Bending region a3 is substantially elongated in first direction D1 to facilitate bending. Each second trace 13 extends along the first direction D1 in the bending region a 3. The signal output area a4 is provided with a plurality of output pins 18.
Each first trace 12 extends substantially along the first direction D1, and a plurality of first traces 12 are arranged at intervals along the second direction D2. Each second trace 13 is electrically connected to one first trace 12 through an electrical conductor 15 disposed in one via 11. A test pad 16 is disposed at the junction of each first trace 12 and one second trace 13. That is, the number of test pads 16 is equal to the number of vias 11. A test pad 16 is disposed corresponding to each via 11. In other embodiments, the circuit board 100 may be provided with test pads 16 only at positions corresponding to a portion of the vias 11. That is, not all the positions of the vias 11 on the circuit board 100 are provided with the test pads 16, and some vias 11 are only used as routing layers on different layers.
Each second trace 13 extends substantially along the first direction D1, and a plurality of second traces 13 are arranged at intervals along the second direction D2. After each first trace 12 is electrically connected to one test pad 16, the self-test area a2 extends to the signal input area a1, and is electrically connected to one input pin 17 in the signal input area a 1. After each second trace 13 is electrically connected to one test pad 16, the self-test area a2 extends across the bending area A3 and is electrically connected to one output pin 18 in the signal output area a 4. Each first trace 12 may be electrically connected to the first electronic component 60 through an input pin 17, and each second trace 13 may be electrically connected to the second electronic component 70 through an output pin 18.
In one embodiment, the input pins 17 include a first input pin 172 and a second input pin 174. The second input pin 174 is further from the test area a2 than the first input pin 172. Each of the first input pins 172 and one of the second input pins 174 are spaced apart. In this way, the arrangement of the first traces 12 in the signal input area a1 can be more compact, so as to reduce the width of the signal input area a1 of the circuit board 100 in the second direction D2 and improve the integration level of the circuit board 100.
In one embodiment, in the test area a2, each of the first traces 12 and each of the second traces 13 are electrically connected to one of the test pads 16 and then approach the middle region of the first substrate layer 10 along the second direction D2. In this way, the arrangement of the first traces 12 and the second traces 13 in the test area a2 can be more compact, so as to reduce the width of the test area a2 of the circuit board 100 in the second direction D2, and improve the integration level of the circuit board 100.
In one embodiment, the first substrate layer 10 is axisymmetric along the second direction D2, and the distribution of the test pads 16 may be symmetrically distributed about the symmetry axis of the first substrate layer 10. The test pads 16 may be divided into a plurality of groups (fig. 1, with the middle test pad 16 removed and the remaining test pads 16 grouped into three groups), and the test pads 16 in each group are arranged in a diagonal line. That is, the connecting line of the test pads 16 in each group is a straight line or a curved line, and forms an angle with the second direction D2 (or the first direction D1). It is understood that the range of the included angles and the grouping of the test pads 16 are based on the convenience of wiring the circuit board 100, and are not limited to the situation shown in fig. 1.
In one embodiment, the output pins 18 include a first output pin 182 and a second output pin 184. The first output lead 182 is further away from the bending region a3 than the second output lead 184. Each of the first output pins 182 and one of the second output pins 184 are spaced apart. In this way, the arrangement of the second traces 13 in the signal output area a4 can be more compact, so as to reduce the width of the signal output area a4 of the circuit board 100 in the second direction D2 and improve the integration level of the circuit board 100.
Referring to fig. 2, the circuit board 100 is a dual-layer circuit board. That is, the circuit board 100 includes two routing layers. The via hole 11 is a through hole penetrating the first base material layer 10 substantially in a direction perpendicular to the first surface 10a and the second surface 10 b. The conductor 15 has a substantially hollow columnar shape. The electrical conductor 15 is embedded on the inner wall of the via 11 and extends partially onto the first surface 10a and the second surface 10b of the first substrate. One end of the conductive body 15 is electrically connected to the first trace 12 on the first surface 10a, and the other end is electrically connected to the second trace 13 on the second surface 10b, so as to implement signal transmission between the first trace 12 and the second trace 13. The material of the conductor 15 may be copper foil. In this embodiment, the via hole 11 is a circular hole. The projection of the conductor 15 on the first substrate layer 10 is a circular ring.
As shown in fig. 3 to 5, in other embodiments, the via hole 11 may be an elliptical hole or a polygonal hole. As shown in fig. 3, when the via hole 11 is an elliptical hole, the projection of the conductive body 15 on the first substrate layer 10 is an elliptical ring. As shown in fig. 4, when the via hole 11 is a trapezoidal hole, the projection of the conductor 15 on the first substrate layer 10 is a ring formed by two trapezoids with different sizes. As shown in fig. 5, when the via hole 11 is a parallelogram hole, the projection of the conductor 15 on the first base material layer 10 is a ring formed of two trapezoids having different sizes.
Referring to fig. 2, the first surface 10a of the first substrate layer 10 is further provided with other traces 14 different from the first trace 12. The conductive body 15 is spaced apart from and insulated from the other traces 14 on the first surface 10 a. The second surface 10b of the first substrate layer 10 is further provided with other traces 14 different from the second traces 13. The electrical conductor 15 is spaced from and insulated from the other tracks 14 on the second surface 10 b. The test pad 16 covers and electrically connects the electrical conductor 15. The test pad 16 extends partially into the hollow space surrounded by the electrical conductor 15. The material of the test pad 16 may be solder paste or copper-tin alloy.
With continued reference to fig. 2, the circuit board 100 further includes a first solder mask layer 20 and a second solder mask layer 50. The first solder resist layer 20 and the second solder resist layer 50 are both the outermost layers of the circuit board 100. The first solder resist layer 20 covers the first trace 12 and the other traces 14 on the first surface 10a and exposes the test pads 16. The second solder resist layer 50 covers the second trace 13 and the other traces 14 on the second surface 10 b. The first solder resist layer 20 and the second solder resist layer 50 are used to prevent each trace covered by the solder resist layer from being exposed to air and oxidized. The material of the first solder mask layer 20 and the second solder mask layer 50 may be protective paint or three-proofing glue.
As shown in fig. 1, in the first embodiment, only one first trace 12 and one second trace 13 are needed to be electrically connected between one input pin 17 and one output pin 18. That is, only one via 11 and one test pad 16 corresponding to the via 11 are provided between one input pin 17 and one output pin 18. In an alternative embodiment, more than two vias 11 and more than two test pads 16 may be disposed between one input pin 17 and one output pin 18.
As shown in fig. 6, two vias 11, two test pads 16, two first traces 12 and one second trace 13 may be disposed between one input pin 17 and one output pin 18. One of the first traces 12 is electrically connected to an input pin 17, and the other first trace 12 is electrically connected to an output pin 18. The wire change between the different layers of wires is realized between the first wire 12 and the second wire 13 through the via 11 (the test pad 16).
As shown in fig. 7, two vias 11, two test pads 16, two second traces 13 and one first trace 12 may be disposed between one input pin 17 and one output pin 18. One of the second traces 13 is electrically connected to an input pin 17, and the other second trace 13 is electrically connected to an output pin 18. The wire change between the different layers of wires is realized between the first wire 12 and the second wire 13 through the via 11 (the test pad 16).
As shown in fig. 8, the circuit board 200 of the second embodiment of the present invention has substantially the same structure as the circuit board 100 of the first embodiment, except that: in the first embodiment, the circuit board 100 is a double-layer circuit board, which includes a substrate layer and two routing layers; in the second embodiment, the circuit board 200 is a multilayer circuit board, and further includes at least one second substrate layer 30 located on a side of the second trace 13 away from the first substrate layer 10, and other traces 14 located on a surface of the second substrate layer 30. That is, in the second embodiment, the circuit board 200 includes at least two substrate layers and at least three routing layers.
In the first embodiment, the via hole 11 is a through hole penetrating all substrate layers (first substrate layers 10) of the circuit board 100. In the second embodiment, the via hole 11 is a blind hole that does not penetrate through all the substrate layers of the circuit board 200. As shown in fig. 8, the via hole 11 penetrates only the first base material layer 10 and does not penetrate the second base material layer 30. By such a design, the phenomenon of poor reliability of the electrical connection between the first trace 12 and the second trace 13 caused by moisture and the like entering the conductive body 15 from one side of the test pad 16 can be prevented.
In the first embodiment, the conductor 15 is embedded on the inner wall of the via hole 11 and has a hollow cylindrical shape; in the second embodiment, the conductive body 15 completely fills the via hole 11.
It is understood that the circuit board 200 may also be a four-layer circuit board including three substrate layers and four routing layers. The specific structure may be that in the circuit board 200 shown in fig. 8, the second substrate layer 30, the other traces 14, the second substrate layer 30, and the other traces 14 are sequentially disposed between the second trace 13 and the second solder resist layer 50. That is, two substrate layers and two wiring layers are provided between the second trace 13 and the second solder resist layer 50.
As shown in fig. 9, the circuit board 300 in the third embodiment of the present invention has substantially the same structure as the circuit board 100 in the first embodiment, except that: in the first embodiment, the circuit board 100 is a double-layer circuit board, which includes a substrate layer and two routing layers; the circuit board 300 in the third embodiment is a multilayer circuit board with more than two layers, and further includes at least one third substrate layer 40 located on a side of the first trace 12 away from the first substrate layer 10, and other traces 14 located on a surface of the third substrate layer 40. That is, in the third embodiment, the circuit board 300 includes at least two substrate layers and at least three routing layers.
As shown in fig. 9, the circuit board 300 is a four-layer circuit board, and further includes two layers of third substrate layers 40 located on the side of the first trace 12 away from the first substrate layer 10, other traces 14 located between the two layers of third substrate layers 40, and other traces 14 located between the first solder resist layer 20 and the third substrate layer 40. The via holes 11 are through holes penetrating all the substrate layers (the first substrate layer 10 and the two third substrate layers 40) of the circuit board. The other wires 14 are arranged at intervals and in an insulating way at the position of the via hole 11, and the first wire 12 arranged on the same layer, the second wire 13 arranged on the same layer or the other wires 14 arranged on the same layer are arranged.
It is understood that the circuit board 300 may also be a three-layer circuit board including two substrate layers and three routing layers. A specific structure may be the circuit board 300 shown in fig. 9, in which a layer of the third substrate layer 40 and a layer of the other traces 14 are reduced between the first trace 12 and the first solder mask layer 20. That is, only one substrate layer and one wiring layer are provided between the first trace 12 and the first solder resist layer 20.
In the embodiment of the present invention, the test pads 16 are disposed at the via holes 11, so that each test pad 16 does not occupy the area of the circuit board 100 alone, and the position corresponding to the via hole 11 can realize layer changing of routing on different routing layers and also has the function of the test pad 16. Thus, the space of the circuit board 100 is saved, and the integration level of the circuit board 100 is improved.
Still another embodiment of the present invention provides an electronic device 80. The electronic device 80 includes the first and second electronic components 60 and 70 and the circuit board 100(200, 300) described above. The first electronic element 60 is electrically connected to the first trace 12 through the input pin 17. The second electronic element 70 is electrically connected to the second trace 13 through the output pin 18. Due to the advantage of high integration of the circuit board 100(200, 300), the electronic device 80 using the circuit board 100(200, 300) has a more compact structure.
In one embodiment, the electronic device 80 may be a display panel, the first electronic element 60 may be a display driver chip, and the second electronic element 70 may be a display electrode for receiving signals from the display driver chip.
In another embodiment, the electronic device 80 may be a touch panel, the first electronic component 60 may be a touch driving chip, and the second electronic component 70 may be a touch driving electrode for receiving signals from the touch driving chip.
Although the present invention has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the spirit and scope of the present invention.
Claims (10)
1. A circuit board, comprising:
the circuit board is provided with a first base material layer and a second base material layer, wherein the first base material layer is provided with a first surface and a second surface which are opposite to each other, a through hole is defined in the circuit board, and the through hole penetrates through the first base material layer along the direction from the first surface to the second surface;
the first routing wires are positioned on the first surface;
a plurality of second routing lines positioned on the second surface;
the electric conductor is positioned in the through hole so as to electrically connect one first wire and one second wire; and
and the test pad covers and is electrically connected with the conductor.
2. The circuit board of claim 1, wherein the electrical conductor is disposed on an inner wall of the via.
3. The circuit board of claim 1, wherein the electrical conductor completely fills the via.
4. The circuit board of claim 1, further comprising a first solder mask layer on a side of the first trace away from the first substrate layer, the first solder mask layer exposing the test pad.
5. The circuit board of claim 4, further comprising at least a second substrate layer, wherein the second substrate layer is located on a side of the second trace away from the first substrate layer, and the via does not penetrate through the second substrate layer.
6. The circuit board of claim 4, further comprising at least a third substrate layer, the third substrate layer being located between the first trace and the solder resist layer, the via hole penetrating through the first substrate layer and the third substrate layer.
7. The circuit board of claim 6, further comprising a second solder mask covering a surface of the second trace.
8. The circuit board of claim 1, further comprising an input pin for inputting a signal and an output pin for outputting a signal, the input pin and the output pin being electrically connected by the first trace and the second trace.
9. The circuit board of claim 8, wherein the number of the test pads between the input pin and the output pin is one or two.
10. An electronic device, comprising a first electronic component, a second electronic component and a circuit board electrically connecting the first electronic component and the second electronic component, wherein the circuit board is the circuit board according to any one of claims 1 to 9, the first electronic component is electrically connected to the first trace, and the second electronic component is electrically connected to the second trace.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911036548.0A CN110611989A (en) | 2019-10-29 | 2019-10-29 | Circuit board and electronic device |
| TW108139821A TWI730489B (en) | 2019-10-29 | 2019-11-01 | Circuit board and electronic device using same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911036548.0A CN110611989A (en) | 2019-10-29 | 2019-10-29 | Circuit board and electronic device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110611989A true CN110611989A (en) | 2019-12-24 |
Family
ID=68895417
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911036548.0A Withdrawn CN110611989A (en) | 2019-10-29 | 2019-10-29 | Circuit board and electronic device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN110611989A (en) |
| TW (1) | TWI730489B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114286510A (en) * | 2021-12-28 | 2022-04-05 | 武汉天马微电子有限公司 | Circuit board, display module assembly and display device |
| CN114990503A (en) * | 2022-06-30 | 2022-09-02 | 业成科技（成都）有限公司 | Film coating method, film coating apparatus, and electronic apparatus |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017143193A (en) * | 2016-02-10 | 2017-08-17 | 株式会社リコー | Wiring board, wiring board design method, wiring board design assisting device, and program |
| CN206775815U (en) * | 2017-02-24 | 2017-12-19 | 昆山苏杭电路板有限公司 | Intersect the HDI printed boards of blind hole conduction beneficial to detection |
| CN207783246U (en) * | 2017-11-16 | 2018-08-28 | 江西竞超科技股份有限公司 | A kind of rapid cooling type HDI wiring boards |
| CN110277363A (en) * | 2018-03-16 | 2019-09-24 | 南茂科技股份有限公司 | Semiconductor Package Structure |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI528876B (en) * | 2012-03-22 | 2016-04-01 | 矽品精密工業股份有限公司 | Medium board and its electrical testing method |
| CN103983809A (en) * | 2013-02-08 | 2014-08-13 | 辉达公司 | PCB and online testing structure thereof, and manufacturing method of online testing structure |
| DE102018116531A1 (en) * | 2017-10-23 | 2019-06-06 | Samsung Electronics Co., Ltd. | Display device, semiconductor package and film for a package substrate |
-
2019
- 2019-10-29 CN CN201911036548.0A patent/CN110611989A/en not_active Withdrawn
- 2019-11-01 TW TW108139821A patent/TWI730489B/en active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017143193A (en) * | 2016-02-10 | 2017-08-17 | 株式会社リコー | Wiring board, wiring board design method, wiring board design assisting device, and program |
| CN206775815U (en) * | 2017-02-24 | 2017-12-19 | 昆山苏杭电路板有限公司 | Intersect the HDI printed boards of blind hole conduction beneficial to detection |
| CN207783246U (en) * | 2017-11-16 | 2018-08-28 | 江西竞超科技股份有限公司 | A kind of rapid cooling type HDI wiring boards |
| CN110277363A (en) * | 2018-03-16 | 2019-09-24 | 南茂科技股份有限公司 | Semiconductor Package Structure |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114286510A (en) * | 2021-12-28 | 2022-04-05 | 武汉天马微电子有限公司 | Circuit board, display module assembly and display device |
| CN114286510B (en) * | 2021-12-28 | 2024-01-19 | 武汉天马微电子有限公司 | Circuit board, display module and display device |
| CN114990503A (en) * | 2022-06-30 | 2022-09-02 | 业成科技（成都）有限公司 | Film coating method, film coating apparatus, and electronic apparatus |
| CN114990503B (en) * | 2022-06-30 | 2023-12-12 | 业成科技（成都）有限公司 | Coating method, coating equipment and electronic equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI730489B (en) | 2021-06-11 |
| TW202118364A (en) | 2021-05-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5847936A (en) | Optimized routing scheme for an integrated circuit/printed circuit board | |
| KR100201185B1 (en) | Thick Film Laminated Substrate and Electronic Circuit Device Using the Same | |
| US6717071B2 (en) | Coaxial via hole and process of fabricating the same | |
| US6720501B1 (en) | PC board having clustered blind vias | |
| JP6158023B2 (en) | Fine pitch interface for probe cards | |
| US10504829B2 (en) | Semiconductor package and semiconductor module including the same | |
| US5418690A (en) | Multiple wiring and X section printed circuit board technique | |
| US5723823A (en) | Circuit board with enhanced rework configuration | |
| CN109644550B (en) | Flexible printed circuit board | |
| TWI730489B (en) | Circuit board and electronic device using same | |
| US20140312488A1 (en) | Method of manufacturing wiring board unit, method of manufacturing insertion base, wiring board unit, and insertion base | |
| US6465890B1 (en) | Integrated circuit package having offset segmentation of package power and/or ground planes and methods for reducing delamination in integrated circuit packages | |
| KR100891531B1 (en) | Pattern misalignment detection device | |
| US6351391B1 (en) | Signal busses on printed board structures mounting ASIC chips with signal termination resistor devices using planar signal terminating devices | |
| KR100364507B1 (en) | Probe card | |
| US6842344B1 (en) | Multi-layer printed circuit board and signal routing therein | |
| JP2010002257A (en) | Probe card | |
| JP4045841B2 (en) | Probe card | |
| CN112566390B (en) | Multilayer flexible circuit board and preparation method thereof | |
| JP3447496B2 (en) | Wiring board for semiconductor mounting | |
| KR101124729B1 (en) | Technique for accommodating electronic components on a multilayer signal routing device | |
| TW202343000A (en) | Electrical connection device | |
| KR20090083614A (en) | Printed circuit board | |
| JPH08241935A (en) | Multilayer circuit board | |
| JP2006041318A (en) | Wiring structure and electronic equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WW01 | Invention patent application withdrawn after publication |
Application publication date: 20191224 |
|
| WW01 | Invention patent application withdrawn after publication |