CN110620630B - Time synchronization method, device, network equipment and computer readable storage medium - Google Patents
Time synchronization method, device, network equipment and computer readable storage medium Download PDFInfo
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Abstract
The embodiment of the invention provides a time synchronization method, a time synchronization device, network equipment and a computer readable storage medium. Since the scheme in which the processor performs time synchronization according to the time synchronization protocol has the advantage of fast synchronization convergence speed, the use of the scheme at the beginning of time synchronization enables fast convergence of the time offset between the device and the master device. Because the time synchronization chip can fully inhibit and filter the message data between the time synchronization chip and the master device, the time synchronization chip is switched to continue time synchronization after the time synchronization of the system clock reaches a stable state, the influence of network oscillation, interference noise and the like on a time synchronization result can be avoided, and the synchronization stability and the synchronization precision of the time synchronization of the system clock are improved.
Description
Technical Field
The present invention relates to the field of communications, and in particular, to a time synchronization method, apparatus, network device, and computer-readable storage medium.
Background
With the rise of 5G (5th Generation, fifth Generation mobile communication) network technology and the push of 5G-related application requirements and clock technology standards, the IEEE (Institute of Electrical and Electronics Engineers) 1588 time synchronization protocol plays an important role in network clock time synchronization. As an important backup of a GPS (Global Positioning System) time source, the 1588 clock provides a high-precision clock time synchronization function for the entire communication network, and provides a powerful support and guarantee for the normal operation of the network communication service.
In the prior art, a 1588 time synchronization protocol stack can be run by a CPU of a network device to interact with a master device, thereby synchronizing a system clock. However, this time synchronization scheme is not accurate because the path delay from the network device port to the CPU is uncertain. In addition, in consideration of the processing capability and processing speed of the CPU, no or only a simple suppression filtering process is generally performed in time stamp calculation and processing. Therefore, the scheme also has the defects of sensitivity to network oscillation and noise interference and poor stability.
Therefore, it is needed to provide a new time synchronization scheme to solve the problems of low accuracy and poor stability of the existing time synchronization scheme.
Disclosure of Invention
The time synchronization method, the time synchronization device, the network equipment and the computer readable storage medium provided by the embodiment of the invention mainly solve the technical problems that: a new time synchronization scheme is provided to solve the problems of low precision and poor stability of the existing time synchronization scheme.
To solve the foregoing technical problem, an embodiment of the present invention provides a time synchronization method, including:
the processor carries out time synchronization on the system clock according to a time synchronization protocol;
and when the time synchronization of the system clock is determined to reach a stable state, the time synchronization chip is switched to continue to perform time synchronization on the system clock.
Optionally, switching to continue time synchronization of the system clock by the synchronization chip includes:
controlling a system clock to output time to a time synchronization chip;
and after the time synchronization chip locks the time of the system clock, controlling the time synchronization chip to perform time synchronization on the system clock and stopping the time synchronization of the processor on the system clock.
Optionally, determining that the time synchronization of the system clock reaches a steady state comprises:
and determining that the time deviation delta t between the equipment and the main equipment is smaller than the preset deviation delta Th for N times in continuous K-time synchronous detection, wherein N and K are positive integers larger than 0, and K is larger than or equal to N.
Optionally, N is equal to K.
Optionally, the time synchronization protocol is a precision clock synchronization protocol standard PTP of the network measurement and control system.
Optionally, after controlling the synchronization chip to continue time synchronization of the system clock, the method further includes:
and when the synchronous chip is in an abnormal state, the control processor continues to carry out time synchronization on the system clock according to the time synchronization protocol.
An embodiment of the present invention further provides a time synchronization apparatus, including:
the first synchronization module is used for carrying out time synchronization on the system clock according to a time synchronization protocol;
the synchronous detection module is used for detecting whether the time synchronization of the system clock reaches a stable state;
and the second synchronization module is used for switching the time synchronization chip to continue to perform time synchronization on the system clock after the time synchronization of the system clock is determined to reach a stable state.
The embodiment of the invention also provides network equipment, which comprises a processor, a memory, a time synchronization chip, a communication unit and a communication bus;
the communication bus is used for realizing the connection and communication between the processor and the memory, the time synchronization chip and the communication unit respectively;
the processor is configured to execute one or more programs stored in the memory to implement the steps of the time synchronization method as in any one of the above.
Optionally, the time synchronization chip is a 1588 functional chip.
Embodiments of the present invention also provide a computer storage medium, in which one or more programs are stored, and the one or more programs can be executed by one or more processors to implement the steps of the time synchronization method as described in any one of the above.
The invention has the beneficial effects that:
according to the time synchronization method, the time synchronization device, the network equipment and the computer readable storage medium provided by the embodiment of the invention, the processor firstly carries out time synchronization on the system clock according to the time synchronization protocol, and when the time synchronization of the system clock reaches a stable state, the time synchronization chip is switched to continue carrying out time synchronization on the system clock. Since the scheme in which the processor performs time synchronization according to the time synchronization protocol has the advantage of fast synchronization convergence speed, the use of the scheme at the beginning of time synchronization enables fast convergence of the time offset between the device and the master device. Because the time synchronization chip can fully inhibit and filter the message data between the time synchronization chip and the master device, the time synchronization chip is switched to continue time synchronization after the time synchronization of the system clock reaches a stable state, the influence of network oscillation, interference noise and the like on a time synchronization result can be avoided, and the synchronization stability and the synchronization precision of the time synchronization of the system clock are improved.
Additional features and corresponding advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
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Fig. 1 is a flowchart of a time synchronization method according to an embodiment of the present invention;
FIG. 2 is a flowchart illustrating a method for switching the time synchronization of the system clock by the time synchronization chip according to the first embodiment of the present invention;
fig. 3 is a flowchart of a time synchronization method according to a second embodiment of the present invention;
fig. 4 is a schematic diagram of a display interface of a network device according to a second embodiment of the present invention;
fig. 5 is a schematic structural diagram of a time synchronization apparatus according to a third embodiment of the present invention;
fig. 6 is a schematic structural diagram of a time synchronization apparatus according to a fourth embodiment of the present invention;
fig. 7 is a schematic diagram of a hardware structure of a network device according to a fifth embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention are described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The first embodiment is as follows:
the IEEE1588 time Synchronization Protocol is called the Precision Clock Synchronization Protocol standard (IEEE1588Precision Clock Synchronization Protocol) of the network measurement and control system, which is referred to as PTP (Precision timing Protocol) for short. The method supports time synchronization between the master device and the slave device in a packet switching mode, and has sub-microsecond time synchronization precision. The 1588 time synchronization system can be realized in a pure software mode, for example, a 1588 protocol stack is realized by using a CPU, so as to complete the receiving and sending of PTP messages, timestamp processing and time synchronization. The 1588 time synchronization system realized by using pure software of the CPU has the advantages that: the implementation is simple, only the 1588 protocol stack needs to be maintained, and the method is irrelevant to the specific hardware of the bottom layer; the synchronous convergence is fast; low cost and the like. However, the packet sending rate of the PTP message is low due to the performance limitation of the CPU. Moreover, due to the uncertainty of the path delay from the device port to the CPU and the delay of the software processing, the time method cannot achieve high accuracy.
In order to improve the precision of time synchronization, a 1588 time synchronization system can be realized by combining CPU software and underlying hardware. The CPU software is responsible for the operation of the protocol stack and issues the calculation result of each time of receiving and sending message synchronization to adjust the bottom layer hardware. The bottom layer hardware is responsible for the delay measurement and correction of the message on the internal transmission path of the equipment. By the method, the time synchronization precision of the network equipment can be greatly improved (nanosecond level can be achieved), and the synchronization convergence speed is very high. However, this approach generally does not or only does a simple suppression filtering process in time stamp calculation and processing, considering the processing power and speed of the CPU. Therefore, the time synchronization result is very sensitive to network oscillation and noise interference, and the stability of time synchronization is poor.
In order to get rid of the limitation of the CPU software implementation in the above scheme, adding a special 1588 functional chip may be considered when designing a scheme of the 1588 time synchronization system. The 1588 functional chip can operate a 1588 protocol stack independently of the CPU, receive and transmit PTP messages and perform timestamp processing and operation. The CPU only needs to do configuration management work of the 1588 functional chip, and compared with the operation of the whole 1588 protocol stack, the expense of the CPU can be ignored. In order to ensure the stability of 1588 time synchronization, the 1588 functional chip performs sliding window filtering processing on message data during synchronization. The processing can prevent the clock time synchronization from being influenced by the network oscillation, but at the same time, the sliding window filtering processing also increases the time length that the synchronization tends to be stable, and although the larger the sliding window is, the better the effect of preventing the network oscillation is, the longer the time required for the time synchronization to reach the stable state is. Especially, when the difference between the starting synchronization time of the 1588 functional chip and the time of the opposite terminal device is too large, the time length required for synchronization convergence is obviously increased.
In order to solve the problem that the synchronization precision and the synchronization stability are poor when the CPU pure software realizes time synchronization, a 1588 functional chip is used for time synchronization, and the problem that the synchronization convergence time is long is increased while the precision and the stability of time synchronization are improved, this embodiment provides a time synchronization scheme, please refer to fig. 1:
s102: the processor time-synchronizes the system clock according to a time synchronization protocol.
When two network devices interact, it is necessary to ensure that the system times of the two network devices are consistent, and in a general case, the slave device synchronizes the time of its own system clock according to the time of the master device. Therefore, in the present embodiment, the time synchronization method may be performed by the slave device. After the time synchronization starts, the slave device may control the processor of the slave device to perform time synchronization on the system clock of the slave device according to the time synchronization protocol. It should be understood that the term "processor time-synchronizes the system clock" as used herein refers to a scenario in which the processor performs a main operation such as running a protocol stack when time-synchronizing the system clock, and the processor simply participates in the time synchronization of the system clock, for example, if the processor merely performs parameter configuration on a time synchronization chip and does not perform other operations of time synchronization, such a situation cannot be considered as time synchronization performed by the processor. The following describes a process of time synchronizing a system clock by a processor according to a time synchronization protocol, for example:
the slave device controls the processor to run the time synchronization protocol stack, time synchronization message receiving and sending are carried out between the slave device and the master device, then time deviation between the slave device and the master device is calculated according to the message timestamp, and then time of a system clock is adjusted according to the calculation result, so that time synchronization of the system clock of the slave device is achieved.
It should be understood that, when the processor runs the time synchronization protocol stack to perform time synchronization on the system clock, only simple suppression filtering processing is performed, or even no time filtering processing is performed at all, so that when the slave device control processor synchronizes the system clock according to the time synchronization protocol, the time of the system clock can reach synchronization convergence more quickly. When the control processor performs time synchronization on the system clock, the slave device detects the current time synchronization of the system clock and determines whether the time synchronization of the system clock meets the requirement of reaching a stable state.
S104: and after the time synchronization of the system clock is determined to reach a stable state, the time synchronization chip is switched to continue to perform time synchronization on the system clock.
After the time synchronization of the system clock is determined to reach the stable state, the slave device can control the switching to continue the time synchronization of the system clock by the time synchronization chip. Thus, when the time synchronization is performed by the time synchronization chip during switching, the time synchronization of the time synchronization chip can cross the process of synchronization unconvergence, so that the problem of low synchronization convergence speed of the time synchronization chip is avoided. In an example of this embodiment, the slave device detects whether the time synchronization of the system clock reaches a stable state while the controller processor performs the time synchronization, and switches the time synchronization chip to continue the time synchronization of the system clock once the time synchronization of the system clock reaches the stable state is detected. Of course, in some special cases, the processor may continue to perform time synchronization for a period of time after the time synchronization of the system clock reaches a steady state, and then switch to the synchronization stage in which the time synchronization chip performs synchronization.
The synchronization of the system clock to a steady state has two requirements: firstly, the time synchronization precision of a system clock meets the requirement; secondly, the time synchronization of the system clock tends to be stable, that is, the time difference between the system clock and the master device has small fluctuation. In order to determine whether the time synchronization of the system clock reaches a stable state, the slave device performs a synchronization detection after the processor calculates the time deviation between the current time of the system clock and the time of the master device each time, and determines whether the time deviation Δ t between the system clock of the slave device and the master device is smaller than a preset deviation Δ Th. If the slave device determines that all the N detection results are that Δ t is smaller than Δ Th in the consecutive K detections, it may be determined that the time synchronization of the system clock of the device has currently reached a stable state. For example, if K is set to 50 and N is set to 45, then at least in the last 50 synchronization detections of the slave device, at least 45 detections exist, where Δ t is smaller than Δ Th, and it can be determined that the time synchronization of the system clock has reached a steady state. Of course, in some examples of this embodiment, the values of K and N may also be set to be the same, that is, N is equal to K, in this case, as long as the slave determines that all the detection results obtained from K consecutive times are Δ t smaller than Δ Th, it may be determined that the time synchronization of the system clock reaches the stable state. For example, if the slave device detects that the time deviation Δ t between the system clock and the master device is less than the preset deviation Δ Th 5 times in succession, it may be determined that the time synchronization of the system clock is in a steady state, and the time synchronization chip may be switched to continue time synchronization of the system clock.
The general process of time synchronizing the system clock by the time synchronization chip is basically similar to the general process of time synchronizing the system clock by the processor: the time synchronization chip is independent of the processor running time synchronization protocol stack, so that the slave equipment and the master equipment receive and transmit time synchronization messages, calculate the time deviation between the equipment and the master equipment, and adjust the time of a system clock according to the time deviation.
It should be understood that the foregoing "continue" means that the time synchronization chip performs time synchronization on the system clock based on the time synchronization that has been performed by the processor, and therefore, when switching to perform time synchronization by the time synchronization chip, the slave device should ensure that the time synchronization chip acquires the current time of the system clock first. In this embodiment, the process of switching from time synchronization of the system clock by the processor to time synchronization of the system clock by the time synchronization chip can be seen from the flowchart of fig. 2:
s202: and controlling the system clock to output time to the time synchronization chip.
In the process of controlling the processor to perform time synchronization on the system clock, the slave device may simultaneously detect whether the time synchronization of the system clock meets a requirement of reaching a stable state, and if the detection result represents that the current time synchronization reaches the stable state, the slave device may control the system clock to output time to the time synchronization chip, so that the time synchronization chip may lock the time of the system clock, and in the process, the time synchronization chip may obtain a synchronization result of performing time synchronization on the processor, and the synchronization result may be used as a basis for subsequent time synchronization on the time synchronization chip.
S204: and after the time synchronization chip locks the time of the system clock, controlling the time synchronization chip to perform time synchronization on the system clock and stopping the time synchronization of the processor on the system clock.
After detecting that the time synchronization chip has locked the time of the system clock output, the slave device may control the time synchronization chip to perform time synchronization on the system clock, and simultaneously stop the time synchronization of the processor on the system clock. Thereafter, the synchronization time received by the system clock should be output by the time synchronization chip.
It should be understood that, although the time synchronization process of the time synchronization chip to the system clock is substantially similar to the time synchronization process of the processor to the system clock, in the embodiment, the time synchronization chip performs the sliding window filtering process on the received and transmitted message data, so that the time synchronization result of the system clock can be prevented from being affected by the network oscillation and the interference noise. Therefore, the time synchronization method provided by this embodiment can integrate the advantages of fast synchronization convergence when the processor performs time synchronization and the advantages of good synchronization stability and high synchronization precision when the time synchronization chip performs time synchronization.
The time synchronization protocol in this embodiment may be a PTP protocol, and the time synchronization chip may be a 1588 functional chip, or another chip for time synchronization having a similar function to the 1588 functional chip. The 1588 functional chip has a great advantage in the packet sending rate of the message compared with the mode that a PTP protocol stack is operated by a processor, and can well cope with scenes with high requirements on the message sending and receiving rate, such as frequency recovery.
In the time synchronization method provided by this embodiment, a processor is first used to run a time synchronization protocol stack to perform time synchronization on a system clock, so that the time synchronization is rapidly converged. After the time synchronization of the system clock is determined to be in a stable state, the time synchronization chip can be switched to be adopted, and the subsequent time synchronization is continuously carried out on the basis of the time synchronization result of the processor, so that the time synchronization has better synchronization precision and stability, and the synchronization effect of the system clock is improved.
Furthermore, the time synchronization chip has a better message transmitting and receiving rate, so that the time synchronization chip is suitable for carrying out frequency synchronization on a system clock and can meet the requirements of scenes such as frequency recovery.
Example two:
the present embodiment will continue to further describe the time synchronization method provided in the present embodiment with reference to some specific examples, please refer to the flowchart of the time synchronization method shown in fig. 3:
in this embodiment, a time synchronization protocol is 1588, that is, a PTP protocol, and a time synchronization chip is a 1588 functional chip, which is taken as an example for description, but it should be understood by those skilled in the art that this is only an example given in this embodiment, and is not the only implementation manner of the present invention. In the slave device, the system clock may be implemented by an FPGA (Field-Programmable Gate Array), and provided to each device, module, and the like that require use of the system time in the device.
S302: the processor time-synchronizes the system clock according to a time synchronization protocol.
The slave device control processor runs the time synchronization protocol stack according to the time synchronization protocol, performs message interaction with the master device, calculates the time deviation between the slave device control processor and the master device according to the message timestamp, and adjusts the time of the system clock according to the time deviation. It should be understood that the processor controls the communication unit of the slave device to perform messaging with the master device when running the time synchronization protocol stack.
S304: and detecting whether the time synchronization of the system clock reaches a stable state.
If so, it indicates that the time synchronization of the system clock has currently reached the stable state, and therefore the process may proceed to S306, otherwise, it indicates that the time synchronization of the system clock has not reached the stable state, and therefore S302 needs to be continuously performed. In this embodiment, whether the time synchronization of the system clock reaches the steady state or not is detected, and whether the number of consecutive times that the time deviation Δ t between the system clock and the master device is smaller than the preset deviation Δ Th reaches the preset number or not may be detected.
It should be understood that the value of the preset number of times is related to the current synchronized network environment. For example, in a synchronization environment supported by a synchronous ethernet, the value of the preset number of times may be appropriately reduced, and in a synchronization environment that does not support a synchronous ethernet, such as a simple 1588 synchronization environment, the value of the preset number of times may be appropriately increased. Similarly, the value of the Δ Th is also related to the current synchronization network environment, and in the synchronization environment supported by the synchronous ethernet, the value of the Δ Th can be appropriately reduced, and in the environment that does not support the synchronous ethernet, such as a simple 1588 synchronization environment, the value of the Δ Th can be appropriately increased. However, the value of Δ Th cannot be lower than the synchronization precision supported by the slave device, for example, for a slave device whose time precision is 8ns, the value of Δ Th should be greater than or equal to 8 ns. Considering that the synchronization precision of the processor is not high, the value of Δ Th is usually greater than 8ns for a slave device with time precision of 8ns supported by itself.
S306: and controlling the system clock to output time to the time synchronization chip.
After the slave device detects that the time synchronization of the system clock reaches a stable state, the slave device may control the system clock to output time to the time synchronization chip, that is, the system clock transmits the time synchronization result of the processor to the time synchronization chip.
S308: and controlling the time synchronization chip to continuously perform time synchronization on the system clock.
After the time of the system clock is locked by the time synchronization chip is ensured, the slave device controls switching to enable the system clock to carry out time synchronization according to the output of the time synchronization chip, and at the moment, the processor does not need to run the time synchronization protocol stack to carry out message interaction with the master device, so that the processing overhead of the processor can be reduced to the greatest extent. In addition, because the speed of the time synchronization chip for transmitting and receiving messages by running the time synchronization protocol stack can meet the requirement of frequency recovery, the frequency of the system clock can be synchronized with the frequency of the master device after the time synchronization chip is controlled to continue to perform time synchronization on the system clock.
S310: and detecting whether the time synchronization chip is in an abnormal state or not.
While controlling the time synchronization chip to perform time synchronization on the system clock, the slave device also detects the operation of the time synchronization chip to determine whether the time synchronization chip is in an abnormal state, for example, whether the time synchronization chip is in a fault, and if it is determined that the time synchronization chip is in the abnormal state, S312 is entered, otherwise S308 is continuously performed.
S312: the switching is time synchronized to the system clock by the processor.
If the time synchronization chip is determined to be in an abnormal state, the slave device can control to switch to the processor to perform time synchronization on the system clock, so that the system clock does not perform time synchronization according to the output of the time synchronization chip any more, and at the moment, the slave device can control to close the time synchronization chip. In addition, the slave equipment can also send out alarm information to prompt the manager of the slave equipment that the time synchronization chip is abnormal, so that the manager can timely process the abnormal condition. Fig. 4 is a schematic diagram of a display interface for sending a prompt message to a manager after the network device detects a fault of a 1588 functional chip, and it should be understood that, in addition to the manner of sending a prompt to the manager through display, the network device may also send an alarm through sending a prompt tone, sending a prompt voice, and the like.
In addition, after switching back to the time synchronization of the system clock by the processor, the slave device does not need to switch the time synchronization mode according to the fact that the time synchronization of the system clock reaches the stable state, and therefore the slave device does not need to detect whether the time synchronization of the system clock reaches the stable state.
The time synchronization method provided by the embodiment not only integrates the respective advantages of the scheme of performing time synchronization by using the processor to run the protocol stack and the scheme of performing time synchronization by using the time synchronization chip, so that the whole time synchronization process has the advantages of high synchronization convergence speed, high synchronization precision, good synchronization stability and the like; and moreover, the advantage of high message receiving and transmitting speed of the time synchronization chip can be utilized to carry out frequency synchronization on the system clock. Furthermore, in the process of performing time synchronization on the system clock by using the time synchronization chip, the slave device also monitors whether the time synchronization chip fails, and switches to the processor to continue time synchronization when the time synchronization chip cannot normally work, so as to avoid the problem that the normal work of the system is seriously affected by incapability of outputting or abnormal output clock when the time synchronization chip has a hardware failure.
Example three:
referring to fig. 5, the time synchronizer 50 includes a software synchronization module 502 and a chip synchronization module 504. The first synchronization module 502 is configured to control the processor to perform time synchronization on the system clock according to a time synchronization protocol, and the synchronization detection module 504 is configured to detect whether the time synchronization of the system clock reaches a stable state; the second synchronization module 506 is configured to switch the time synchronization chip to continue time synchronization of the system clock after the detection result of the synchronization detection module 504 is yes.
When two network devices interact, it is necessary to ensure that the system times of the two network devices are consistent, and in a general case, the slave device synchronizes the time of its own system clock according to the time of the master device. Therefore, in the present embodiment, the time synchronizer 50 may be deployed on various network devices serving as slave devices. After the time synchronization starts, the first synchronization module 502 may perform time synchronization on the system clock of the device according to a time synchronization protocol. It should be understood that the term "the first synchronization module 502 performs time synchronization on the system clock" refers to a scenario where the first synchronization module 502 performs a main operation of running a protocol stack and the like when performing time synchronization on the system clock, but the first synchronization module 502 does not simply participate in the time synchronization on the system clock, for example, if the first synchronization module 502 performs only parameter configuration on a time synchronization chip and does not perform other operations of time synchronization, such a scenario cannot be regarded as the first synchronization module 502 performs time synchronization. The following describes a process of the first synchronization module 502 performing time synchronization on the system clock according to a time synchronization protocol, for example:
the first synchronization module 502 runs the time synchronization protocol stack, performs time synchronization message transmission and reception with the master device, calculates the time deviation between the device and the master device according to the message timestamp, and then adjusts the time of the system clock according to the calculation result to realize the time synchronization of the system clock of the device.
It should be understood that, since the first synchronization module 502 only performs simple suppression filtering or even does not perform time filtering at all when running the time synchronization protocol stack to perform time synchronization on the system clock, when the first synchronization module 502 synchronizes the system clock according to the time synchronization protocol, the time of the system clock can reach synchronization convergence more quickly. While time synchronization is performed on the system clock, the synchronization detection module 504 detects the current time synchronization of the system clock, and determines whether the time synchronization of the system clock reaches a stable state.
After the synchronization detection module 504 determines that the time synchronization of the system clock reaches a stable state, the second synchronization module 506 may control the switching to continue the time synchronization of the system clock by the time synchronization chip. Thus, when the time synchronization is performed by the time synchronization chip during switching, the time synchronization of the time synchronization chip can cross the process of synchronization unconvergence, so that the problem of low synchronization convergence speed of the time synchronization chip is avoided. In an example of the embodiment, while the first synchronization module 502 controls the processor to perform time synchronization, the synchronization detection module 504 detects whether the time synchronization of the system clock reaches a stable state, and once the time synchronization of the system clock reaches the stable state, the second synchronization module 506 immediately controls the time synchronization chip to continue time synchronization. Of course, in some special cases, the first synchronization module 502 may continue to perform time synchronization for a period of time by using the processor after the synchronization detection module 504 detects that the time synchronization of the system clock reaches a stable state, and then the second synchronization module 506 switches to the synchronization phase performed by the time synchronization chip.
The synchronization of the system clock to a steady state has two requirements: firstly, the time synchronization precision of a system clock meets the requirement; secondly, the time synchronization of the system clock tends to be stable, that is, the time difference between the system clock and the master device has small fluctuation. In order to determine whether the time synchronization of the system clock reaches a stable state, the synchronization detection module 504 performs a synchronization detection after the processor calculates the time deviation between the current time of the system clock and the time of the master device each time, and determines whether the time deviation Δ t between the system clock of the device and the master device is smaller than the preset deviation Δ Th. If the synchronization detection module 504 determines that all of the N detection results are Δ t smaller than Δ Th in the consecutive K detections, it may be determined that the time synchronization of the system clock of the device has currently reached the stable state. For example, if K is set to 50 and N is set to 45, then at least in the last 50 synchronization detections of the synchronization detection module 504, at least 45 detections are such that Δ t is smaller than Δ Th, and it can be determined that the time synchronization of the system clock has reached the steady state. Of course, in some examples of this embodiment, the values of K and N may also be set to be the same, that is, N is equal to K, in this case, only if the synchronization detection module 504 determines that all the detection results obtained after K consecutive times are Δ t smaller than Δ Th, it may be determined that the time synchronization of the system clock reaches the stable state. For example, if the synchronization detecting module 504 continuously detects that the time deviation Δ t between the system clock and the master device is less than the preset deviation Δ Th 5 times, it may be determined that the time synchronization of the system clock reaches the stable state, and the time synchronization chip may switch to continue to perform the time synchronization on the system clock.
The general process of the second synchronization module 506 controlling the time synchronization chip to time synchronize the system clock is substantially similar to the general process of the processor to time synchronize the system clock: the second synchronization module 506 controls the time synchronization chip to transmit and receive the time synchronization message with the master device independently of the processor running time synchronization protocol stack, calculates the time deviation between the device and the master device, and adjusts the time of the system clock according to the time deviation.
It should be understood that the foregoing "continue" means that the time synchronization chip time synchronizes the system clock based on the time synchronization that has been performed by the processor, and therefore, when switching to the time synchronization chip for time synchronization, the second synchronization module 506 should ensure that the time synchronization chip first acquires the current time of the system clock.
In the process of controlling the processor to perform time synchronization on the system clock by the first synchronization module 502, the synchronization detection module 504 may simultaneously detect whether the time synchronization of the system clock is in a stable state, and if the detection result indicates that the time synchronization of the system clock is in the stable state, the second synchronization module 506 may control the system clock to output time to the time synchronization chip, so that the time synchronization chip may lock the time of the system clock.
After detecting that the time synchronization chip has locked the time of the system clock output, the second synchronization module 506 may control the time synchronization chip to perform time synchronization on the system clock, and simultaneously stop the time synchronization of the processor on the system clock. Thereafter, the synchronization time received by the system clock should be output by the time synchronization chip.
It should be understood that, although the time synchronization process of the time synchronization chip to the system clock is substantially similar to the time synchronization process of the processor to the system clock, in the embodiment, the time synchronization chip performs the sliding window filtering process on the received and transmitted message data, so that the time synchronization result of the system clock can be prevented from being affected by the network oscillation and the interference noise. Therefore, the time synchronizer 50 provided in this embodiment can integrate the advantages of fast synchronization convergence when the processor performs time synchronization and the advantages of good synchronization stability and high synchronization accuracy when the time synchronization chip performs time synchronization.
The time synchronization protocol in this embodiment may be a PTP protocol, and the time synchronization chip may be a 1588 functional chip, or another chip for time synchronization having a similar function to the 1588 functional chip. The 1588 functional chip has a great advantage in the packet sending rate of the message compared with the mode that a PTP protocol stack is operated by a processor, and can well cope with scenes with high requirements on the message sending and receiving rate, such as frequency recovery.
The time synchronization device provided in this embodiment first uses a processor running time synchronization protocol stack to perform time synchronization on a system clock, so that the time synchronization is rapidly converged. After the time synchronization of the system clock is determined to be in a stable state, the time synchronization chip can be switched to be adopted, and the subsequent time synchronization is continuously carried out on the basis of the time synchronization result of the processor, so that the time synchronization has better synchronization precision and stability, and the synchronization effect of the system clock is improved.
Furthermore, the time synchronization chip has a better message transmitting and receiving rate, so that the time synchronization chip is suitable for carrying out frequency synchronization on a system clock and can meet the requirements of scenes such as frequency recovery.
Example four:
in this embodiment, it is assumed that the time synchronization protocol is 1588 time synchronization protocol, that is, PTP protocol, and the time synchronization chip is 1588 functional chip, but it should be understood by those skilled in the art that this is only an example given in this embodiment and is not the only implementation manner of the present invention.
Please refer to a schematic structural diagram of the time synchronization apparatus shown in fig. 6: the time synchronization apparatus 60 includes a first synchronization module 602, a synchronization detection module 604, a second synchronization module 606, and an exception handling module 608, wherein the first synchronization module 602, the synchronization detection module 604, and the second synchronization module 606 have similar functions to those of the modules in fig. 5, and the exception handling module 608 is configured to control the processor to continue to perform time synchronization on the system clock according to the time synchronization protocol when the synchronization chip is in an abnormal state. The following describes the process of time synchronizing the system clock of the slave device by the time synchronizer 60:
the first synchronization module 602 controls the processor to run the time synchronization protocol stack according to the time synchronization protocol, perform message interaction with the master device, calculate a time offset between the processor and the master device according to the message timestamp, and adjust the time of the system clock according to the time offset. It should be understood that the processor, when running the time synchronization protocol stack, is messaging with the master device by controlling the communication unit of the slave device.
While the first synchronization module 602 controls the processor to run the time synchronization protocol stack to time synchronize the system clock, the synchronization detection module 604 may detect whether the time synchronization of the system clock reaches a steady state. If the determination result of the synchronization detection module 604 is yes, it indicates that the time synchronization of the system clock has currently reached a stable state, and therefore, the second synchronization module 606 may start to operate. Otherwise, the system clock is not synchronized to a steady state and is therefore continuously operated by the first synchronization module 602. In this embodiment, the synchronization detecting module 604 detects whether the time synchronization of the system clock reaches a stable state, and may detect whether the consecutive times that the time deviation Δ t between the system clock and the master device is smaller than the preset deviation Δ Th reach the preset times.
It should be understood that the value of the preset number of times is related to the current synchronized network environment. For example, in a synchronization environment supported by a synchronous ethernet, the value of the preset number of times may be appropriately reduced, and in a synchronization environment that does not support a synchronous ethernet, such as a simple 1588 synchronization environment, the value of the preset number of times may be appropriately increased. Similarly, the value of the Δ Th is also related to the current synchronization network environment, and in the synchronization environment supported by the synchronous ethernet, the value of the Δ Th can be appropriately reduced, and in the environment that does not support the synchronous ethernet, such as a simple 1588 synchronization environment, the value of the Δ Th can be appropriately increased. However, the value of Δ Th cannot be lower than the synchronization precision supported by the slave device, for example, for a slave device whose time precision is 8ns, the value of Δ Th should be greater than or equal to 8 ns. Considering that the synchronization precision of the processor is not high, the value of Δ Th is usually greater than 8ns for a slave device with time precision of 8ns supported by itself.
After the synchronization detection module 604 detects that the time synchronization of the system clock reaches a stable state, the second synchronization module 606 may control the system clock to output time to the time synchronization chip, that is, the system clock transmits the time synchronization result of the processor to the time synchronization chip.
After the time of locking the system clock by the time synchronization chip is ensured, the second synchronization module 606 controls switching to enable the system clock to perform time synchronization according to the output of the time synchronization chip, and at the moment, the processor does not need to run the time synchronization protocol stack to perform message interaction with the master device, so that the processing overhead of the processor can be reduced to a great extent. In addition, because the speed of the time synchronization chip for transmitting and receiving messages by running the time synchronization protocol stack can meet the requirement of frequency recovery, the frequency of the system clock can be synchronized with the frequency of the master device after the time synchronization chip is controlled to continue to perform time synchronization on the system clock.
When the time synchronization chip is controlled to perform time synchronization on the system clock, the exception handling module 608 detects the operation of the time synchronization chip to determine whether the time synchronization chip is in an abnormal state, for example, whether the time synchronization chip is in a fault, and if it is determined that the time synchronization chip is in the abnormal state, the exception handling module 608 switches to perform time synchronization on the system clock by the processor, so that the system clock does not perform time synchronization according to the output of the time synchronization chip any more, and at this time, the exception handling module 608 may control to turn off the time synchronization chip. In addition, the exception handling module 608 may further enable the slave device to send an alarm message to prompt a manager of the slave device that the time synchronization chip is abnormal, so that the manager can handle the abnormal condition in time. Fig. 4 is a schematic diagram of a display interface for sending a prompt message to a manager after the network device detects a fault of a 1588 functional chip, and it should be understood that, in addition to the manner of sending a prompt to the manager through display, the network device may also send an alarm through sending a prompt tone, sending a prompt voice, and the like.
In addition, after switching back to the time synchronization of the system clock by the processor, the second synchronization module 606 will not switch the time synchronization mode according to the time synchronization of the system clock reaching the steady state, and therefore the synchronization detection module 604 does not need to detect whether the time synchronization of the system clock reaches the steady state. Both the sync detection module 604 and the secondary synchronization module 606 may be in a sleep state.
The time synchronization apparatus provided in the present embodiment and the third embodiment may be deployed on a network device, where functions of the first synchronization module, the synchronization detection module, the second synchronization module, and the exception handling module may be implemented by a processor of the network device.
The time synchronization device provided by the embodiment not only integrates respective advantages of a scheme of performing time synchronization by using a processor to run a protocol stack and a scheme of performing time synchronization by using a time synchronization chip, so that the whole time synchronization process has the advantages of high synchronization convergence speed, high synchronization precision, good synchronization stability and the like; and moreover, the advantage of high message receiving and transmitting speed of the time synchronization chip can be utilized to carry out frequency synchronization on the system clock. Furthermore, in the process of performing time synchronization on the system clock by using the time synchronization chip, the slave device also monitors whether the time synchronization chip fails, and switches to the processor to continue time synchronization when the time synchronization chip cannot normally work, so as to avoid the problem that the normal work of the system is seriously affected by incapability of outputting or abnormal output clock when the time synchronization chip has a hardware failure.
Example five:
in this embodiment, the computer-readable storage medium may store a time synchronization program, and the time synchronization program may be executed by one or more processors to implement any one of the time synchronization methods described in the foregoing first and second embodiments.
The embodiment also provides a network device, please refer to the schematic diagram of the hardware structure of the network device 7 shown in fig. 7:
the network device 7 includes a processor 71, a memory 72, a time synchronization chip 73, a communication unit 74, and a communication bus 75 for implementing communication connection between the processor 71 and each of the memory 72, the time synchronization chip 73, and the communication unit 74, where the memory 72 may be the aforementioned storage medium storing the time synchronization program. The processor 71 can read the time synchronization program stored in the memory 72, compile and execute the time synchronization method according to any one of the first and second embodiments.
In this embodiment, the processor 71 of the network device 7 performs time synchronization on the system clock of the device according to a time synchronization program, which may be performed according to a 1588 time synchronization protocol, and the time synchronization chip 73 may also be a 1588 functional chip. The time synchronization procedure of the network device 7 is briefly described below:
the processor 71 may run a time synchronization protocol stack, for example, a 1588 time synchronization protocol stack, to control the communication unit 74 to perform message interaction with the host device, calculate a time offset between the host device and the host device according to the message timestamp, and perform synchronization adjustment on the system time of the host device according to the time offset. The processor 71, while running the protocol stack to synchronize the time of the system clock, also detects whether the time synchronization of the system clock has reached a stable state, and if the detection result is yes, the processor 71 notifies the time synchronization chip 73 to continue synchronizing the time of the system clock. Alternatively, the processor 71 may notify the system clock, for example, the FPGA chip outputs time to the time synchronization chip 73, and after determining the time when the time synchronization chip 73 locks the system clock, the processor 71 may stop running the time synchronization protocol stack, and the time synchronization chip 73 independently runs the time synchronization protocol stack to synchronize the system clock.
In addition, while the time synchronization chip 73 synchronizes the system clock, the processor 71 may also monitor the operating state of the time synchronization chip 73, and if it is determined that the time synchronization chip 73 is in an abnormal state, for example, the time synchronization chip 73 fails, the processor 71 will continue to run the protocol stack to perform time synchronization on the system clock. Meanwhile, the processor 71 may control to turn off the abnormal time synchronization chip 73, so as to avoid the time synchronization chip 73 outputting wrong synchronization information to the system clock.
For further details of the time synchronization of the network device 7, reference may be made to the description of the foregoing embodiments, which are not described herein again.
The network device and the computer-readable storage medium provided by the embodiment ensure that the synchronization convergence speed of the system clock time synchronization is high, the synchronization precision is high, and the synchronization stability is good. Meanwhile, after the time synchronization chip fails, the processor can be switched to continue time synchronization immediately, and the problem that the normal work of the system is influenced by the hardware failure of the time synchronization chip is avoided.
It will be apparent to those skilled in the art that the modules or steps of the embodiments of the invention described above may be implemented in a general purpose computing device, they may be centralized on a single computing device or distributed across a network of multiple computing devices, and alternatively, they may be implemented in program code executable by a computing device, such that they may be stored on a computer storage medium (ROM/RAM, magnetic disk, optical disk) and executed by a computing device, and in some cases, the steps shown or described may be performed in an order different than that described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple ones of them may be fabricated into a single integrated circuit module. Thus, the present invention is not limited to any specific combination of hardware and software.
The foregoing is a more detailed description of embodiments of the present invention, and the present invention is not to be considered limited to such descriptions. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (9)
1. A method of time synchronization, comprising:
the processor carries out time synchronization on the system clock according to a time synchronization protocol;
after the time synchronization of the system clock is determined to reach a stable state, switching a time synchronization chip to continue to perform time synchronization on the system clock;
the switching to continue the time synchronization of the system clock by the time synchronization chip comprises:
controlling the system clock to output time to the time synchronization chip;
and after the time synchronization chip locks the time of the system clock, controlling the time synchronization chip to perform time synchronization on the system clock, and stopping the time synchronization of the processor on the system clock.
2. The method of time synchronization of claim 1, wherein the determining that the time synchronization of the system clock reaches a steady state comprises:
and determining that the time deviation delta t between the equipment and the main equipment is less than the preset deviation delta Th for a preset time.
3. The time synchronization method according to claim 2, wherein the determining that the number of times that the time deviation Δ t between the own device and the master device is smaller than the preset deviation Δ Th reaches a preset number of times includes:
and determining whether the continuous times that the time deviation delta t between the equipment and the main equipment is smaller than the preset deviation delta Th reach the preset times.
4. The method for time synchronization of claim 1, wherein the time synchronization protocol is a precision clock synchronization protocol standard, PTP, of a network measurement and control system.
5. The time synchronization method of claim 1, wherein after controlling the time synchronization chip to time synchronize the system clock, further comprising:
and when the time synchronization chip is in an abnormal state, controlling the processor to continue to perform time synchronization on the system clock according to the time synchronization protocol.
6. A time synchronization apparatus, comprising:
the first synchronization module is used for carrying out time synchronization on the system clock according to a time synchronization protocol;
the synchronous detection module is used for detecting whether the time synchronization of the system clock reaches a stable state;
the second synchronization module is used for switching the time synchronization chip to continue to perform time synchronization on the system clock after the time synchronization of the system clock is determined to reach a stable state; the switching to continue the time synchronization of the system clock by the time synchronization chip comprises: controlling the system clock to output time to the time synchronization chip; and after the time synchronization chip locks the time of the system clock, controlling the time synchronization chip to perform time synchronization on the system clock, and stopping the time synchronization of the processor on the system clock.
7. A network device is characterized by comprising a processor, a memory, a time synchronization chip, a communication unit and a communication bus;
the communication bus is used for realizing the connection and communication among the processor, the memory, the time synchronization chip and the communication unit respectively;
the processor is configured to execute one or more programs stored in the memory to implement the steps of the time synchronization method of any one of claims 1 to 5.
8. The network device of claim 7, wherein the time synchronization chip is a 1588 function chip.
9. A computer-readable storage medium, characterized in that the computer-readable storage medium stores one or more programs which are executable by one or more processors to implement the steps of the time synchronization method according to any one of claims 1 to 5.
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| PCT/CN2019/076340 WO2019242321A1 (en) | 2018-06-19 | 2019-02-27 | Time synchronization method, device, network device and computer readable storage medium |
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| CN113839730B (en) * | 2020-06-24 | 2025-02-18 | 中兴通讯股份有限公司 | Time synchronization method, network device and storage medium |
| CN112040472B (en) * | 2020-08-10 | 2022-10-18 | 烽火通信科技股份有限公司 | Clock synchronization method, system and readable storage medium |
| CN113098650B (en) * | 2021-03-29 | 2023-07-25 | 大连市共进科技有限公司 | Time deviation measurement method, device, communication device and readable storage medium |
| CN115085850B (en) * | 2022-06-27 | 2024-11-05 | 中国电信股份有限公司 | Clock synchronization method, device, electronic device and storage medium |
| CN116321402A (en) * | 2023-03-16 | 2023-06-23 | 湖南大学重庆研究院 | 4G/5G-oriented lightweight PTP time synchronization system and method |
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| CN202353572U (en) * | 2011-11-25 | 2012-07-25 | 中国西电电气股份有限公司 | Institute of Electrical and Electronic Engineers (IEEE) 1588 time synchronization system for electronic type mutual inductor merging units |
| KR101682978B1 (en) * | 2016-07-26 | 2016-12-07 | 쿨사인 주식회사 | Video playback synchronization system and method using Precision Time Protocol |
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| US7447931B1 (en) * | 2005-12-09 | 2008-11-04 | Rockwell Automation Technologies, Inc. | Step time change compensation in an industrial automation network |
| CN101867469A (en) * | 2010-06-10 | 2010-10-20 | 北京东土科技股份有限公司 | A Realization Method of Precise Synchronous Clock |
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