[go: up one dir, main page]

CN110634943B - Lateral structure GaN-based JFET device regrown by MBE and its preparation method - Google Patents

Lateral structure GaN-based JFET device regrown by MBE and its preparation method Download PDF

Info

Publication number
CN110634943B
CN110634943B CN201910976128.4A CN201910976128A CN110634943B CN 110634943 B CN110634943 B CN 110634943B CN 201910976128 A CN201910976128 A CN 201910976128A CN 110634943 B CN110634943 B CN 110634943B
Authority
CN
China
Prior art keywords
gan
channel
mesa
lateral
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201910976128.4A
Other languages
Chinese (zh)
Other versions
CN110634943A (en
Inventor
郭慧
陈敦军
陶涛
王科
刘斌
张�荣
郑有炓
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nanjing University
Original Assignee
Nanjing University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nanjing University filed Critical Nanjing University
Priority to CN201910976128.4A priority Critical patent/CN110634943B/en
Publication of CN110634943A publication Critical patent/CN110634943A/en
Application granted granted Critical
Publication of CN110634943B publication Critical patent/CN110634943B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/051—Manufacture or treatment of FETs having PN junction gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H10D30/83—FETs having PN junction gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/328—Channel regions of field-effect devices of FETs having PN junction gates

Landscapes

  • Junction Field-Effect Transistors (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)

Abstract

本发明公开了一种利用MBE再生长的横向结构GaN基JFET器件及其制备方法。该方法首先利用金属有机物汽相化学沉积装置在硅衬底上外延好半绝缘的3‑5μm的GaN层，再外延300nm左右的n‑GaN沟道层，然后在外延好的器件结构上刻蚀出陡峭的n沟道台面，接着利用MBE在台面两侧通过掩模选区外延p‑GaN，与中间n沟道台面形成横向突变的p‑n结，从而构成一种具有横向沟道的结构简单的GaN‑JFET。

Figure 201910976128

The invention discloses a lateral structure GaN-based JFET device regrown by MBE and a preparation method thereof. In this method, a metal-organic vapor chemical deposition device is used to epitaxy a semi-insulating 3-5 μm GaN layer on a silicon substrate, and then an n-GaN channel layer of about 300 nm is epitaxial, and then the epitaxial device structure is etched Create a steep n-channel mesa, and then use MBE to epitaxially select p-GaN on both sides of the mesa through a mask to form a laterally abrupt p-n junction with the middle n-channel mesa, thus forming a simple structure with a lateral channel GaN‑JFETs.

Figure 201910976128

Description

Lateral structure GaN-based JFET device regrown by MBE and preparation method thereof
Technical Field
The invention relates to a Junction Field Effect Transistor (JFET), in particular to a lateral structure GaN-based JFET device regrown by MBE.
Background
The nitride semiconductor material has the characteristics of wide forbidden bandwidth, high electronic saturation rate, high critical breakdown electric field and the like, so that the transistor with lower on resistance, higher voltage resistance, higher frequency and higher working temperature can be prepared. The Junction Field Effect Transistor (JFET) device has the characteristics of high input impedance, low noise, low power consumption, strong irradiation resistance and the like. Therefore, the JFET based on the GaN material has more outstanding advantages and is expected to have important application in the fields of complementary transistor logic circuits, current sensing amplifiers, analog-to-digital converter drivers, photodiode trans-impedance amplifiers and the like. The JFET epitaxial wafer with the longitudinal structure needs an n-type conductive substrate, the growth process is complex, the cost is high, and the integration is inconvenient. The JFET with the transverse structure has lower epitaxial wafer cost, simple process and easy planar integration; the previously reported lateral structure GaN-based JFET device (document 1) is single pn junction controlled, in the structure of the present invention. The channel is controlled by two pn junctions, and the controllability of the channel is stronger.
Disclosure of Invention
The invention aims to provide a lateral structure GaN-based JFET device regrown by using MBE, which has a simple growth process and is easy to integrate.
The purpose of the invention is realized by the following technical scheme:
a lateral structure GaN-based JFET device regrown with MBE comprising:
a substrate layer;
a semi-insulating GaN layer grown on the substrate layer;
the transverse n-GaN channel table top is positioned on the top surface of the semi-insulating GaN layer;
the two p-GaN table tops are arranged on two sides of the transverse n-GaN channel table top and are in contact with the transverse n-GaN channel, are positioned on the top surface of the semi-insulating GaN layer, and form two GaN p-n junctions of transverse p-n-p with the transverse n-GaN channel table top;
the source electrode and the drain electrode are respectively arranged at two ends of the top surface of the transverse n-GaN channel table board;
two gate electrodes respectively covering the top surfaces of the two p-GaN mesas.
Preferably, the substrate layer is a silicon substrate.
Preferably, the height of the semi-insulating GaN layer is 3-5 μm.
Preferably, the channel width of the transverse n-GaN channel mesa is 200-600nm, and the channel thickness is 600-1200 nm.
Preferably, the height of the p-GaN mesa is 50nm higher than that of the n-GaN channel mesa, the size of the p-GaN mesa in the x direction is 15-30 μm, and the size of the p-GaN mesa in the y direction is 2-10 μm; the doping concentration of p-GaN is 1 x1018-1*1019cm-3。
Preferably, the source electrode and the drain electrode are Ti/Al/Ni/Au multilayer metal prepared by electron beam evaporation, the thickness is 30/150/50/150nm, the size of the X direction is 50-100nm smaller than the channel thickness of the transverse n-GaN channel mesa, and the size of the Y direction is 20-30 μm; the gate electrode is made of Ni/Au multilayer metal, the thickness of the gate electrode is 50/100nm, the size of each direction is slightly smaller than that of the p-GaN table board, the slightly smaller size means that the size of the y direction is 2-10 mu m, the size of the y direction is the same as that of the p-GaN so as to ensure the good control of a channel, and the size of the x direction is 13-28 mu m and is 1-2 mu m less than that of the p-GaN.
The preparation method of the lateral structure GaN-based JFET device by utilizing MBE regrowth comprises the following steps:
(1) the MOCVD method is used for depositing a semi-insulating GaN layer and an n-GaN channel layer on the surface of the substrate to grow the semi-insulating GaN: trimethyl gallium and NH3Respectively as Ga source and N source, and H as carrier gas2Or N2The growth temperature is 1000-1100 ℃, and the growth time is 3-5 h; the growth method of the n-GaN channel layer comprises the following steps: the temperature is 950-18cm-3The growth time is 15-20 min;
(2) etching the n-GaN channel layer into a steep transverse n-GaN channel mesa by an ICP (inductively coupled plasma) chlorine-based ion etching method, and over-etching by 50-80nm to ensure that the n-GaN is completely etched;
(3) the MBE method deposits a p-GaN table respectively on two sides of a transverse n-GaN channel table through selective area growth, and the specific growth conditions are as follows: the growth temperature is 700-800 ℃, Mg doping is carried out under the condition of Ga-rich growth, and the doping concentration is 2 x1019cm-3；
(4) Ti/Al/Ni/Au30/150/50/150nm alloy electrodes are manufactured at two ends of the top surface of the transverse n-GaN channel mesa by an electron beam evaporation method to serve as a source electrode and a drain electrode, and Ni/Au50/100nm gate electrodes are manufactured at the top surface of the p-GaN channel mesa.
The invention realizes the GaN-based junction field effect transistor with the transverse channel by a secondary regrowth method, and the structural device has simple process and easy integration. Compared with the traditional p-type ion implantation method, the method for regrowing the p-GaN twice can obtain a steeper p-n junction interface and reduce material damage. In the single pn junction controlled GaN-based JFET device with the transverse structure, the channel is controlled by two pn junctions, and compared with a single pn junction longitudinal channel, a double pn junction has stronger control capability on the channel and smaller leakage current.
Drawings
Fig. 1 is a schematic structural view of a silicon-based GaN epitaxial wafer obtained in step (1) of example 1.
Fig. 2 is a schematic structural view of a silicon-based GaN epitaxial wafer obtained in step (2) of example 1.
Fig. 3 is a schematic structural view of the GaN JFET device obtained in step (3) of example 1.
Fig. 4 is a schematic structural view of the GaN-on-silicon epitaxial wafer obtained in step (4) of example 1.
Fig. 5 is a schematic structural view of the GaN-on-silicon epitaxial wafer obtained in step (4) of example 1.
Detailed Description
The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
Example 1
A method for preparing a lateral structure GaN-based JFET device by utilizing MBE regrowth comprises the following steps:
(1) a Metal Organic Chemical Vapor Deposition (MOCVD) method of growing a semi-insulating GaN layer 2 by epitaxy on a silicon substrate 1 and then by epitaxy on an n-GaN channel layer 3 as shown in fig. 1: trimethyl gallium and NH3Respectively as Ga source and N source, and H as carrier gas2Or N2The growth temperature is 1000 ℃, and the growth time is 3 hours; the growth method of the n-GaN channel layer comprises the following steps: temperature 950 ℃ and silicon doping concentration of 2 x1018cm-3The growth time is 15 min;
(2) etching the n-GaN channel layer into a steep transverse n-GaN channel mesa by an ICP chlorine-based ion etching method, and over-etching by 50nm to ensure that the n-GaN is completely etched, as shown in FIG. 2;
(3) the MBE method deposits a p-GaN table respectively on two sides of a transverse n-GaN channel table through selective area growth, and the specific growth conditions are as follows: the growth temperature is 700 ℃, Mg doping is carried out under the condition of Ga-rich growth, and the doping concentration is 2 x1019cm-3As shown in fig. 3;
(4) Ti/Al/Ni/Au30/150/50/150nm alloy electrodes are manufactured at two ends of the top surface of the transverse n-GaN channel mesa by an electron beam evaporation method to serve as a source electrode and a drain electrode, and a Ni/Au50/100nm gate electrode is manufactured at the top surface of the p-GaN channel mesa, as shown in FIG. 4.
Example 2
A method for preparing a lateral structure GaN-based JFET device by utilizing MBE regrowth comprises the following steps:
(1) a Metal Organic Chemical Vapor Deposition (MOCVD) method of growing semi-insulating GaN by epitaxially growing a semi-insulating 3-5 μm GaN layer 2 on a silicon substrate 1 and then an n-GaN channel layer 3 of about 300nm as shown in fig. 1: trimethyl gallium and NH3Respectively as Ga source and N source, and H as carrier gas2Or N2The growth temperature is 1100 ℃, and the growth time is 5 hours; the growth method of the n-GaN channel layer comprises the following steps: at 1050 deg.C, the silicon doping concentration is 2 x1018cm-3The growth time is 20 min;
(2) etching the n-GaN channel layer into a steep transverse n-GaN channel mesa by an ICP (inductively coupled plasma) chlorine-based ion etching method, and over-etching for 80nm to ensure that the n-GaN is completely etched, as shown in FIG. 2;
(3) the MBE method deposits a p-GaN table respectively on two sides of a transverse n-GaN channel table through selective area growth, and the specific growth conditions are as follows: the growth temperature is 800 ℃, Mg doping is carried out under the condition of Ga-rich growth, and the doping concentration is 2 x1019cm-3As shown in fig. 3;
(4) Ti/Al/Ni/Au30/150/50/150nm alloy electrodes are manufactured at two ends of the top surface of the transverse n-GaN channel mesa by an electron beam evaporation method to serve as a source electrode and a drain electrode, and a Ni/Au50/100nm gate electrode is manufactured at the top surface of the p-GaN channel mesa, as shown in FIG. 4.
Example 3
A method for preparing a lateral structure GaN-based JFET device by utilizing MBE regrowth comprises the following steps:
(1) a Metal Organic Chemical Vapor Deposition (MOCVD) method of growing semi-insulating GaN on a silicon substrate 1 by epitaxial growth of a semi-insulating GaN layer 2 of 3-5 μm and then an n-GaN channel layer 3 of about 300nm as shown in fig. 1: trimethyl gallium and NH3Respectively as Ga source and N source, and H as carrier gas2Or N2The growth temperature is 1050 ℃, and the growth time is 4 hours; the growth method of the n-GaN channel layer comprises the following steps: the temperature is 1000 ℃, and the doping concentration of silicon is 2 x1018cm-3The growth time is 18 min;
(2) etching the n-GaN channel layer into a steep transverse n-GaN channel mesa by an ICP chlorine-based ion etching method, and over-etching for 60nm to ensure that the n-GaN is completely etched, as shown in FIG. 2;
(3) the MBE method deposits a p-GaN table respectively on two sides of a transverse n-GaN channel table through selective area growth, and the specific growth conditions are as follows: the growth temperature is 750 ℃, Mg doping is carried out under the condition of Ga-rich growth, and the doping concentration is 2 x1019cm-3As shown in fig. 3;
(4) Ti/Al/Ni/Au30/150/50/150nm alloy electrodes are manufactured at two ends of the top surface of the transverse n-GaN channel mesa by an electron beam evaporation method to serve as a source electrode and a drain electrode, and a Ni/Au50/100nm gate electrode is manufactured at the top surface of the p-GaN channel mesa, as shown in FIG. 4.
Example 4
As shown in fig. 5, the lateral structure GaN-based JFET device using MBE regrowth includes:
a silicon substrate layer 1;
a semi-insulating GaN layer 2 grown on the substrate layer and having a height of 3 μm;
the transverse n-GaN channel table top 3 is positioned on the top surface of the semi-insulating GaN layer, the height of the transverse n-GaN channel table top is 200nm, the channel width of the n-GaN channel table top is 200nm, and the channel thickness is 600 nm;
the two p-GaN table tops 4 which are arranged on two sides of the transverse n-GaN channel table top and are in contact with the transverse n-GaN channel are 50nm higher than the transverse n-GaN channel table top, are positioned on the top surface of the semi-insulating GaN layer and form two transverse p-n-p GaN p-n junctions with the transverse n-GaN channel table top, and the size of the p-GaN table top in the x direction is 15 mu m, and the size of the p-GaN table top in the y direction is 2 mu m; the doping concentration of p-GaN is 1 x1018cm-3；
The source electrode 5 and the drain electrode 6 are respectively arranged at two ends of the top surface of the transverse n-GaN channel table board; the source electrode and the drain electrode are made of Ti/Al/Ni/Au multilayer metal by electron beam evaporation, the thickness is 30/150/50/150nm, the size of the x direction is 50nm less than the channel thickness of the transverse n-GaN channel mesa, and the size of the y direction is 20 μm;
and the two gate electrodes 7 respectively cover the top surfaces of the two p-GaN mesas, are made of Ni/Au multilayer metal and have the thickness of 50/100nm, the size of each direction is slightly smaller than that of the p-GaN mesas, the size of the y direction is the same as that of the p-GaN, so that the good control of a channel is ensured, and the size of the x direction is about 13 mu m.
Example 5
This utilize lateral structure GaN base JFET device of MBE regrowth includes:
a sapphire substrate layer 1;
a semi-insulating GaN layer 2 grown on the substrate layer and having a height of 5 μm;
the transverse n-GaN channel table top 3 is positioned on the top surface of the semi-insulating GaN layer, the height of the transverse n-GaN channel table top is 600nm, the channel width of the n-GaN channel table top is 600nm, and the channel thickness is 1200 nm;
the two p-GaN table tops 4 which are arranged on two sides of the transverse n-GaN channel table top and are in contact with the transverse n-GaN channel are 50nm higher than the transverse n-GaN channel table top, are positioned on the top surface of the semi-insulating GaN layer and form two transverse p-n-p GaN p-n junctions with the transverse n-GaN channel table top, and the size of the p-GaN table top in the x direction is 30 mu m and the size of the p-GaN table top in the y direction is 10 mu m; the doping concentration of p-GaN is 1 x1019cm-3；
The source electrode 5 and the drain electrode 6 are respectively arranged at two ends of the top surface of the transverse n-GaN channel table board; the source electrode and the drain electrode are made of Ti/Al/Ni/Au multilayer metal by electron beam evaporation, the thickness is 30/150/50/150nm, the size of the x direction is 100nm smaller than the channel thickness of the transverse n-GaN channel mesa, and the size of the y direction is 30 μm;
two gate electrodes 7 respectively cover the top surfaces of the two p-GaN mesas, the gate electrodes are made of Ni/Au multilayer metal and have the thickness of 50/100nm, the size of each direction is slightly smaller than that of the p-GaN mesas, the size of the y direction is the same as that of the p-GaN mesa, so that the good control of a channel is ensured, and the size of the x direction is about 28 micrometers.
Example 6
This utilize lateral structure GaN base JFET device of MBE regrowth includes:
a SiC substrate layer 1;
a semi-insulating GaN layer 2 grown on the substrate layer and having a height of 4 μm;
the transverse n-GaN channel table top 3 is positioned on the top surface of the semi-insulating GaN layer, the height of the transverse n-GaN channel table top is 400nm, the channel width of the n-GaN channel table top is 400nm, and the channel thickness is 800 nm;
the two p-GaN table tops 4 which are arranged on two sides of the transverse n-GaN channel table top and are in contact with the transverse n-GaN channel are 50nm higher than the transverse n-GaN channel table top, are positioned on the top surface of the semi-insulating GaN layer and form two transverse p-n-p GaN p-n junctions with the transverse n-GaN channel table top, and the size of the p-GaN table top in the x direction is 25 mu m, and the size of the p-GaN table top in the y direction is 6 mu m; the doping concentration of p-GaN is 1.5x1019 cm-3；
The source electrode 5 and the drain electrode 6 are respectively arranged at two ends of the top surface of the transverse n-GaN channel table board; the source electrode and the drain electrode are made of Ti/Al/Ni/Au multilayer metal by electron beam evaporation, the thickness is 30/150/50/150nm, the size of the x direction is 80nm less than the thickness of the transverse n-GaN channel mesa, and the size of the y direction is 25 μm;
two gate electrodes 7 respectively cover the top surfaces of the two p-GaN mesas, the gate electrodes are made of Ni/Au multilayer metal and have the thickness of 50/100nm, the size of each direction is slightly smaller than that of the p-GaN mesas, the size of the y direction is the same as that of the p-GaN mesa, so that the good control of a channel is ensured, and the size of the x direction is about 24 micrometers.
The above embodiments are preferred embodiments of the present invention, but the present invention is not limited to the above embodiments, and any other changes, modifications, substitutions, combinations, and simplifications which do not depart from the spirit and principle of the present invention should be construed as equivalents thereof, and all such changes, modifications, substitutions, combinations, and simplifications are intended to be included in the scope of the present invention.
Reference documents:
1：Anderson TJ,Luna LE,Koehler AD,Tadjer MJ,Hobart KD,Kub FJ,Aktas O,Odnoblyudov V,Basceri C,and Ieee,Lateral GaN JFET Devices on 200mm Engineered Substrates for Power Switching Applications.(2018),pp.14-17.

Claims (7)

1.一种利用MBE再生长的横向结构GaN基JFET器件，包括：1. A lateral structure GaN-based JFET device regrown by MBE, comprising: 一衬底层；a substrate layer; 一生长于衬底层上的半绝缘GaN层；a semi-insulating GaN layer grown on the substrate layer; 一横向n-GaN沟道台面，位于半绝缘GaN层顶表面；a lateral n-GaN channel mesa on the top surface of the semi-insulating GaN layer; 两个设置于横向n-GaN沟道台面两侧且与横向n-GaN沟道接触的p-GaN台面，位于半绝缘GaN层顶表面，与横向n-GaN沟道台面形成横向p-n-p的两个GaN p-n结；Two p-GaN mesas disposed on both sides of the lateral n-GaN channel mesa and in contact with the lateral n-GaN channel, located on the top surface of the semi-insulating GaN layer, and the lateral n-GaN channel mesa form two lateral p-n-p GaN p-n junction; 源电极和漏电极，分别设置于横向n-GaN沟道台面顶表面两端；The source electrode and the drain electrode are respectively arranged at both ends of the top surface of the lateral n-GaN channel mesa; 两个栅电极，分别覆盖两个p-GaN台面顶表面。Two gate electrodes, covering the top surfaces of the two p-GaN mesa, respectively. 2.根据权利要求1所述的利用MBE再生长的横向结构GaN基JFET器件，其特征在于：所述衬底层为硅衬底、蓝宝石衬底或SiC衬底。2 . The lateral structure GaN-based JFET device regrown by MBE according to claim 1 , wherein the substrate layer is a silicon substrate, a sapphire substrate or a SiC substrate. 3 . 3.根据权利要求1所述的利用MBE再生长的横向结构GaN基JFET器件，其特征在于：所述半绝缘GaN层高度为3-5 μm。3 . The lateral structure GaN-based JFET device regrown by MBE according to claim 1 , wherein the height of the semi-insulating GaN layer is 3-5 μm. 4 . 4.根据权利要求1、2或3所述的利用MBE再生长的横向结构GaN基JFET器件，其特征在于：所述横向n-GaN沟道台面的沟道宽度为200-600 nm，沟道厚度为600-1200 nm。4. The lateral structure GaN-based JFET device regrown by MBE according to claim 1, 2 or 3, characterized in that: the channel width of the lateral n-GaN channel mesa is 200-600 nm, and the channel width is 200-600 nm. Thickness is 600-1200 nm. 5.根据权利要求4所述的利用MBE再生长的横向结构GaN基JFET器件，其特征在于：所述p-GaN台面高度比n-GaN沟道台面高50 nm，p-GaN台面在x方向的尺寸为15-30 μm，在y方向的尺寸为2-10 μm；p-GaN的掺杂浓度为1*1018-1*1019 cm-3。5 . The lateral structure GaN-based JFET device regrown by MBE according to claim 4 , wherein the p-GaN mesa height is 50 nm higher than that of the n-GaN channel mesa, and the p-GaN mesa is in the x direction. 6 . The size of the p-GaN is 15-30 μm, and the size in the y direction is 2-10 μm; the doping concentration of p-GaN is 1*10 18 -1*10 19 cm -3 . 6.根据权利要求5所述的利用MBE再生长的横向结构GaN基JFET器件，其特征在于：源电极和漏电极为用电子束蒸发制备的Ti/Al/Ni/Au多层金属，厚度为30nm/150nm/50nm/150nm，其x方向的尺寸比横向n-GaN沟道台面的沟道厚度小50-100 nm，y方向的尺寸为20-30 μm；栅电极为Ni/Au多层金属，厚度为50nm/100 nm，各方向的尺寸略小于p-GaN台面。6. The lateral structure GaN-based JFET device regrown by MBE according to claim 5, wherein the source electrode and the drain electrode are Ti/Al/Ni/Au multilayer metals prepared by electron beam evaporation, and the thickness is 30nm /150nm/50nm/150nm, the dimension in the x-direction is 50-100 nm smaller than the channel thickness of the lateral n-GaN channel mesa, and the dimension in the y-direction is 20-30 μm; the gate electrode is Ni/Au multilayer metal, The thickness is 50 nm/100 nm, and the dimensions in each direction are slightly smaller than the p-GaN mesa. 7.权利要求1-6中任一项所述的利用MBE再生长的横向结构GaN基JFET器件的制备方法，其步骤包括：7. The method for preparing a lateral structure GaN-based JFET device regrown by MBE according to any one of claims 1-6, the steps comprising: （1）MOCVD法在衬底表面沉积半绝缘GaN层和n-GaN沟道层， 生长半绝缘GaN的方法：三甲基镓和NH3分别作为Ga源和N源，载气为H2或者N2，生长温度为1000-1100 ℃，生长时间3-5h；n-GaN沟道层的生长方法：温度950-1050 ℃，硅掺杂浓度为2*1018 cm-3，生长时间15-20min；(1) The MOCVD method is used to deposit a semi-insulating GaN layer and an n-GaN channel layer on the surface of the substrate, and the method of growing semi-insulating GaN: trimethyl gallium and NH 3 are used as Ga source and N source respectively, and the carrier gas is H 2 or N 2 , the growth temperature is 1000-1100 ℃, the growth time is 3-5h; the growth method of the n-GaN channel layer: the temperature is 950-1050 ℃, the silicon doping concentration is 2*10 18 cm -3 , and the growth time is 15- 20min; （2）用ICP氯基离子刻蚀的方法将n-GaN沟道层刻蚀成陡峭的横向n-GaN沟道台面，过刻50-80 nm以保证n-GaN被全部刻完；(2) The n-GaN channel layer is etched into a steep lateral n-GaN channel mesa by the ICP chloride-based ion etching method, and over-etching 50-80 nm to ensure that the n-GaN is completely etched; （3）MBE法通过选区生长在横向n-GaN沟道台面两侧各沉积一个p-GaN台面，具体生长条件为：生长温度为700-800 ℃，在富Ga生长的条件下进行Mg掺杂，掺杂浓度2*1019 cm-3；(3) The MBE method deposits a p-GaN mesa on each side of the lateral n-GaN channel mesa by selective growth. The specific growth conditions are: the growth temperature is 700-800 °C, and Mg doping is performed under the condition of Ga-rich growth. , doping concentration 2*10 19 cm -3 ; （4）用电子束蒸镀的方法在横向n-GaN沟道台面顶表面两端制作Ti/Al/Ni/Au 30nm/150nm/50nm/150 nm合金电极为源电极和漏电极，在p-GaN台面顶表面制作Ni/Au 50nm/100nm栅电极。(4) Ti/Al/Ni/Au 30nm/150nm/50nm/150nm alloy electrodes were fabricated on both ends of the top surface of the lateral n-GaN channel mesa by electron beam evaporation as source and drain electrodes. A Ni/Au 50nm/100nm gate electrode was fabricated on the top surface of the GaN mesa.
CN201910976128.4A 2019-10-15 2019-10-15 Lateral structure GaN-based JFET device regrown by MBE and its preparation method Active CN110634943B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910976128.4A CN110634943B (en) 2019-10-15 2019-10-15 Lateral structure GaN-based JFET device regrown by MBE and its preparation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910976128.4A CN110634943B (en) 2019-10-15 2019-10-15 Lateral structure GaN-based JFET device regrown by MBE and its preparation method

Publications (2)

Publication Number Publication Date
CN110634943A CN110634943A (en) 2019-12-31
CN110634943B true CN110634943B (en) 2021-01-01

Family

ID=68975207

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910976128.4A Active CN110634943B (en) 2019-10-15 2019-10-15 Lateral structure GaN-based JFET device regrown by MBE and its preparation method

Country Status (1)

Country Link
CN (1) CN110634943B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115516645B (en) * 2020-05-13 2025-06-10 三菱电机株式会社 Semiconductor devices

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9214538B2 (en) * 2011-05-16 2015-12-15 Eta Semiconductor Inc. High performance multigate transistor
US9660080B2 (en) * 2014-02-28 2017-05-23 Stmicroelectronics, Inc. Multi-layer strained channel FinFET
US9252208B1 (en) * 2014-07-31 2016-02-02 Stmicroelectronics, Inc. Uniaxially-strained FD-SOI finFET
JP6304155B2 (en) * 2015-07-14 2018-04-04 株式会社デンソー Nitride semiconductor device
JP6614116B2 (en) * 2016-05-24 2019-12-04 株式会社デンソー Semiconductor device

Also Published As

Publication number Publication date
CN110634943A (en) 2019-12-31

Similar Documents

Publication Publication Date Title
CN110112215B (en) Power device with both gate dielectric and etch stop functional structure and preparation method
US9166033B2 (en) Methods of passivating surfaces of wide bandgap semiconductor devices
US8551821B2 (en) Enhancement normally off nitride semiconductor device manufacturing the same
JP7013710B2 (en) Manufacturing method of nitride semiconductor transistor
CN109873034B (en) Normally-off HEMT power device for depositing polycrystalline AlN and preparation method thereof
US20230207661A1 (en) Semiconductor Device and Method of Manufacturing the Same
CN111211176B (en) A GaN-based heterojunction integrated device structure and manufacturing method
CN112054056B (en) High electron mobility transistor with grid electrostatic protection structure and manufacturing method
CN113745333A (en) Normally-off gallium oxide based MIS-HEMT device containing delta doped barrier layer and preparation method thereof
CN107958939A (en) One kind nitridation Gallium base heterojunction Schottky diode structures
CN109950324A (en) Group III nitride diode device with p-type anode and method of making the same
CN110690273B (en) Lateral GaN-based enhancement mode junction field effect transistor device and preparation method thereof
CN106971943B (en) Method for manufacturing vertical devices with gallium nitride epitaxial layers grown on silicon substrates
JP2008263212A (en) Semiconductor device, manufacturing method thereof, and semiconductor device application system
CN110767752A (en) Bottom trench gate GaN-MOSFET device with novel structure and preparation method thereof
CN110634943B (en) Lateral structure GaN-based JFET device regrown by MBE and its preparation method
CN111180527A (en) A kind of GaN-based PN diode and preparation method thereof
JP4474292B2 (en) Semiconductor device
CN106449406B (en) A vertical structure GaN-based enhancement mode field effect transistor and its manufacturing method
CN110634747A (en) Method for regrowing p-GaN GaN-JFET device with single gate structure by using MBE
CN110518067B (en) Heterojunction Field Effect Transistor Based on Trench Array and Its Fabrication Method and Application
CN110931547A (en) A kind of HEMT device and preparation method thereof
CN113725297B (en) A normally-on gallium oxide-based HFET device with a cap layer and a method for preparing the same
CN212542443U (en) Gallium nitride transistor structure and gallium nitride-based epitaxial structure
JP2008227039A (en) Semiconductor device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant