CN110676213B - 一种针对小线宽要求的硅通孔互连铜线阻挡层优化方法 - Google Patents
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Abstract
本发明公开一种针对小线宽要求的硅通孔互连铜线阻挡层优化方法，包括步骤：采用Ta和TaN双层作为通孔阻挡层，制备不同厚度的Ta‑TaN阻挡层，测量不同厚度下互连体系电阻电阻电迁移性能，选择具备预期电迁移能力和低互连电阻的适宜厚度的Ta‑TaN阻挡层薄膜作为目标阻挡层。本发明采用Ta和TaN双层作为通孔阻挡层，通过制备不同厚度的Ta‑TaN阻挡层，测量不同厚度下的互连体系电阻电迁移性能，最终获得具备预期电迁移能力和低互连电阻的适宜厚度的Ta‑TaN阻挡层薄膜。
Description
技术领域
本发明涉及集成电路制造工艺技术领域，特别是涉及一种针对小线宽要求的硅通孔互连铜线阻挡层优化方法。
背景技术
随着超大规模混合集成电路的发展，门延迟的下降速度越来越快，电阻和电容都在增大，且间距更窄，限制了集成度的增加。解决的办法是采用基于硅通孔的Cu互连技术，硅通孔用于将一个金属层连接到另一个金属层，为信号从不同的设备流过芯片提供关键路径。由于通孔电阻与RC延迟直接相关，所以通孔电阻对器件性能至关重要。
通孔是通过深反应离子刻蚀(DIRE)或感应耦合等离子体(ICP)刻蚀获得的，为了防止器件之间短路，首先在其上做一层绝缘层SiO2，Cu在Si和含Si的介质层中有较强的扩散性，这样Cu在其中会产生陷阱，使器件性能退化，所以，需要在绝缘层上制备一层阻挡层。降低通孔电阻最直接的方法是增加底部通孔的特征尺寸，但是特征尺寸的增加会降低时间相关介质击穿(TDDB)的性能，并且影响产品的良率；而通过引入新的阻挡层材料如钴(Co)和钌(Ru)会改变当前的集成工艺并且可能对下游工艺产生影响；通过蚀刻处理将通孔延伸到下面的沟槽中可以增加接触面积，从而降低电阻，但在刻蚀过程中可能会引起切角问题和侧壁损伤。在不引起新的集成方案的情况下，减小通孔底部的阻挡层厚度是目前最可行的方案。
目前，阻挡层材料主要为高熔点金属(Cr、Ti、Nb、Mo、Ta和W)，高熔点金属的氮化物、碳化物、硅化物(TaN、TaSi、TaC、TiN)，高熔点金属三元化合物(Ti-Si-N、Zr-Si-N、W-Si-N、Ta-B-N、Zr-Al-N、Ti-Al-N)。国内外多种实验已经奠定了Ta及其氮化物TaN作为铜扩散阻挡层的关键地位。Ta及其化合物有良好的界面黏着性、低电阻率、较好的热稳定性和较高的电导率，Ta材料逐渐成为防止铜扩散的阻挡层材料，并受到越来越多的人的关注。
阻挡层沉积工艺是是平衡特征覆盖率和电参数的同时达到预期电迁移(EM)性能的关键组成部分。阻挡层厚度、沉积过程中的直流/交流偏压等对决定沉积的势垒膜的质量和数量起着重要作用。平衡这些参数能够调节薄膜以获得良好的可靠性的同时，降低通孔的电阻。
发明内容
本发明的目的是针对现有技术中存在的技术缺陷，而提供一种针对小线宽要求的硅通孔互连铜线阻挡层优化方法。
为实现本发明的目的所采用的技术方案是：
一种针对小线宽要求的硅通孔互连铜线阻挡层优化方法，包括步骤：采用Ta和TaN双层作为通孔阻挡层，制备不同厚度的Ta-TaN阻挡层，测量不同厚度下互连体系电阻电阻电迁移性能，获得具备预期电迁移能力和低互连电阻的适宜厚度的Ta-TaN阻挡层薄膜。
本发明采用Ta和TaN双层作为通孔阻挡层，通过制备不同厚度的Ta-TaN阻挡层，测量不同厚度下的互连体系电阻电迁移性能，最终获得具备预期电迁移能力和低互连电阻的适宜厚度的Ta-TaN阻挡层薄膜。
附图说明
图1为本发明的针对小线宽要求的硅通孔互连铜线阻挡层优化方法的工艺流程图。
具体实施方式
以下结合附图和具体实施例对本发明作进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
为了获得阻挡效果更好的阻挡层，且获得尽可能小的互连体系电阻，一般采用Ta-TaN双层结构作为铜互连线的扩散阻挡层。降低电阻方法有多种，增加通孔底部特征尺寸的方法会使降低TDDB的性能，改变阻挡层材料的方法会引入新的工艺问题，加深刻蚀增加接触面积的方法会对侧壁造成损伤。
RC延迟增加的一个重要因素是越来越小的线宽上的电阻和电容制约。而被扩散阻挡层包封的铜连线其尺寸和电阻都会增加，假设互连材料电阻率为ρ，阻挡层材料电阻率为ρb，互连线长L，宽W，高H，阻挡层厚度为b，则去扩散阻挡层，互连线自身电阻为R：
R＝Lρ/(W×H)
当互连线覆以阻挡层时，互连体系电阻变为Rb:
由公式看出ρb和b的增加将导致电阻Rb的增大，因此为了降低互连体系的电阻，阻挡层的电阻率和厚度应该尽可能的低。
因此，本发明以硅通孔为例，提供一种Ta-TaN双层阻挡层Ta和TaN厚度的最优结合，即从Ta和TaN厚度入手，以适度厚的Ta层和较薄的TaN层组成阻挡层，以获得在最小互连体系电阻下的最好抑制铜扩散的阻挡层。
其中，制备不同厚度的Ta-TaN双层阻挡层的技术方案如下：
(1)用乙醇、丙酮将表面有SiO2绝缘层4的Si基体1进行超声清洗并烘干，之后在真空室进行15分钟的溅射清洗；
(2)先对SiO2绝缘层刻蚀，然后再利用感应耦合等离子体(ICP)刻蚀Si基体得到5个相同深度和宽度的通孔，通孔深度为200nm，宽度为30nm(如图1中第二个图)，氧化通孔侧壁和底部产生绝缘层(如图1中第三个图)；
(3)采用纯度为99.95％金属Ta靶的靶材，在通孔上用反应磁控溅射法沉积Ta膜2，其中氩气(Ar2)的流量36mL/min，溅射时工作气压为0.3Pa，溅射功率100W，1号到5号通孔分别表面溅射10nm、30nm、50nm、70nm、90nm；
(4)保持Ar2流量不变，向通孔通过N2，N2的流量4mL/min，通过控制时间来获取不同厚度的TaN薄膜3，1号到5号通孔分别溅射90nm、70nm、50nm、30nm、10nmTaN薄膜；
(5)对利用同步刻蚀填充方法淀积Cu膜5，填充通孔，单次淀积Cu后，直接在腔体内进行同步刻蚀，直至将通孔填满Cu，Cu膜厚度约为100nm；
(6)采用真空退火进行样品的老化扩散特性研究，在450℃退火30min，真空度保持在1×10-3Pa；
(7)分别测量1号到5号通孔的电阻率，比较各个通孔的预期电迁移(EM)性能。
本发明实现铜扩散阻挡层的优化，很好地降低阻挡层的电阻，提高产品性能的同时获得更好地可靠性，提高产品良率。
本发明在不增加新的工艺过程的情况下，考虑通孔自身的电阻和电迁移的特性，设计降低TaN厚度和适度厚的Ta层作为铜扩散的阻挡层，使其获得更好地性能，节约成本。
以上所述仅是本发明的优选实施方式，应当指出的是，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。
Claims (2)
1.针对小线宽要求的硅通孔互连铜线阻挡层优化方法，其特征在于，包括步骤：采用Ta和TaN双层作为通孔阻挡层，制备不同厚度的Ta-TaN阻挡层，测量不同厚度下的互连体系电阻电迁移性能，获得具备预期电迁移能力和低互连电阻的适宜厚度的Ta-TaN阻挡层薄膜。
2.根据权利要求1所述针对小线宽要求的硅通孔互连铜线阻挡层优化方法，其特征在于，所述Ta-TaN阻挡层的制备步骤如下：
用乙醇、丙酮将Si基体进行超声清洗并烘干，之后在真空室进行15分钟的溅射清洗；
利用感应耦合等离子体刻蚀得到5个相同深度和宽度的通孔，通孔深度为200nm，宽度为30nm，氧化通孔侧壁和底部产生绝缘层；
采用纯度为99.95％金属Ta靶的靶材，在通孔上用反应磁控溅射法沉积Ta，其中氩气Ar2的流量36mL/min，溅射时工作气压为0.3Pa，溅射功率100W，1号到5号通孔分别表面溅射10nm、30nm、50nm、70nm、90nm；
保持Ar2流量不变，向通孔通过N2，N2的流量4mL/min，通过控制时间来获取不同厚度的TaN薄膜，1号到5号通孔分别溅射90nm、70nm、50nm、30nm、10nmTaN薄膜；
对利用同步刻蚀填充方法淀积Cu膜，单次淀积Cu后，直接在腔体内进行同步刻蚀，直至将通孔填满Cu，Cu膜厚度约为100nm；
采用真空退火进行样品的老化扩散特性研究，在450℃退火30min，真空度保持在1×10-3Pa；
分别测量1号到5号通孔的电阻率，比较各个通孔的预期电迁移性能。
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