CN110690284A - A kind of gallium nitride based field effect transistor and preparation method thereof - Google Patents

Abstract

The embodiment of the invention discloses a gallium nitride-based field effect transistor and a preparation method thereof, wherein the gallium nitride-based field effect transistor structure comprises: the device comprises a substrate, a buffer layer, a back barrier layer, a channel layer, a barrier layer, a p-type gate layer and a passivation layer; and a source and a drain in contact with the barrier layer, wherein the gate is located in the first region, the source and the drain are located in the second region, and the p-type dopant in the film layer of the p-type gate layer in the second region is not activated. The technical method increases the width of a process window of gate etching, is not limited by the precision of the etching process, and ensures high controllability and good repeatability of the gate etching.

Description

A kind of gallium nitride based field effect transistor and preparation method thereof

technical field

Embodiments of the present invention relate to the technical field of semiconductor devices, and in particular, to a gallium nitride-based field effect transistor and a method for fabricating the same.

Background technique

Conventional gallium nitride (GaN)-based heterojunction transistors are generally depletion-type normally-on structures (D-Mode), and in circuit design, people prefer to use enhancement-type normally-off devices (E-Mode), Because the circuit of this type of device is used, the safety of power failure is high, and the protection circuit is simple. There are many conventional ways to realize enhancement mode GaN-based heterojunction transistors, such as trench gate structure, fluoride ion implantation at the bottom of the gate, metal insulating layer semiconductor gate structure combined with trench gate, p-type gate structure, stacked structure, etc. Among them, the p-type gate structure is a relatively common E-Mode structure, which has a simple structure and is easy to process. The conventional process method for realizing p-type gate is to use photolithography, dielectric deposition, etching and plasma dry etching technology (Inductively Coupled Plasma, ICP) to make a mask at the gate prefabricated position, and then etch the gate electrode. The p-type material in the area other than the prefabricated position is removed, thereby realizing the E-Mode device of the p-type gate structure.

FIG. 1 is a schematic structural diagram of a GaN-based field effect transistor provided in the prior art. Referring to FIG. 1, it includes a substrate 10, a buffer layer 20, a back barrier layer 30, a channel layer 40, and a barrier layer 50. The p-type gate layer 60 , the passivation layer 70 , the gate electrode 80 , the source electrode 90 and the drain electrode 100 . It should be pointed out that after the growth of the conventional epitaxial structure, the conventional epitaxial wafer will be annealed at high temperature under nitrogen to activate the p-type dopant in the p-type gate layer. This etching process is used to fabricate the E of the p-type gate structure. Although -Mode field effect transistors are easy to implement, there are also some difficult problems to solve. In the etching of the p gate, a very high selectivity ratio of the p-type gate layer to the barrier layer etching needs to be adjusted, so that the etching can stop on the surface of the barrier layer 50 after the p-type gate layer is completely removed. The over-etching of the barrier layer 50 will damage the barrier layer, and will also affect the two-dimensional electron gas concentration in the channel layer, reducing the device characteristics; if the etching stops before the barrier layer 50 is reached, it will make the barrier The remaining part of the p-type gate layer material on the top of the layer 50 causes the part of the two-dimensional electron gas in the channel layer to be depleted, reducing the current output capability of the device. The residue of the p-type gate layer material can also cause leakage between the gate and the drain; although the etching conditions can be continuously improved, when the etching reaches the surface of the barrier layer, it will cause damage to this layer of material, making the device The static and dynamic working characteristics deteriorate.

SUMMARY OF THE INVENTION

The embodiments of the present invention provide a gallium nitride-based field effect transistor and a method for fabricating the same, which can reduce the tolerance of the process and ensure the working characteristics of the device.

In a first aspect, an embodiment of the present invention provides a GaN-based field effect transistor, including:

Substrate, buffer layer, back barrier layer, channel layer, barrier layer, p-type gate layer and passivation layer;

a gate electrode in contact with the p-type gate layer, and a source electrode and a drain electrode penetrating the p-type gate layer and the passivation layer and in contact with the barrier layer, wherein the gate electrode is located in the first In a region, the source electrode and the drain electrode are located in a second region, and the p-type dopant of the p-type gate layer in the film layer of the second region is not activated.

Optionally, the film thickness of the p-type gate layer in the first region is greater than the film thickness of the second region.

Optionally, the thickness of the film layer of the p-type gate layer in the second region ranges from 2 nm to 300 nm.

Optionally, the material of the p-type gate layer includes at least one of p-GaN and p-AlGaN.

In a second aspect, an embodiment of the present invention provides a method for fabricating a GaN-based field effect transistor, the method comprising:

An epitaxial wafer is provided, the epitaxial wafer includes a stacked substrate, a buffer layer, a back barrier layer, a channel layer, a barrier layer and a p-type gate layer; wherein the dopant in the p-type gate layer is not subjected to activation;

forming a gate mask on the surface of the p-type gate layer;

thinning the portion of the p-type gate layer not covered by the gate mask;

removing the gate mask;

forming a dielectric isolation layer on the p-type gate layer;

Etching the dielectric isolation layer to expose part of the p-type gate layer, and the exposed region of the p-type gate layer is the gate position region;

selectively activating dopants in the p-type gate layer of the gate site region;

forming a passivation layer on the p-type gate layer;

forming a gate electrode, a source electrode and a drain electrode; wherein, the gate electrode is formed in a first region, and the source electrode and the drain electrode are formed in a second region; in the first region, the p-type gate layer is The p-type dopant of the p-type gate layer is activated, and the p-type dopant of the p-type gate layer is not activated in the second region.

Optionally, the forming a gate mask on the surface of the p-type gate layer includes:

depositing a gate mask dielectric layer on the surface of the p-type gate layer;

Making a photoresist mask on the surface of the gate mask dielectric layer;

The gate mask dielectric layer is etched to form a gate mask at the gate position, and the p-type gate layer not covered by the gate mask leaks out.

Optionally, the thinning of the portion of the p-type gate layer that is not covered by the gate mask includes:

The part of the p-type gate layer not covered by the gate mask is etched, so that the thickness of the part of the p-type gate layer not covered by the gate mask is smaller than the thickness of the p-type gate layer covered by the gate mask. thickness of the portion covered by the gate mask.

Optionally, the forming the gate in the first region includes:

A gate contact window is formed in the gate position region in the first region by photolithography and etching, and the p-type gate layer leaked from the gate contact window is activated;

A gate is formed in the gate contact window, and is in contact with the p-type gate layer leaked from the contact window.

Optionally, forming the source electrode and the drain electrode in the second region includes:

An ohmic contact window is made by etching the source position and the drain position in the second region; the ohmic contact window leaks a portion of the barrier layer;

Evaporating ohmic contact metal at the source position and the drain position;

etching away metal materials other than the ohmic contact metal on the source electrode position and the drain electrode position to form the source electrode and the drain electrode;

The source electrode and the drain electrode are annealed through an annealing process to form a metal-semiconductor ohmic contact.

Optionally, the forming the source electrode and the drain electrode in the second region includes:

An ohmic contact window is made by etching the source position and the drain position in the second region; the ohmic contact window leaks a portion of the barrier layer;

forming a photoresist layer on the dielectric isolation layer;

removing the photoresist at the source position and the drain position;

Evaporating ohmic contact metal at the source position and the drain position;

removing the photoresist layer;

The source electrode and the drain electrode are annealed through an annealing process to form a metal-semiconductor ohmic contact.

Embodiments of the present invention provide a gallium nitride-based field effect transistor and a method for fabricating the same, including: a stacked substrate, a buffer layer, a back barrier layer, a channel layer, a barrier layer, a p-type gate layer, and a passivation layer layer; a gate electrode in contact with the p-type gate layer, and source and drain electrodes penetrating the p-type gate layer and the passivation layer and in contact with the barrier layer, wherein the gate electrode The source electrode and the drain electrode are located in the first region, the source electrode and the drain electrode are located in the second region, and the p-type dopant of the p-type gate layer in the film layer of the second region is not activated. The process has good repeatability and high controllability, the two-dimensional electron gas in the channel will not be depleted, the barrier layer will not be damaged, and the leakage phenomenon between the gate and the drain can be avoided.

Description of drawings

1 is a schematic structural diagram of a GaN-based field effect transistor provided in the prior art

FIG. 2 is a schematic structural diagram of a GaN-based field effect transistor according to Embodiment 1 of the present invention;

3 is a schematic structural diagram of another GaN-based field effect transistor provided in Embodiment 1 of the present invention;

4A is a flowchart of a method for manufacturing a GaN-based field effect transistor according to Embodiment 2 of the present invention;

4B-4J are structural cross-sectional views of each step in a method for fabricating a GaN-based field effect transistor according to Embodiment 2 of the present invention;

FIG. 5 is a flowchart of a method for forming a source electrode and a drain electrode in a second region according to Embodiment 2 of the present invention;

FIG. 6 is a flowchart of another method for forming a source electrode and a drain electrode in the second region according to the second embodiment of the present invention.

Detailed ways

The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention. In addition, it should be noted that, for the convenience of description, the drawings only show some but not all structures related to the present invention.

An embodiment of the present invention provides a gallium nitride-based field effect transistor. Referring to FIG. 1, FIG. 1 is a schematic structural diagram of a gallium nitride-based field effect transistor provided by the first embodiment of the present invention, including:

The stacked substrate 10, the buffer layer 20, the back barrier layer 30, the channel layer 40, the barrier layer 50, the p-type gate layer 60 and the passivation layer 70;

The gate electrode 80 in contact with the p-type gate layer 60, and the source electrode 90 and the drain electrode 100 passing through the p-type gate layer 60 and the passivation layer 70 and in contact with the barrier layer 50, wherein the gate electrode 80 is located in the first region 11. The source electrode 90 and the drain electrode 100 are located in the second region 12, and the p-type dopant of the p-type gate layer 60 in the film layer of the second region 12 is not activated.

Specifically, the epitaxial wafer in the GaN-based field effect transistor includes sequentially stacked substrate 10, buffer layer 20, back barrier layer 30, channel layer 40, barrier layer 50, and p-type gate layer from the bottom to the top of the structure 60 and passivation layer 70; wherein, the substrate layer 10 can be a Si substrate, a sapphire substrate or a GaN substrate; the buffer layer 20 can be a multi-layer alternating periodic structure of AlN/GaN to achieve stress relief; the back barrier layer 30 AlGaN barrier structure can be used, wherein the composition of Al is 5%-35%; the channel layer 40 can use the GaN of this certificate as the channel layer; the barrier layer 50 can be made of AlGaN material, wherein the composition of Al can be 5%-35%; the p-type gate layer 60 is made of p-GaN or p-AlGaN material, wherein the p-type dopant can be selected from Mg element, and the doping method can be constant composition doping, gradient doping, step doping jump doping or delta doping; the passivation layer 70 is made of silicon nitride material;

The gate electrode 80 in contact with the p-type gate layer 60 , and the source electrode 90 and the drain electrode 100 penetrating the p-type gate layer 60 and the passivation layer 70 and in contact with the barrier layer 50 , wherein the gate electrode 80 is located at the first In region 11, the source 90 and drain 100 are located in the second region 12, the p-type gate layer 60 is inactive in the p-type dopant in the film layer of the second region 12, and the p-type dopant in the film layer of the first region 11 is not activated. type dopant is activated.

In the GaN-based field effect transistor provided by the embodiment of the present invention, compared with the problem that the p-type material at the top of the channel must be removed in the traditional process, the p-type material is appropriately retained (that is, the p-type material in the second region is retained. gate layer), even if a p-type gate layer is provided in the second region, it will exhibit a high resistance state because the p-type dopant in the p-type gate layer in this region is not activated. In the prior art, the p-gate layer is first activated, and in the etching of the p-gate, it is necessary to adjust a very high selectivity ratio of the p-type gate layer to the barrier layer etching, so that after all the p-type gate layers are removed, Etching can stop at the surface of the barrier layer. Over-etching of the barrier layer will damage the barrier layer, and will also affect the two-dimensional electron gas concentration in the channel layer, reducing the device characteristics; if the etching stops before the barrier layer is reached, it will make the top of the barrier layer. The remaining part of the p-type gate layer material causes the part of the two-dimensional electron gas in the channel layer to be depleted, reducing the current output capability of the device. Residues of p-type gate layer material can also cause leakage between gate and drain. In the embodiment of the present invention, the p-type dopant in the p-type gate layer arranged in the second region is not activated, but will show a high resistance state, so that the source electrode, the drain electrode and the gate electrode are in a blocking state, which does not affect the device characteristics. , and the process of etching the p-type gate layer to form the gate position will not cause damage to the barrier layer, the process error tolerance is lower, not limited by the etching process accuracy, high controllability, good repeatability, suitable for mass production .

Optionally, the film thickness of the p-type gate layer 60 in the first region 11 is greater than that of the second region 12 .

Specifically, during the etching process of the gate 80 , the p-type gate layer 60 in the second region 12 needs to be etched away, the p-type gate layer 60 in the first region 11 is protruded, and the p-type gate layer 60 in the first region 11 is protruded. The p-type gate layer 60 is used to prepare the gate electrode 80 , so the film thickness of the p-type gate layer 60 in the first region 11 is greater than that of the second region 12 .

Optionally, the thickness of the p-type gate layer 60 in the second region 12 ranges from 2 nm to 300 nm.

Specifically, during the etching process, the thickness of the p-type gate layer 60 in the region other than the gate electrode 80 is generally about 5 nm. In fact, the remaining thickness of the p-type gate layer 60 is at least 2 nm, and the most limiting case is that the gate etching process is not used, that is, the p-type gate layer 60 is completely retained. The thickness of the p-type gate layer 60 is generally between 50-300 nm, so the remaining thickness of the p-type gate layer 60 is in the range of 2 nm-300 nm, and the remaining thickness of the second region 12 is determined according to the original thickness of the p-type gate layer 60 .

Optionally, the material of the p-type gate layer 60 includes at least one of p-GaN and p-AlGaN.

Specifically, p-GaN and p-AlGaN form polarized charges on the material surface or hetero-interface, thereby generating a high-concentration two-dimensional electron gas, and excellent channel-to-point characteristics.

Optionally, referring to FIG. 2 , FIG. 2 is a schematic structural diagram of another GaN-based field effect transistor according to Embodiment 1 of the present invention, which further includes a chip isolation region 110 .

An embodiment of the present invention provides a gallium nitride-based field effect transistor, comprising: a stacked substrate, a buffer layer, a back barrier layer, a channel layer, a potential barrier layer, a p-type gate layer and a passivation layer; A gate electrode in contact with the type gate layer, and a source electrode and a drain electrode which penetrate through the p-type gate layer and the passivation layer and are in contact with the barrier layer, wherein the gate electrode is located in the first region, and the source electrode and the drain electrode are located in the second region , the p-type dopant of the p-type gate layer in the film layer of the second region is not activated. The selective activation method is adopted, so that only the p-type dopant at the gate position is activated, and other residual p-type materials are not activated to affect the device characteristics. The process has good repeatability, high controllability, and no damage to the barrier layer. The window is wide and very suitable for mass production of devices.

An embodiment of the present invention also provides a method for fabricating a GaN-based field effect transistor. Referring to FIG. 4A, FIG. 4A is a flowchart of a method for fabricating a GaN-based field effect transistor according to Embodiment 2 of the present invention. 4B-4J, and FIGS. 4B-4J are structural cross-sectional views of each step in a method for fabricating a GaN-based field effect transistor according to Embodiment 2 of the present invention, and the method includes:

S10. Provide an epitaxial wafer, the epitaxial wafer includes a stacked substrate, a buffer layer, a back barrier layer, a channel layer, a barrier layer and a p-type gate layer; wherein, the dopant in the p-type gate layer is not activated.

Specifically, referring to FIG. 4B , a buffer layer 20 , a back barrier layer 30 , a channel layer 40 , a barrier layer 50 and an unactivated p-type gate layer 60 are sequentially formed on the substrate 10 , wherein the barrier layer 50 and An AlN layer can be added between the channel layers 40 to optimize device characteristics. Wherein, the substrate layer 10 can adopt a Si substrate, a sapphire substrate or a GaN substrate; the buffer layer 20 can adopt a multi-layer alternating periodic structure of AlN/GaN to realize stress relief; the back barrier layer 30 can adopt an AlGaN barrier structure, The composition of Al is 5%-35%; the channel layer 40 can use the GaN of this certificate as the channel layer; the barrier layer 50 can be made of AlGaN material, wherein the composition of Al can be 5%-35%; p The gate layer 60 is made of p-GaN or p-AlGaN material, wherein the p-type dopant can be selected from Mg element, and the doping method can be constant composition doping, graded doping, step doping or delta doping etc.; the passivation layer 70 is made of silicon nitride material

S20, forming a gate mask on the surface of the p-type gate layer.

Specifically, the gate mask formed on the surface of the p-type gate layer can be made of silicon oxide, silicon nitride or metal nickel, and the growth of the gate mask can be made by plasma enhanced vapor chemical deposition, electron beam evaporation or magnetron sputtering. accomplish.

Optionally, forming a gate mask on the surface of the p-type gate layer includes:

Deposit a gate mask dielectric layer on the surface of the p-type gate layer;

Make a photoresist mask on the surface of the gate mask dielectric layer;

The gate mask dielectric layer is etched to form a gate mask at the gate position, and the p-type gate layer not covered by the gate mask leaks out.

Exemplarily, referring to FIG. 4C, a gate mask dielectric layer 61 is deposited on the surface of the p-type gate layer. The gate mask dielectric layer 61 is made of silicon oxide, and the thickness is 300 nm. The deposition method is plasma enhanced. Chemical vapor deposition equipment PECVD; make a photoresist mask on the surface of the gate mask dielectric layer 61, refer to FIG. 4D, etch the gate mask dielectric layer 61 by dry etching to make a gate at the gate position Mask 62, wherein the photoresist can be commonly used S1818, Ruihong 304 or AZ5214 photoresist.

S30, thinning the part of the p-type gate layer that is not covered by the gate mask.

Specifically, referring to FIG. 4E , part of the p-type gate layer 60 in the second region 12 is removed by etching, so as to thin the part of the p-type gate layer not covered by the gate mask 62 .

Optionally, thinning the portion of the p-type gate layer 60 not covered by the gate mask 62 includes:

The part of the p-type gate layer 60 not covered by the gate mask 62 is etched, so that the thickness of the part of the p-type gate layer 60 not covered by the gate mask 62 is smaller than that of the part of the p-type gate layer 60 covered by the gate mask 62 , that is, the thickness of the p-type gate layer 60 in the second region 12 is smaller than that of the p-type gate layer 60 in the first region 11 .

Specifically, after the gate mask 62 is fabricated, the epitaxial wafer is placed in a dry etching machine, and the p-type gate layer 60 is etched. The parts not covered by the gate mask 62 are gradually etched and thinned. However, the part with the gate mask 62 is completely preserved due to the blocking of the mask, and the etching is completed to form the gate position.

S40, removing the gate mask.

Specifically, referring to FIG. 4F , after the etching is completed, the gate position is formed, and the gate mask 62 is cleaned by wet etching.

S50, forming a dielectric isolation layer on the p-type gate layer.

Specifically, referring to FIG. 4G, after the gate mask 62 is cleaned by wet etching, a dielectric isolation layer 63 is deposited on the surface of the p-type gate layer 60. The dielectric isolation layer 63 can be made of various high temperature resistant materials. Materials, such as aluminum oxide, silicon oxide, hafnium oxide, indium tin oxide (ITO) and gallium oxide materials, exemplarily, the dielectric isolation layer 63 is formed by using an Al ₂ O ₃ film grown by atomic layer epitaxy ALD equipment, with a thickness of 200 nm, Growth time is about 60 minutes. However, it should be noted that during the material growth process, try to avoid the reactant containing hydrogen element. In addition, in order to avoid the effect of nitrogen on the selective activation of the p-type dopant, the dielectric isolation layer 63 does not use nitride.

S60, the dielectric isolation layer is etched to expose part of the p-type gate layer, and the exposed region of the p-type gate layer is the gate position region.

Specifically, referring to FIG. 4H , after the growth of the dielectric isolation layer 63 is completed, a gate top window is opened by means of photolithography and dry etching to expose a part of the p-type gate layer 60 .

S70 , selectively activating the dopant in the p-type gate layer in the gate location region.

Specifically, after a part of the p-type gate layer 60 is exposed, the epitaxial wafer is placed in an annealing furnace, and annealed in the range of 700-850 degrees Celsius for 10-30 minutes under a nitrogen atmosphere, and the p-type gate layer near the top window of the gate is annealed for 10-30 minutes. 60 is annealed to achieve selective activation of the gate dopant.

S80, forming a passivation layer on the p-type gate layer.

Specifically, referring to FIG. 4I, after the selective activation of the p-type dopant at the gate position is completed, the dielectric isolation layer 63 is removed, and a passivation layer 70 is formed on the p-type gate layer 60. The material for forming the passivation layer 70 on the gate layer 60 is silicon nitride, which plays an insulating role.

S90, forming a gate electrode, a source electrode and a drain electrode; wherein the gate electrode is formed in the first region, the source electrode and the drain electrode are formed in the second region, and the p-type dopant of the p-type gate layer is activated in the first region , in the second region, the p-type dopant of the p-type gate layer is not activated.

Specifically, referring to FIG. 4J , the passivation layer 70 on the gate position of the first region pre-11 and the passivation layer 70 on the source electrode 11 and the drain electrode 12 in the second region 12 are removed, and the passivation layer 70 in the first region pre-12 is removed. A gate metal is formed on the gate position of 11 to form the gate electrode 80 , and ohmic metal is formed on the position of the source electrode 90 and the drain electrode 100 in the second region 12 to form the source electrode 90 and the drain electrode 100 , respectively. The gate electrode 80 is formed in the first region 11 , the p-type dopant of the p-type gate layer 60 in the film layer of the first region 11 is activated, and the source electrode 90 and the drain electrode 100 are formed in the second region 12 , p The p-type dopant of the type gate layer 60 in the film layer of the second region 12 is not activated.

Optionally, forming the gate in the first region includes:

S91, forming a gate contact window by photolithography and etching the gate position region in the first region, and activating the p-type gate layer leaking from the gate window;

S92 , a gate is fabricated, and the gate is in contact with the drained p-type gate layer through the gate contact window.

Exemplarily, to form the gate electrode 80 in the first region 11, the passivation layer 70 on the position where the gate electrode 80 needs to be fabricated in the gate position region may be formed by a combination of wet etching or dry etching with a photolithography technique. Then, a gate contact window is made; and a gate electrode is made on the gate position by means of photolithography and metal evaporation. The gate 80 and the p-type gate layer 60 can be in ohmic contact or Schottky contact; the electrode structure is preferably a stack of one or more metals in Ni, Ti, Al, Au, TiN, W, Pt, Pd, and Mo. layer structure. Among them, the metal evaporation method includes magnetron sputtering, electron beam evaporation or electroplating scheme.

Forming the source and drain in the second region includes various methods:

Optionally, referring to FIG. 5 , FIG. 5 is a flowchart of a method for forming a source electrode and a drain electrode in a second region according to Embodiment 2 of the present invention. Forming a source electrode and a drain electrode in the second region includes:

S93, forming an ohmic contact window by etching the source electrode position and the drain electrode position in the second region; the ohmic contact window leaks the part of the barrier layer;

S94, evaporating ohmic contact metal at the source position and the drain position;

S95, etching away the metal material other than the ohmic contact metal on the source position and the drain position to form the source electrode and the drain electrode;

S96, annealing the source electrode and the drain electrode through an annealing process to form a metal-semiconductor ohmic contact.

Specifically, after the ohmic contact window is fabricated, the ohmic contact window can leak out of the barrier layer 50 , the upper surface of the barrier layer 50 can be leaked, the interior of the barrier layer 50 can be leaked, and the trench can be penetrated through the barrier layer 50 The surface of the track layer 40 is not limited here; first, ohmic contact metal is evaporated on the source and drain positions, and then photoresist is coated on the passivation layer 70. The photoresist is left in the photolithography exposure method, and then the ohmic metal at the position not covered by the photoresist is removed by dry etching or corrosion, and the metal at the position covered by the photoresist is left as the source electrode 90 metal and the ohmic metal. Drain 100 metal. The ohmic metal uses high temperature rapid annealing equipment to thermally anneal the metal of the source electrode 90 and the metal of the drain electrode 100, so as to realize a source-drain ohmic contact structure. Depending on the material and composition of the metal electrode, the annealing temperature is generally 500°C to 900°C, and the annealing environment is a nitrogen environment.

Optionally, referring to FIG. 6 , FIG. 6 is a flowchart of another method for forming a source electrode and a drain electrode in a second region provided by Embodiment 2 of the present invention. Forming a source electrode and a drain electrode in the second region includes:

S97, forming an ohmic contact window by etching the source electrode position and the drain electrode position in the second region; the ohmic contact window leaks the part of the barrier layer;

S98, forming a photoresist layer on the dielectric isolation layer;

S99, removing the photoresist at the source position and the drain position;

S100, evaporating ohmic contact metal at the source position and the drain position;

S101, removing the photoresist layer;

S102 , annealing the source electrode and the drain electrode through an annealing process to form a metal-semiconductor ohmic contact.

Specifically, after the ohmic contact window is fabricated, the ohmic contact window can leak out of the barrier layer 50 , the upper surface of the barrier layer 50 can be leaked, the interior of the barrier layer 50 can be leaked, and the trench can be penetrated through the barrier layer 50 The surface of the track layer 40 is not limited here; first, the photoresist is coated on the passivation layer 70, and the photoresist is removed by photolithography exposure at the positions where the source electrode 90 and the drain electrode 100 need to be fabricated, and the evaporation is continued. The ohmic contact metal is then removed; in this way, only the source 90 and drain 100 positions have ohmic contact metal to form the source 90 and the drain 100, and the metal at other positions is removed along with the photoresist. The ohmic metal uses high temperature rapid annealing equipment to thermally anneal the metal of the source electrode 90 and the metal of the drain electrode 100, so as to realize a source-drain ohmic contact structure. Depending on the material and composition of the metal electrode, the annealing temperature is generally 500°C to 900°C, and the annealing environment is a nitrogen environment.

An embodiment of the present invention provides a method for fabricating a GaN-based field effect transistor, including: providing an epitaxial wafer, the epitaxial wafer includes a stacked substrate, a buffer layer, a back barrier layer, a channel layer, a barrier layer and a p type gate layer; wherein, the dopant in the p-type gate layer is not activated; a gate mask is formed on the surface of the p-type gate layer; the part of the p-type gate layer not covered by the gate mask is thinned; the gate is removed mask; forming a dielectric isolation layer on the p-type gate layer; etching the dielectric isolation layer to expose part of the p-type gate layer, and the exposed area of the p-type gate layer is the gate position area; to the p-type gate layer of the gate position area The dopant in the device is selectively activated; a passivation layer is formed on the p-type gate layer; a gate electrode, a source electrode and a drain electrode are formed; wherein, the gate electrode is formed in the first region, and the p-type gate layer is formed in the first region. The p-type dopant in the film layer is activated, the source electrode and the drain electrode are formed in the second region, and the p-type dopant in the film layer of the p-type gate layer in the second region is not activated. It can improve the gate etching process, overcome the problem that the p-type material at the top of the channel must be completely removed in the traditional process, and the p-type material can be properly retained because the p-type dopant is not activated and presents a high resistance state, which can It reduces the fault tolerance rate of etching and is suitable for mass production. This technical method increases the process window width of gate etching, is not limited by the precision of the etching process, has high controllability and good repeatability.

Note that the above are only preferred embodiments of the present invention and applied technical principles. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and can also include more other equivalent embodiments without departing from the concept of the present invention. The scope is determined by the scope of the appended claims.

Claims (10)

1. a gallium nitride based field effect transistor, is characterized in that, comprises: Substrate, buffer layer, back barrier layer, channel layer, barrier layer, p-type gate layer and passivation layer; a gate electrode in contact with the p-type gate layer, and a source electrode and a drain electrode in contact with the barrier layer, wherein the gate electrode is located in a first region, and the source electrode and the drain electrode are located in a second region region, the p-type dopant of the p-type gate layer in the film layer of the second region is not activated. 2 . The GaN-based field effect transistor according to claim 1 , wherein a film thickness of the p-type gate layer in the first region is greater than that in the second region. 3 . 3 . The GaN-based field effect transistor according to claim 2 , wherein the thickness of the film layer of the p-type gate layer in the second region ranges from 2 nm to 300 nm. 4 . 4 . The gallium nitride based field effect transistor according to claim 1 , wherein the material of the p-type gate layer comprises at least one of p-GaN and p-AlGaN. 5 . 5. A preparation method of a gallium nitride-based field effect transistor, characterized in that, comprising: An epitaxial wafer is provided, the epitaxial wafer includes a substrate, a buffer layer, a back barrier layer, a channel layer, a barrier layer and a p-type gate layer; wherein, the dopant in the p-type gate layer is not activated; forming a gate mask on the surface of the p-type gate layer; thinning the portion of the p-type gate layer not covered by the gate mask; removing the gate mask; forming a dielectric isolation layer on the p-type gate layer; Etching the dielectric isolation layer to expose part of the p-type gate layer, and the exposed region of the p-type gate layer is the gate position region; selectively activating dopants in the p-type gate layer of the gate site region; forming a passivation layer on the p-type gate layer; forming a gate electrode, a source electrode and a drain electrode; wherein, the gate electrode is formed in a first region, and the source electrode and the drain electrode are formed in a second region; in the first region, the p-type gate layer is The p-type dopant is activated, and in the second region, the p-type dopant of the p-type gate layer is not activated. 6 . The method for manufacturing a GaN-based field effect transistor according to claim 5 , wherein the forming a gate mask on the surface of the p-type gate layer comprises: 6 . depositing a gate mask dielectric layer on the surface of the p-type gate layer; Making a photoresist mask on the surface of the gate mask dielectric layer; The gate mask dielectric layer is etched to form a gate mask at the gate position, and the p-type gate layer not covered by the gate mask leaks out. 7 . The method for manufacturing a GaN-based field effect transistor according to claim 5 , wherein the thinning of the portion of the p-type gate layer not covered by the gate mask comprises: 8 . The part of the p-type gate layer not covered by the gate mask is etched, so that the thickness of the part of the p-type gate layer not covered by the gate mask is smaller than the thickness of the p-type gate layer covered by the gate mask. thickness of the portion covered by the gate mask. 8 . The method for manufacturing a GaN-based field effect transistor according to claim 5 , wherein the forming the gate in the first region comprises: A gate contact window is formed in the gate position region in the first region by photolithography and etching, and the p-type gate layer leaked from the gate contact window is activated; A gate is formed in the gate contact window, and is in contact with the p-type gate layer leaked from the contact window. 9 . The method for manufacturing a GaN-based field effect transistor according to claim 5 , wherein forming the source electrode and the drain electrode in the second region comprises: 10 . An ohmic contact window is made by etching the source position and the drain position in the second region; the ohmic contact window leaks a portion of the barrier layer; Evaporating ohmic contact metal at the source position and the drain position; etching away metal materials other than the ohmic contact metal on the source electrode position and the drain electrode position to form the source electrode and the drain electrode; The source electrode and the drain electrode are annealed through an annealing process to form a metal-semiconductor ohmic contact. 10 . The method for fabricating a GaN-based field effect transistor according to claim 5 , wherein the forming the source electrode and the drain electrode in the second region comprises: 10 . An ohmic contact window is made by etching the source position and the drain position in the second region; the ohmic contact window leaks a portion of the barrier layer; forming a photoresist layer on the dielectric isolation layer; removing the photoresist at the source position and the drain position; Evaporating ohmic contact metal at the source position and the drain position; removing the photoresist layer; The source electrode and the drain electrode are annealed through an annealing process to form a metal-semiconductor ohmic contact.

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