CN110770160B - Flow channel structure device and its manufacturing method - Google Patents

Abstract

A flow channel structure device and method of making the same, the method comprising: providing a substrate (21) comprising a first portion (211) and a second portion (212) adjoining the first portion (211); forming a patterned first sacrificial layer (31) on the substrate (21), the first sacrificial layer (31) covering the second portion (212) and exposing the first portion (211); forming a first structural layer (41) on a first portion (211) of a substrate (21) and a first sacrificial layer (31); performing a first polishing process to expose the first sacrificial layer (31); removing the first sacrificial layer (31) to expose an upper surface of the second portion (212) of the substrate (21) and a side surface of the first structural layer (41); forming a second sacrificial layer (32) on a part of the upper surface of the second portion (212) of the substrate (21), wherein the second sacrificial layer (32) covers a side of the first structural layer (41); forming a second structural layer (42) on the second portion (212) of the substrate (21), the second sacrificial layer (32) and the first structural layer (41); performing a second polishing process to expose a second sacrificial layer (32); and removing the second sacrificial layer (32) by using a selective etching process to form a flow channel (50); the method can realize the flow channel structure device with the vertical flow channel.

Description

Flow channel structure device and its manufacturing method

technical field

The present invention relates to the technical field of semiconductors, in particular to a flow channel structure device and a manufacturing method thereof.

Background technique

Micro-nanofluidic analysis technology based on micro-nano flow channel is receiving more and more research and application in the fields of biochemical analysis and gene sequencing. The combination of micro-nano flow channel device and integrated circuit (Integrated Circuit, referred to as IC) will also help to improve the automation and miniaturization of the micro-analysis system, and better expand its application space. In some applications, electrode materials need to be embedded in the micro-nano channels, and in some designs, nano-channels with high aspect ratios are required.

In the traditional method, electron beam lithography or laser lithography can be used in combination with anisotropic etching process to realize nano-channels. However, direct electron beam or laser lithography methods have low efficiency and poor size tunability, and it is difficult to achieve high aspect ratios on metal materials, usually only about 1.

In the prior art, the sidewall method can also be used to realize the above-mentioned micro-nano flow channel structure. However, the sidewall method must rely on the sidewall support structure of semiconductor materials to realize structural interconnection and signal extraction, which will bring more parasitic effects and ultimately affect the quality of the detection signal, and the process thermal budget is high, which is not conducive to integration with CMOS chips. . For example, most of the electrode leads in the prior art need to rely on spliced metal interconnect lines (eg, typical materials are aluminum and copper) or semiconductor interconnect lines (eg, typical materials are polysilicon) and electrode materials to form alloy structure leads. However, the alloy structure has the following disadvantages: (1) The alloy process requires an additional heat treatment process, which will increase the process thermal budget and is not conducive to the implementation of process integration on the IC chip. Taking the typical polysilicon interconnect process as an example, a polysilicon deposition process (the temperature is usually high (600℃), ion implantation and activation (usually above 550℃), and metal-semiconductor alloys (usually above 400℃) with relatively high thermal budget; (2) the alloy body will introduce additional contact resistance, which will degrade device performance. In addition, there is also a lateral flow channel structure of metal leads in the prior art, but in such a lateral flow channel structure, the metal electrodes are relatively distributed on the upper and lower sides of the flow channel, which will affect its application range. For example, it cannot be used for Include light-emitting applications, as the light signal will be blocked by the upper and lower electrodes. Moreover, such a lateral flow channel structure also limits the fabrication density on the chip.

In the prior art, the nanogap structure can also be realized by adjusting the metal sputtering angle. In this sputtering process, the sputtering direction of the particles is at a certain angle with the surface of the substrate. By adjusting the angle, a dead space for sputtering can be generated at the bottom of the pre-prepared trench, thereby obtaining a nano-gap flow channel structure. Poor controllability and size adjustability.

SUMMARY OF THE INVENTION

The inventors of the present invention found that there are problems in the above-mentioned prior art, and therefore proposed a new technical solution for at least one of the problems.

According to a first aspect of the present invention, there is provided a method for manufacturing a flow channel structure device, comprising: providing a substrate, the substrate including a first part and a second part adjacent to the first part; on the substrate forming a patterned first sacrificial layer, the first sacrificial layer covering the second part and exposing the first part; forming a first structure layer on the first part of the substrate and the first sacrificial layer; After forming the first structure layer, a first polishing process is performed to expose the first sacrificial layer; the first sacrificial layer is removed to expose the upper surface of the second portion of the substrate and the first structure the side of the layer; a second sacrificial layer is formed on a part of the upper surface of the second part of the substrate, wherein the second sacrificial layer covers the exposed side of the first structural layer; on the side of the substrate forming a second structure layer on the second part, the second sacrificial layer and the first structure layer; after forming the second structure layer, performing a second polishing process to expose the second sacrificial layer; and using A selective etching process removes the second sacrificial layer to form flow channels.

In one embodiment, in the step of performing the second polishing process, the first structural layer and the second structural layer are further exposed; before the second sacrificial layer is removed by a selective etching process, The method also includes forming a capping layer on the second sacrificial layer, the first structural layer, and the second structural layer.

In one embodiment, the step of forming the first structural layer includes: forming a first material layer on the first portion of the substrate and the first sacrificial layer, wherein the first material layer covers the first material layer. A side surface of a sacrificial layer; and forming a first support layer on the first material layer; wherein, the first structure layer includes: the first material layer and the first support layer; the forming a second The step of the structural layer includes: forming a second material layer on the second portion of the substrate, the second sacrificial layer and the first structural layer, the second material layer covering the second sacrificial layer. and forming a second support layer on the second material layer; wherein the second structure layer includes: the second material layer and the second support layer.

In one embodiment, in the step of removing the first sacrificial layer to expose the side surface of the first structure layer, the exposed side surface of the first structure layer is the side surface of the first material layer; in In the step of forming the second sacrificial layer, the second sacrificial layer covers the exposed side surface of the first material layer.

In one embodiment, in the step of performing the second polishing process, the first material layer, the first support layer, the second material layer and the second support layer are further exposed; Before removing the second sacrificial layer by a selective etching process, the method further includes: removing the second sacrificial layer, the first material layer, the first support layer, the second material layer and the second sacrificial layer. A cap layer is formed on the second support layer.

In one embodiment, the material of the capping layer includes: an insulating dielectric material or a semiconductor material; the thickness of the capping layer ranges from 1 nanometer to 10 micrometers.

In one embodiment, in the step of removing the second sacrificial layer by a selective etching process, a selective etching solution is injected from the edge of the second sacrificial layer to remove the second sacrificial layer.

In one embodiment, prior to removing the second sacrificial layer using a selective etching process, the method further includes: etching the capping layer to form through the capping layer and exposing the second sacrificial layer A through hole of the layer; wherein, in the step of removing the second sacrificial layer by a selective etching process, a selective etching solution is injected from the through hole to remove the second sacrificial layer.

In one embodiment, a part of the first material layer is between the first support layer and the flow channel, and another part of the first material layer is between the first support layer and the substrate between the first part of the second material layer; a part of the second material layer is between the second support layer and the flow channel, and another part of the second material layer is between the second support layer and the substrate between the second part.

In one embodiment, the material of the first material layer includes: a metal material or a semiconductor material; the material of the second material layer includes: a metal material or a semiconductor material; wherein, the material of the first material layer in the The part between the first support layer and the flow channel serves as the first electrode of the flow channel structure device; the part of the first material layer between the first support layer and the first part of the substrate part of the first lead of the first electrode; part of the second material layer between the second support layer and the flow channel as the second electrode of the flow channel structure device; the first The portion of the two-material layer between the second support layer and the second portion of the substrate serves as the second lead of the second electrode.

In one embodiment, the material of the first material layer and the material of the second material layer respectively include: an insulating dielectric material.

In one embodiment, the thickness of the first sacrificial layer is determined according to the required height of the flow channel; the thickness of the first sacrificial layer ranges from 100 nanometers to 100 micrometers.

In one embodiment, the thickness of the second sacrificial layer is determined according to the required width of the flow channel; the thickness of the second sacrificial layer ranges from 0.1 nanometer to 1 micrometer.

In one embodiment, the thickness of the first material layer is in the range of 1 nanometer to 500 nanometers; the thickness of the first support layer is in the range of 100 nanometers to 100 micrometers; the thickness of the second material layer is in the range of 1 nanometer to 500 nanometers; the thickness of the second support layer ranges from 100 nanometers to 100 micrometers.

In the above manufacturing method, a patterned first sacrificial layer is formed on a substrate; a first structural layer is formed on a first portion of the substrate and the first sacrificial layer; a first polishing process is performed to expose the first sacrificial layer; a sacrificial layer to expose the upper surface of the second part of the substrate and the side surface of the first structural layer; a second sacrificial layer is formed on part of the upper surface of the second part of the substrate; on the second part of the substrate, the second forming a second structure layer on the sacrificial layer and the first structure layer; after forming the second structure layer, performing a second polishing process to expose the second sacrificial layer; and removing the second sacrificial layer using a selective etching process to form runner. The above-mentioned manufacturing method of the present invention can form a flow channel structure device with vertical flow channels, and the above-mentioned manufacturing method can reduce the thermal budget of the process and facilitate the integration of the flow channel structure device and the CMOS chip.

Further, in the above manufacturing method, the thickness of the first sacrificial layer and the thickness of the second sacrificial layer can be determined according to design requirements, so a flow channel structure with a high aspect ratio can be realized.

Further, when the first material layer and the second material layer are respectively made of conductive materials such as metal or semiconductor, the first material layer may include a first electrode and a first lead, and the second material layer may include a second electrode and a first lead. Two leads, since the first material layer and the second material layer are integrally formed respectively, therefore, compared with the prior art, the contact resistance between the first electrode and the first lead can be reduced, and the contact resistance between the second electrode and the second lead can be reduced. Contact resistance can also be reduced, which can improve device performance.

According to a second aspect of the present invention, there is provided a flow channel structure device, comprising: a substrate including a first portion and a second portion adjacent to the first portion; a first structure on the substrate layer and a second structural layer; wherein the first structural layer comprises: a first material layer on a first portion of the substrate and a first support layer on the first material layer, the second The structural layer includes: a second material layer on the second portion of the substrate and a second support layer on the second material layer; between the first material layer and the second material layer The first support layer and the second support layer are respectively on both sides of the flow channel; wherein, a part of the first material layer is between the first support layer and the flow channel. and another part of the first material layer is between the first support layer and the first part of the substrate; a part of the second material layer is between the second support layer and the flow channel and another portion of the second material layer is between the second support layer and the second portion of the substrate.

In one embodiment, the flow channel structure device further comprises: a cap layer covering the first material layer, the first support layer, the second material layer and the second support layer; wherein , the cap layer covers the flow channel.

In one embodiment, the material of the capping layer includes: an insulating dielectric material or a semiconductor material; the thickness of the capping layer ranges from 1 nanometer to 10 micrometers.

In one embodiment, the flow channel structure device further includes: a through hole penetrating the cap layer and communicating with the flow channel.

In one embodiment, the material of the first material layer includes: a metal material or a semiconductor material; the material of the second material layer includes: a metal material or a semiconductor material; wherein, the material of the first material layer in the The part between the first support layer and the flow channel serves as the first electrode of the flow channel structure device; the part of the first material layer between the first support layer and the first part of the substrate part of the first lead of the first electrode; part of the second material layer between the second support layer and the flow channel as the second electrode of the flow channel structure device; the first The portion of the two-material layer between the second support layer and the second portion of the substrate serves as the second lead of the second electrode.

In one embodiment, the material of the first material layer and the material of the second material layer respectively include: an insulating dielectric material.

In one embodiment, the height of the flow channel is in the range of 100 nanometers to 100 micrometers; the width of the flow channel is in the range of 0.1 nanometers to 1 micrometer.

In one embodiment, the thickness of the first material layer is in the range of 1 nanometer to 500 nanometers; the thickness of the first support layer is in the range of 100 nanometers to 100 micrometers; the thickness of the second material layer is in the range of 1 nanometer to 500 nanometers; the thickness of the second support layer ranges from 100 nanometers to 100 micrometers.

The flow channel structure device of the above embodiments of the present invention has vertical flow channels, which can improve the manufacturing density of the flow channels on the chip, and reduce the manufacturing and application costs.

Further, the above-mentioned flow channel structure device can realize a flow channel structure with a high aspect ratio.

Further, when the first material layer and the second material layer are respectively made of conductive materials such as metal or semiconductor, the first material layer may include a first electrode and a first lead, and the second material layer may include a second electrode and a first lead. Two leads, since the first material layer and the second material layer are integrally formed respectively, therefore, compared with the prior art, the contact resistance between the first electrode and the first lead can be reduced, and the contact resistance between the second electrode and the second lead can be reduced. Contact resistance can also be reduced, which can improve device performance.

According to a third aspect of the present invention, a flow channel sensor is provided, comprising: the aforementioned flow channel structure device.

According to a fourth aspect of the present invention, a biochemical analysis device is provided, comprising: the aforementioned flow channel structure device.

According to a fifth aspect of the present invention, there is provided a chip for molecular detection, comprising: a flow channel structure device, a signal collection unit and a signal processing unit as described above; wherein a sample to be detected is added to the flow channel In the flow channel of the structural device, when the electrodes of the flow channel structural device are applied with electrical excitation, the target molecules in the sample to be detected generate electrical signals or optical signals under the action of electrical excitation; the signal collection unit is used for collecting the electrical signal or the optical signal, and transmitting the electrical signal or the optical signal to the signal processing unit; the signal processing unit is used for performing signal processing on the electrical signal or the optical signal , to identify the information of the target molecule.

According to a sixth aspect of the present invention, there is provided a molecular detection method, comprising: using the aforementioned chip for molecular detection.

In one embodiment, the step of using the chip for molecular detection includes: processing the sample to be detected; adding the sample to be detected into the chip; applying the application to electrodes in the flow channel structure device in the chip Electrical excitation, so that the target molecule in the sample to be detected generates an electrical signal or an optical signal under the action of electrical excitation; and the signal processing unit of the chip obtains the electrical signal or the optical signal through the signal collection unit signal, and perform signal processing on the electrical signal or the optical signal to identify the information of the target molecule.

In the above-mentioned embodiments, the application of molecular detection is realized by using the chip including the flow channel structure device of the embodiment of the present invention.

Other features and advantages of the present invention will become apparent from the following detailed description of exemplary embodiments of the present invention with reference to the accompanying drawings.

Description of drawings

The accompanying drawings, which form a part of the specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.

The present invention may be more clearly understood from the following detailed description with reference to the accompanying drawings, wherein:

FIG. 1 is a flowchart illustrating a method of manufacturing a flow channel structure device according to an embodiment of the present invention.

2 to 10 are cross-sectional views schematically showing structures at several stages in a manufacturing process of a flow channel structure device according to an embodiment of the present invention.

11 is a cross-sectional view schematically showing the structure of a stage in a manufacturing process of a flow channel structure device according to another embodiment of the present invention.

FIG. 12 is a plan view schematically showing the structure of a stage in a manufacturing process of a flow channel structure device according to another embodiment of the present invention.

13 is a cross-sectional view schematically showing the structure of a stage in a manufacturing process of a flow channel structure device according to another embodiment of the present invention.

14 to 22 are cross-sectional views schematically showing structures of several stages in a manufacturing process of a flow channel structure device according to another embodiment of the present invention.

23 is a cross-sectional view schematically showing the structure of a stage in a manufacturing process of a flow channel structure device according to another embodiment of the present invention.

24 is a cross-sectional view schematically showing the structure of a stage in a manufacturing process of a flow channel structure device according to another embodiment of the present invention.

FIG. 25 is a structural diagram schematically showing a chip for molecular detection according to an embodiment of the present invention.

Figure 26 is a flow chart illustrating a molecular detection method according to one embodiment of the present invention.

Detailed ways

Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the invention unless specifically stated otherwise.

Meanwhile, it should be understood that, for the convenience of description, the dimensions of various parts shown in the accompanying drawings are not drawn in an actual proportional relationship.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus should be considered part of the specification.

In all examples shown and discussed herein, any specific value should be construed as illustrative only and not as limiting. Accordingly, other examples of exemplary embodiments may have different values.

It should be noted that like numerals and letters refer to like items in the following figures, so once an item is defined in one figure, it does not require further discussion in subsequent figures.

FIG. 1 is a flowchart illustrating a method of manufacturing a flow channel structure device according to an embodiment of the present invention. 2 to 10 are cross-sectional views schematically showing structures at several stages in a manufacturing process of a flow channel structure device according to an embodiment of the present invention. The manufacturing process of the flow channel structure device according to an embodiment of the present invention will be described in detail below with reference to FIG. 1 and FIGS. 2 to 10 .

As shown in FIG. 1, in step S101, a substrate is provided, the substrate including a first portion and a second portion adjacent to the first portion.

FIG. 2 is a cross-sectional view schematically showing a structure at step S101 in a manufacturing process of a flow channel structure device according to an embodiment of the present invention. As shown in FIG. 2 , a substrate 21 is provided, which may include a first portion 211 and a second portion 212 adjoining the first portion 211 . For example, the substrate may include: a semiconductor substrate (eg, silicon, germanium, etc.), an insulating substrate (eg, quartz, silicon nitride, etc.), a wafer with integrated IC circuits, or any combination of these substrates.

It should be noted that the dotted line in FIG. 2 is only for the convenience of illustrating the first part and the second part, and the line does not necessarily exist in practice, and the following drawings are similar.

Returning to FIG. 1 , in step S102 , a patterned first sacrificial layer is formed on the substrate, and the first sacrificial layer covers the second portion and exposes the first portion.

FIG. 3 is a cross-sectional view schematically illustrating a structure at step S102 in a manufacturing process of a flow channel structure device according to an embodiment of the present invention. As shown in FIG. 3 , a patterned first sacrificial layer 31 is formed on the substrate 21 , the first sacrificial layer 31 covers the second portion 212 and exposes the first portion 211 . The first sacrificial layer can serve as a defining layer for the position of the flow channel. The thickness of the first sacrificial layer can be determined according to the required height of the flow channel. In one embodiment, the thickness of the first sacrificial layer may range from 100 nanometers to 100 micrometers. For example, the thickness of the first sacrificial layer may be 500 nanometers, 1 micrometer, 10 micrometers, or 50 micrometers. In one embodiment, the material of the first sacrificial layer may include: semiconductor materials (eg, polysilicon, amorphous silicon, indium tin oxide, etc. or a combination of multiple semiconductor materials), insulating dielectric materials (eg, silicon oxide, nitrogen Silicon oxide, silicon oxynitride, etc., or a combination of various insulating dielectric materials) or a metal material (eg, aluminum, copper, etc., or a combination of various metal materials).

Optionally, the step S102 may include: forming a first sacrificial layer on the substrate, the first sacrificial layer covering the first part and the second part of the substrate. Optionally, the step S102 may further include: patterning the first sacrificial layer by using a photolithography method, so as to remove a part of the first sacrificial layer covering the first part to expose the first part. For example, the lithography method may include pattern exposure, pattern development, pattern etching, and the like. For example, the pattern exposure method may include: optical exposure, electron beam exposure, or nanoimprinting. For example, the pattern etching method may include wet etching or dry etching.

Returning to FIG. 1, in step S103, a first structural layer is formed on the first portion of the substrate and the first sacrificial layer.

FIG. 4 is a cross-sectional view schematically showing the structure at step S103 in the manufacturing process of the flow channel structure device according to one embodiment of the present invention. As shown in FIG. 4 , the first structural layer 41 is formed on the first portion 211 of the substrate 21 and the first sacrificial layer 31 by, for example, a deposition process. The first structure layer 41 covers the side surface of the first sacrificial layer 31 . Preferably, the thickness of the first structural layer is greater than or equal to the thickness of the first sacrificial layer, so that in the subsequent process of performing the first polishing process, the part of the first sacrificial layer can be polished and removed as little as possible, which is conducive to good control The height of the runner obtained subsequently. Of course, the scope of the present invention is not limited to this, for example, the thickness of the first structural layer may also be smaller than the thickness of the first sacrificial layer.

In one embodiment, the material of the first structural layer may include: metal materials (eg, gold, platinum, silver, titanium, titanium nitride, etc. or a combination of multiple metal materials), semiconductor materials (eg, polysilicon, non- crystalline silicon, indium tin oxide, etc., or a combination of multiple semiconductor materials) or insulating dielectric materials (eg, silicon oxide, silicon nitride, silicon oxynitride, etc., or a combination of multiple insulating dielectric materials).

Returning to FIG. 1 , in step S104 , after the first structural layer is formed, a first polishing process is performed to expose the first sacrificial layer.

FIG. 5 is a cross-sectional view schematically showing the structure at step S104 in the manufacturing process of the flow channel structure device according to one embodiment of the present invention. As shown in FIG. 5 , for example, a first polishing process (eg, CMP (Chemical Mechanical Polishing)) is performed on the semiconductor structure shown in FIG. 4 , thereby exposing the top surface of the first sacrificial layer 31 . The polishing process may remove portions of the first structural layer on the top surface of the first sacrificial layer.

Returning to FIG. 1 , in step S105 , the first sacrificial layer is removed to expose the upper surface of the second portion of the substrate and the side surface of the first structural layer.

FIG. 6 is a cross-sectional view schematically showing the structure at step S105 in the manufacturing process of the flow channel structure device according to one embodiment of the present invention. As shown in FIG. 6 , for example, the first sacrificial layer 31 is removed by a selective etching process, thereby exposing the upper surface of the second portion 212 of the substrate 21 and the side surface of the first structure layer 41 . For example, the selective etching process may include dry etching or wet etching.

Returning to FIG. 1 , in step S106 , a second sacrificial layer is formed on a portion of the upper surface of the second portion of the substrate, wherein the second sacrificial layer covers the exposed side surface of the first structural layer.

FIG. 7 is a cross-sectional view schematically illustrating a structure at step S106 in a manufacturing process of a flow channel structure device according to an embodiment of the present invention. As shown in FIG. 7 , a second sacrificial layer 32 is formed on a part of the upper surface of the second part 212 of the substrate 21 with the first structural layer 41 as a support, wherein the second sacrificial layer 32 covers the first structural layer 41 exposed side. For example, the step S106 may include: depositing a second sacrificial layer on the semiconductor structure shown in FIG. 6 ; and then performing an etch back on the second sacrificial layer, thereby forming the structure shown in FIG. 7 . The thickness of the second sacrificial layer can be determined according to the required width of the flow channel. In one embodiment, the thickness of the second sacrificial layer may range from 0.1 nanometer to 1 micrometer. For example, the thickness of the second sacrificial layer may be 1 nanometer, 10 nanometers, 100 nanometers, or 500 nanometers.

In one embodiment, the material of the second sacrificial layer may include: metal materials (eg, chromium, aluminum, titanium, etc. or a combination of multiple metal materials), semiconductor materials (eg, polysilicon, amorphous silicon, indium tin oxide, etc., or a combination of semiconductor materials) or an insulating dielectric material (eg, silicon oxide, silicon nitride, silicon oxynitride, etc., or a combination of multiple insulating dielectric materials).

Returning to FIG. 1, in step S107, a second structure layer is formed on the second portion of the substrate, the second sacrificial layer and the first structure layer.

FIG. 8 is a cross-sectional view schematically showing the structure at step S107 in the manufacturing process of the flow channel structure device according to one embodiment of the present invention. As shown in FIG. 8 , the second structure layer 42 is formed on the second portion 212 of the substrate 21 , the second sacrificial layer 32 and the first structure layer 41 , for example, by a deposition process. Preferably, the thickness of the second structural layer is greater than or equal to the height of the second sacrificial layer, so that during the subsequent second polishing process, the part of the second sacrificial layer can be polished and removed as little as possible, which is conducive to good control The height of the runner obtained subsequently. Of course, the scope of the present invention is not limited to this, for example, the thickness of the second structure layer may also be smaller than the height of the second sacrificial layer.

In one embodiment, the material of the second structural layer may include: metal materials (eg, gold, platinum, silver, titanium, titanium nitride, etc. or a combination of multiple metal materials), semiconductor materials (eg, polysilicon, non- crystalline silicon, indium tin oxide, etc., or a combination of multiple semiconductor materials) or insulating dielectric materials (eg, silicon oxide, silicon nitride, silicon oxynitride, etc., or a combination of multiple insulating dielectric materials).

Returning to FIG. 1 , in step S108 , after the second structural layer is formed, a second polishing process is performed to expose the second sacrificial layer.

FIG. 9 is a cross-sectional view schematically showing the structure at step S108 in the manufacturing process of the flow channel structure device according to one embodiment of the present invention. As shown in FIG. 9 , for example, a second polishing process (eg, CMP) is performed on the semiconductor structure shown in FIG. 8 , thereby exposing the top surface of the second sacrificial layer 32 . In the step of performing the second polishing process, the first structure layer 41 and the second structure layer 42 may also be exposed, for example, the top surface of the first structure layer 41 and the top surface of the second structure layer 42 are exposed. The second polishing process may remove portions of the second structural layer on top surfaces of the first structural layer and the second sacrificial layer.

Returning to FIG. 1 , in step S109 , the second sacrificial layer is removed by a selective etching process to form a flow channel.

FIG. 10 is a cross-sectional view schematically showing the structure at step S109 in the manufacturing process of the flow channel structure device according to one embodiment of the present invention. As shown in FIG. 10 , the second sacrificial layer 32 is removed by a selective etching process to form the flow channel 50 . In one embodiment, the height of the flow channel may range from 100 nanometers to 100 micrometers. In one embodiment, the width of the flow channel may range from 0.1 nanometer to 1 micrometer.

So far, a method for fabricating a flow channel structure device according to an embodiment of the present invention is provided. In the manufacturing method, a patterned first sacrificial layer is formed on a substrate; a first structural layer is formed on a first portion of the substrate and the first sacrificial layer; a first polishing process is performed to expose the first sacrificial layer; a sacrificial layer to expose the upper surface of the second part of the substrate and the side surface of the first structural layer; a second sacrificial layer is formed on part of the upper surface of the second part of the substrate; on the second part of the substrate, the second forming a second structure layer on the sacrificial layer and the first structure layer; after forming the second structure layer, performing a second polishing process to expose the second sacrificial layer; and removing the second sacrificial layer using a selective etching process to form runner. Through the above manufacturing method, a flow channel structure device having vertical flow channels (ie, the flow channels are perpendicular to the surface of the substrate) can be formed. For example, the flow channel can be open space in a direction perpendicular to the substrate or can be provided with a transparent material so that this does not affect the transmission of the optical signal. In addition, by using vertical flow channels, the effective surface area of a single flow channel can be the cross-sectional area of the flow channel, which can greatly improve the manufacturing density of the flow channels on the chip, and reduce the manufacturing and application costs.

The above-mentioned manufacturing method of the embodiment of the present invention can reduce the thermal budget of the process. For example, the process temperature involved in the method of the present invention is relatively low (the temperature range is between room temperature and 350° C.), and the heat treatment process time is short, thus reducing the process thermal budget and facilitating the integration of the runner structure device and the CMOS chip.

Further, in the above manufacturing method, the thickness of the first sacrificial layer and the thickness of the second sacrificial layer can be determined according to design requirements, so a flow channel structure with a high aspect ratio can be realized. For example, a flow channel structure with a width of 10 nm and an aspect ratio of 100:1 can be realized. The aspect ratio of the flow channel structure implemented by the method of the embodiment of the present invention may range from 1:1 to 100,000:1.

Through the above manufacturing method, a flow channel structure device is formed. The flow channel structure device includes: a substrate, a first structure layer and a second structure layer on the substrate, and a flow channel between the first structure layer and the second structure layer. In the case where the first structural layer and the second structural layer are made of insulating dielectric materials, respectively, an insulating dielectric flow channel structure device can be formed, which can be applied to fluid formation and control, and the like. Where the first and second structural layers are each a conductive material (eg a metallic material or a semiconductor material (eg a doped semiconductor material)), they can act as electrodes on both sides of the flow channel, which can be used for fluid handling , biochemical detection and other applications.

11 and 13 are cross-sectional views schematically showing structures of several stages in a manufacturing process of a flow channel structure device according to another embodiment of the present invention. FIG. 12 is a plan view schematically showing the structure of a stage in a manufacturing process of a flow channel structure device according to another embodiment of the present invention. The manufacturing process of the flow channel structure device according to other embodiments of the present invention will be described in detail below with reference to FIGS. 11 to 13 .

In an embodiment of the present invention, before removing the second sacrificial layer by a selective etching process, the manufacturing method may further include: as shown in FIG. A cap layer 60 is formed on the second structural layer 42 . In the subsequent step of forming the flow channel, the cap layer 60 can realize the closed flow channel together with the first structure layer 41 and the second structure layer 42 (that is, the upper part of the flow channel is closed), and the first structure layer 41 can also be avoided. and the parasitic reaction that may be brought about by the contact between the upper surface of the second structural layer 42 and the fluid. Furthermore, for some applications that require the flow of fluids (eg, liquids) in the flow channel, the flow channel covered with the capping layer of this embodiment makes it easier to control the flow of these fluids. In one embodiment, the material of the capping layer 60 may include: insulating dielectric materials (eg, silicon oxide, silicon nitride, silicon oxynitride, borophosphosilicate glass, aluminum oxide, titanium oxide or tantalum oxide, etc.) or semiconductor materials (eg, polysilicon or amorphous silicon, etc.). In one embodiment, the thickness of the capping layer 60 may range from 1 nanometer to 10 micrometers. For example, the thickness of the capping layer may be 10 nanometers, 100 nanometers, 500 nanometers, 1 micrometer, or 5 micrometers.

In one embodiment, in the step of removing the second sacrificial layer by a selective etching process, a selective etching solution may be injected from the edge of the second sacrificial layer to remove the second sacrificial layer, thereby forming the second sacrificial layer as shown in FIG. 13 . The flow channel structure device shown. In the actual planar structure, the planar extending second sacrificial layer is bounded, and the edge of the second sacrificial layer can be exposed, so a selective etchant is injected at the edge (ie, the boundary) of the second sacrificial layer to remove The second sacrificial layer, thereby forming the flow channel.

In another embodiment, before using the selective etching process to remove the second sacrificial layer, the manufacturing method may further include: as shown in FIG. 12 , etching the capping layer 60 to form penetrating through the capping layer and exposing The through hole 61 of the second sacrificial layer. Wherein, in the step of removing the second sacrificial layer by a selective etching process, a selective etching solution may be injected from the through hole 61 to remove the second sacrificial layer, thereby forming a flow channel structure device as shown in FIG. 13 . Those skilled in the art should understand that the number, shape or size of the through holes can be determined according to design requirements, and the scope of the present invention is not limited to the number, shape or size of the through holes shown in FIG. 12 . In this embodiment, by forming a through hole on the cap layer 60, in the selective etching process, it is favorable for the selective etching solution to pass through the through hole to remove the second sacrificial layer, and the etching rate can be accelerated.

In the flow channel structure device shown in FIG. 13 , in addition to having the same or similar structure as FIG. 10 , the flow channel structure device further includes: a cap layer 60 on the first structure layer 41 and the second structure layer 42 , the cap layer 60 covers the flow channel. The cap layer 60 can realize a closed flow channel together with the first structure layer 41 and the second structure layer 42 (that is, the upper part of the flow channel is closed), and can also avoid the upper surface of the first structure layer 41 and the second structure layer 42 Possible parasitic reactions from contact with fluids. Furthermore, for some applications that require the flow of fluids (eg, liquids) in the flow channel, the flow channel covered with the capping layer of this embodiment makes it easier to control the flow of these fluids. Optionally, the flow channel structure device may further include: through holes penetrating the cap layer and communicating with the flow channel.

In one embodiment, the step of forming the first structural layer may include: forming a first material layer on the first portion of the substrate and the first sacrificial layer, wherein the first material layer covers sides of the first sacrificial layer; and A first support layer is formed on the first material layer. Wherein, the first structural layer may include: the first material layer and the first support layer.

In another embodiment, the step of forming the second structural layer may include: forming a second material layer on the second portion of the substrate, the second sacrificial layer and the first structural layer, the second material layer covering the second material layer sides of the sacrificial layer; and forming a second support layer on the second material layer. Wherein, the second structural layer may include: the second material layer and the second support layer.

14 to 22 are cross-sectional views schematically showing structures of several stages in a manufacturing process of a flow channel structure device according to another embodiment of the present invention. Hereinafter, the first structural layer includes a first material layer and a first support layer, and the second structural layer includes a second material layer and a second support layer as an example, and another embodiment according to the present invention will be described in detail with reference to FIGS. 14 to 22 . The fabrication process of the flow channel structure device.

First, a substrate is provided that includes a first portion and a second portion adjoining the first portion. This step has been described in detail above with reference to FIG. 2 , and will not be repeated here.

Next, a patterned first sacrificial layer is formed on the substrate, the first sacrificial layer covering the second portion and exposing the first portion. This step has been described in detail above with reference to FIG. 3 , and will not be repeated here.

Next, as shown in FIG. 14 , a first material layer 411 is formed on the first portion 211 of the substrate 21 and the first sacrificial layer 31 by, for example, a deposition process, wherein the first material layer 411 covers the first sacrificial layer 31 side.

In one embodiment, the material of the first material layer 411 may include: a metal material (eg, gold, platinum, silver, titanium, titanium nitride, etc., or a combination of multiple metal materials) or a semiconductor material (eg, polysilicon, Amorphous silicon, indium tin oxide, etc. or a combination of various semiconductor materials). In this embodiment, the first material layer can be a conductive material such as a metal material or a semiconductor material (for example, a doped semiconductor material), so that the first material layer can be used as one of the embedded electrode layers of the subsequently formed flow channel. It is used in fluid treatment or biochemical detection, etc.

In another embodiment, the material of the first material layer 411 may include an insulating dielectric material (eg, silicon oxide, silicon nitride, silicon oxynitride, etc., or a combination of multiple insulating dielectric materials). In this way, a flow channel formed of an insulating medium material can be formed in the subsequent steps, which can be applied to the formation and control of the fluid, and the like.

In one embodiment, the thickness of the first material layer 411 may range from 1 nanometer to 500 nanometers. For example, the thickness of the first material layer 411 may be 10 nanometers, 50 nanometers, 100 nanometers, or 300 nanometers.

Next, as shown in FIG. 15 , a first support layer 412 is formed on the first material layer 411 by, for example, a deposition process. The first support layer 412 may serve as a support layer for the first material layer 411 . So far, the first structure layer 41 is formed. The first structural layer 41 may include: a first material layer 411 on the first portion 211 of the substrate 21 and the first sacrificial layer 31 and a first support layer 412 on the first material layer 411 .

In one embodiment, the material of the first support layer 412 may include: semiconductor materials (eg, polysilicon, amorphous silicon, indium tin oxide, etc., or a combination of multiple semiconductor materials), insulating dielectric materials (eg, silicon oxide, nitrogen, etc.) Silicon oxide, silicon oxynitride, etc., or a combination of various insulating dielectric materials) or conductive metal materials (eg, aluminum, copper, titanium, titanium nitride, etc., or a combination of multiple metal materials).

In one embodiment, the thickness of the first support layer ranges from 100 nanometers to 100 micrometers. For example, the thickness of the first support layer may be 200 nanometers, 500 nanometers, 1 micrometer, 10 micrometers, or 50 micrometers.

Next, as shown in FIG. 16 , a first polishing process (eg, CMP) is performed on the first structure layer 41 (ie, the first support layer 412 and the first material layer 411 ) to expose the first sacrificial layer 31 . The first polishing process may remove portions of the first support layer 412 and the first material layer 411 on the top surface of the first sacrificial layer 31 . Of course, a part of the first sacrificial layer can also be removed by further polishing.

Next, as shown in FIG. 17 , the first sacrificial layer 31 is removed, for example, by a selective etching process to expose the upper surface of the second portion 212 of the substrate 21 and the side surface of the first structure layer 41 . In this step, as shown in FIG. 17 , the exposed side surface of the first structure layer 41 is the side surface of the first material layer 411 .

Next, as shown in FIG. 18 , using the first support layer 412 and the first material layer 411 as supports, a second sacrificial layer 32 is formed on a part of the upper surface of the second portion 212 of the substrate 21 , wherein the second sacrificial layer 32 is formed. Layer 32 covers the exposed sides of first structural layer 41 . In this step, the second sacrificial layer 32 covers the exposed side surface of the first material layer 411 .

Next, as shown in FIG. 19 , on the second portion 212 of the substrate 21 , the second sacrificial layer 32 and the first structural layer 41 (ie, the first material layer 411 and the first support layer 412 ), for example, by a deposition process A second material layer 421 is formed, and the second material layer 421 covers the side surface of the second sacrificial layer 32 .

In one embodiment, the material of the second material layer 421 may include: a metal material (eg, gold, platinum, silver, titanium, titanium nitride, etc. or a combination of multiple metal materials) or a semiconductor material (eg, polysilicon, Amorphous silicon, indium tin oxide, etc. or a combination of various semiconductor materials). In this embodiment, the second material layer can be a conductive material such as a metal material or a semiconductor material (for example, a doped semiconductor material), so that the second material layer can be used as one of the embedded electrode layers of the subsequently formed flow channel, which can Used in fluid processing or biochemical detection, etc.

In another embodiment, the material of the second material layer 421 may include an insulating dielectric material (eg, silicon oxide, silicon nitride, silicon oxynitride, etc., or a combination of multiple insulating dielectric materials). In this way, a flow channel formed of an insulating medium material can be formed in a subsequent step, which can be applied to fluid formation and control, and the like.

In one embodiment, the thickness of the second material layer 421 may range from 1 nm to 500 nm. For example, the thickness of the second material layer 421 may be 10 nanometers, 50 nanometers, 100 nanometers, or 300 nanometers.

Next, as shown in FIG. 20 , a second support layer 422 is formed on the second material layer 421 by, for example, a deposition process. The second support layer 422 can serve as a support layer for the second material layer 421 . So far, the second structure layer 42 is formed. The second structural layer 42 may include: a second material layer on the second portion 212 of the substrate 21 , the second sacrificial layer 32 and the first structural layer 41 (ie, the first material layer 411 and the first support layer 412 ) 421 and a second support layer 422 on the second material layer 421.

In one embodiment, the material of the second support layer 422 may include: semiconductor materials (eg, polysilicon, amorphous silicon, indium tin oxide, etc., or a combination of multiple semiconductor materials), insulating dielectric materials (eg, silicon oxide, Silicon nitride, silicon oxynitride, etc., or a combination of various insulating dielectric materials) or conductive metal materials (eg, aluminum, copper, titanium, titanium nitride, etc., or a combination of various metal materials).

In one embodiment, the thickness of the second support layer 422 may range from 100 nanometers to 100 micrometers. For example, the thickness of the second support layer may be 200 nanometers, 500 nanometers, 1 micrometer, 10 micrometers, or 50 micrometers.

Next, as shown in FIG. 21 , a second polishing process (eg, CMP) is performed on the second structure layer 42 (ie, the second support layer 422 and the second material layer 421 ) to expose the second sacrificial layer 32 . In addition, the second polishing process may also remove portions of the second material layer 421 and the second support layer 422 on the top surface of the first support layer 412 . As shown in FIG. 21 , in the step of performing the second polishing process, the first material layer 411 , the first support layer 412 , the second material layer 421 and the second support layer 422 are also exposed.

Next, as shown in FIG. 22 , the second sacrificial layer 32 is removed by a selective etching process to form the flow channel 50 .

So far, a method for fabricating a flow channel structure device according to another embodiment of the present invention is provided. In the flow channel structure device formed by the above manufacturing method, the first structure layer may include: a first material layer and a first support layer, wherein a part of the first material layer is between the first support layer and the flow channel, Another part of the first material layer is between the first support layer and the first part of the substrate; the second structural layer may include: a second material layer and a second support layer, wherein a part of the second material layer is in Between the second support layer and the flow channel, another part of the second material layer is between the second support layer and the second part of the substrate.

In the case where the material of the first material layer includes a conductive material such as a metal material or a semiconductor material (eg, a doped semiconductor material), the part of the first material layer between the first support layer and the flow channel can serve as the flow channel. For the first electrode of the channel structure device, the part of the first material layer between the first support layer and the first part of the substrate can be used as the first lead of the first electrode. In the case where the material of the second material layer includes a conductive material such as a metal material or a semiconductor material (eg, a doped semiconductor material), the part of the second material layer between the second support layer and the flow channel can serve as the flow channel. The second electrode of the channel structure device, the part of the second material layer between the second support layer and the second part of the substrate can be used as the second lead of the second electrode. Since the first material layer and the second material layer are integrally formed by, for example, a deposition process, respectively, compared with the prior art, the contact resistance between the first electrode and the first lead can be reduced, and the second electrode and the The contact resistance between the second leads can also be reduced, so that the device performance can be improved.

In addition, the above-mentioned manufacturing method of the embodiment of the present invention can reduce the thermal budget of the process. For example, the process temperature involved in the method of the present invention is relatively low (the temperature range is between room temperature and 350° C.), and the heat treatment process time is short, thus reducing the process thermal budget and facilitating the integration of the runner structure device and the CMOS chip.

Further, in the above manufacturing method, the thickness of the first sacrificial layer and the thickness of the second sacrificial layer can be determined according to design requirements, so a flow channel structure with a high aspect ratio can be realized.

From the above manufacturing method, a flow channel structure device is also formed. As shown in FIG. 22 , the flow channel structure device may include a substrate 21 , and the substrate 21 may include a first portion 211 and a second portion 212 adjacent to the first portion 211 . The flow channel structure device may further include: a first structure layer 41 and a second structure layer 42 on the substrate 21 . Wherein, the first structural layer 41 may include: a first material layer 411 on the first part 211 of the substrate 21 and a first supporting layer 412 on the first material layer 411, and the second structural layer 42 may include : a second material layer 421 on the second portion 212 of the substrate 21 and a second support layer 422 on the second material layer 421 . The flow channel structure device may further include: a flow channel 50 between the first material layer 411 and the second material layer 421 . The first support layer 421 and the second support layer 422 are respectively on two sides of the flow channel 50 . As shown in FIG. 22 , a part of the first material layer 411 is between the first support layer 412 and the flow channel 50 , and another part of the first material layer 411 is between the first support layer 412 and the substrate 21 . Between the first part 211; a part of the second material layer 421 is between the second support layer 422 and the flow channel 50, and another part of the second material layer 421 is between the second support layer 422 and the substrate 21 between the second part 212 .

The flow channel structure device of the above-mentioned embodiments of the present invention has vertical flow channels, for example, the flow channel can be open space in the direction perpendicular to the substrate or can be provided with transparent materials, so this will not affect the transmission of optical signals. In addition, by using vertical flow channels, the effective surface area of a single flow channel can be the cross-sectional area of the flow channel, which can greatly improve the manufacturing density of the flow channels on the chip, and can improve the application flux (ie, the number of flow channels per unit area), As well as reducing manufacturing and application costs, etc.

In one embodiment, the height of the flow channel 50 may range from 100 nanometers to 100 micrometers. For example, the height of the flow channel can be 500 nanometers, 1 micrometer, 10 micrometers, or 50 micrometers. In one embodiment, the width of the flow channel 50 may range from 0.1 nanometer to 1 micrometer. For example, the width of the flow channel can be 1 nanometer, 10 nanometers, 14 nanometers, 100 nanometers, or 500 nanometers. After selecting the appropriate height and width of the flow channel, the flow channel structure device can realize the flow channel structure with high aspect ratio.

In one embodiment, the thickness of the first material layer 411 may range from 1 nanometer to 500 nanometers. In one embodiment, the thickness of the first support layer 412 may range from 100 nanometers to 100 micrometers. In one embodiment, the thickness of the second material layer 421 may range from 1 nm to 500 nm. In one embodiment, the thickness of the second support layer 422 may range from 100 nanometers to 100 micrometers.

In one embodiment, the material of the first material layer 411 may include: a metal material or a semiconductor material (eg, a doped semiconductor material). The part of the first material layer 411 between the first support layer 412 and the flow channel 50 can be used as the first electrode of the flow channel structure device; the part of the first material layer 411 between the first support layer 412 and the base The part between the first parts 211 of the sheet 21 can serve as the first lead of the first electrode. In one embodiment, the material of the second material layer 412 may include: a metal material or a semiconductor material (eg, a doped semiconductor material). The part of the second material layer 412 between the second support layer 422 and the flow channel 50 can be used as the second electrode of the flow channel structure device; the part of the second material layer 421 between the second support layer 422 and the base The portion between the second portions 212 of the sheet 21 may serve as the second lead of the second electrode. In this embodiment, since the first material layer and the second material layer are integrally formed, respectively, compared with the prior art, the contact resistance between the first electrode and the first lead can be reduced, and the second electrode and the second lead can be reduced. Contact resistance between leads can also be reduced, which can improve device performance.

In the above-mentioned embodiment, the above-mentioned flow channel structure device may have a damascene electrode structure, and may have different biochemical analysis and fluid processing functions. For example, by applying electrical excitation through electrodes, an electrical or electrochemical reaction can occur in the flow channel, an electrical signal or an optical signal can be generated, and a specific molecular species can be identified through the obtained electrical or optical signal; further, by identifying a variety of Different molecular species can realize functions such as gene sequencing.

In another embodiment, the materials of the first material layer 411 and the material of the second material layer 421 may respectively include: insulating dielectric materials (eg, silicon oxide, silicon nitride, silicon oxynitride, etc. or a plurality of insulating dielectric materials). combination). Such a flow channel formed of an insulating medium material can be applied to the formation and control of fluid, and the like. For example, by using an insulating dielectric material as the first material layer and the second material layer, the flow channel structure device can be applied to some situations that do not require the application of electrodes in the flow channel, for example, in some cases, it is necessary to use a specific insulating medium material. As a material layer, the surface of the flow channel is modified to obtain some specific effects, such as obtaining a hydrophobic surface or a hydrophilic surface, etc., which is beneficial to the formation and control of the fluid.

23 and 24 are cross-sectional views schematically showing structures of several stages in a manufacturing process of a flow channel structure device according to another embodiment of the present invention. The manufacturing process of the flow channel structure device according to another embodiment of the present invention will be described in detail below with reference to FIG. 23 and FIG. 24 .

In one embodiment, before the second sacrificial layer is removed by the selective etching process and after the second polishing process is performed, the manufacturing method may further include: in the second sacrificial layer 32, the first material layer 411, the first A cap layer 60 is formed on a support layer 412 , the second material layer 421 and the second support layer 422 . In the subsequent step of forming the flow channel, the capping layer may be together with the first structural layer (which may include the first material layer and the first supporting layer) and the second structural layer (which may include the second material layer and the second supporting layer) By realizing the closed flow channel structure, parasitic reactions that may be caused by the contact between the tops of the first material layer and the second material layer and the fluid can also be avoided. Furthermore, for some applications that require the flow of fluids (eg, liquids) in the flow channel, the flow channel covered with the capping layer of this embodiment makes it easier to control the flow of these fluids.

In one embodiment, similar to the foregoing, in the step of removing the second sacrificial layer by a selective etching process, a selective etching solution may be injected from the edge of the second sacrificial layer to remove the second sacrificial layer, Thus, a flow channel structure device as shown in FIG. 24 is formed. In the actual planar structure, the planar extending second sacrificial layer is bounded, and the edge of the second sacrificial layer can be exposed, so a selective etchant is injected at the edge (ie, the boundary) of the second sacrificial layer to remove The second sacrificial layer, thereby forming the flow channel.

In another embodiment, similar to the foregoing, before removing the second sacrificial layer by a selective etching process, the manufacturing method may further include: etching the capping layer to form the first capping layer penetrating the capping layer and exposing the second sacrificial layer. Two through holes of the sacrificial layer (not shown in FIG. 24 , you can refer to the through holes 61 in FIG. 12 ). Wherein, in the step of removing the second sacrificial layer by a selective etching process, a selective etching solution may be injected from the through hole to remove the second sacrificial layer, thereby forming a flow channel structure device as shown in FIG. 24 . In this embodiment, by forming a through hole on the cap layer, in the selective etching process, it is favorable for the selective etching solution to pass through the through hole to remove the second sacrificial layer, and the etching rate can be accelerated.

From the above-described manufacturing method, a flow channel structure device according to another embodiment of the present invention is also formed. As shown in FIG. 24 , the flow channel structure device may include the same or similar structure as that shown in FIG. 22 , for example, may include: a substrate 21 , a first material layer 411 , a first support layer 412 , a second material layer 421 , a second The support layer 422 and the flow channel 50 are not described in detail here.

In one embodiment, as shown in FIG. 24 , the flow channel structure device may further include: a cap layer covering the first material layer 411 , the first support layer 412 , the second material layer 421 and the second support layer 422 60. Wherein, the cap layer 60 covers the flow channel 50 . The capping layer 60 can achieve sealing together with the first structural layer 41 (which may include the first material layer 411 and the first support layer 412 ) and the second structural layer 42 (which may include the second material layer 421 and the second support layer 422 ) The flow channel (that is, the upper part of the flow channel is closed) can also avoid parasitic reactions that may be caused by the contact between the upper surfaces of the first structural layer 41 and the second structural layer 42 and the fluid. Furthermore, for some applications that require the flow of fluids (eg, liquids) in the flow channel, the flow channel covered with the capping layer of this embodiment makes it easier to control the flow of these fluids.

In one embodiment, the material of the capping layer 60 may include: insulating dielectric materials (eg, silicon oxide, silicon nitride, silicon oxynitride, borophosphosilicate glass, aluminum oxide, titanium oxide or tantalum oxide, etc.) or semiconductor materials (eg, polysilicon or amorphous silicon, etc.).

In one embodiment, the thickness of the capping layer 60 may range from 1 nanometer to 10 micrometers. For example, the thickness of the capping layer may be 10 nanometers, 100 nanometers, 500 nanometers, 1 micrometer, or 5 micrometers.

In one embodiment, the flow channel structure device may further include: a through hole penetrating the cap layer and communicating with the flow channel.

Thus far, fabrication methods according to some embodiments of the present invention and flow channel structure devices formed by these fabrication methods have been provided. The flow channel of the embodiment of the present invention may be a nano-flow channel. The invention has the following advantages: (1) a nano-channel structure with a high aspect ratio can be realized, and the size controllability is good; (2) an all-metal conductive electrode mosaic structure can be realized; (3) the controllability of the nano-channel structure can be effectively improved manufacturability, reducing the manufacturing cost of the nano-channel structure; (4) having a relatively low thermal budget, which can be compatible with integrated circuit processes. In addition, the flow channel structure device of the embodiment of the present invention can be applied in molecular detection, liquid formation or fluid transport control and the like.

In an embodiment of the present invention, a flow channel sensor can also be provided. The flow channel sensor may include: a flow channel structure device as previously described (eg, a flow channel structure device as shown in FIG. 22 or FIG. 24 ).

In one embodiment of the present invention, a biochemical analysis device can also be provided. The biochemical analysis device may include: a flow channel structure device as previously described (eg, a flow channel structure device as shown in FIG. 22 or FIG. 24 ).

FIG. 25 is a structural diagram schematically showing a chip for molecular detection according to an embodiment of the present invention. As shown in FIG. 25 , the chip 250 may include: a flow channel structure device 2501 , a signal collection unit 2502 and a signal processing unit 2503 . The flow channel structure device 2501 includes electrodes (eg, a first electrode and a second electrode). For example, the flow channel structure device may be the flow channel structure device shown in FIG. 22 or FIG. 24 . Wherein, the sample to be detected is added into the flow channel of the flow channel structure device, and the target molecules in the sample to be detected under the condition that the electrodes (for example, the first electrode and the second electrode) of the flow channel structure device are applied with electrical excitation Under the action of electrical excitation, electrical or optical signals are generated.

The signal collecting unit 2502 can be used to collect the electrical signal or the optical signal, and transmit the electrical signal or the optical signal to the signal processing unit 2503 .

The signal processing unit 2503 can be used to perform signal processing on the electrical signal or the optical signal to identify the information of the target molecule.

In an embodiment of the present invention, a molecular detection method is also provided. The method may include molecular detection using a chip as previously described (eg, the chip shown in Figure 25).

Figure 26 is a flow chart illustrating a molecular detection method according to one embodiment of the present invention. The steps of molecular detection using the chip will be described below with reference to FIG. 26 .

In step S2601, the sample to be detected is processed. For example, the sample to be tested may be chemically or otherwise treated.

In step S2602, the sample to be detected is added to the chip. For example, the sample to be detected is added into the flow channel of the flow channel structure device of the chip.

In step S2603, electrical excitation is applied to the electrodes (eg, the first electrode and the second electrode) in the flow channel structure device in the chip, so that the target molecules in the sample to be detected generate electrical or optical signals under the action of electrical excitation.

In step S2604, the signal processing unit of the chip obtains the electrical signal or the optical signal through the signal collection unit, and performs signal processing on the electrical signal or the optical signal to identify the information of the target molecule.

In the above-mentioned embodiments, the application of molecular detection is realized by using the chip including the flow channel structure device of the embodiment of the present invention.

So far, the present invention has been described in detail. Some details that are well known in the art have not been described in order to avoid obscuring the concept of the present invention. Those skilled in the art can fully understand how to implement the technical solutions disclosed herein based on the above description.

While some specific embodiments of the present invention have been described in detail by way of example, those skilled in the art will appreciate that the above examples are provided for illustration only and not for the purpose of limiting the scope of the invention. Those skilled in the art will appreciate that modifications may be made to the above embodiments without departing from the scope and spirit of the present invention. The scope of the invention is defined by the appended claims.

Claims (27)

1. a manufacturing method of a flow channel structure device is characterized in that, comprising: providing a substrate including a first portion and a second portion adjacent to the first portion; forming a patterned first sacrificial layer on the substrate, the first sacrificial layer covering the second part and exposing the first part; forming a first structural layer on the first portion of the substrate and the first sacrificial layer; after forming the first structural layer, performing a first polishing process to expose the first sacrificial layer; removing the first sacrificial layer to expose the upper surface of the second portion of the substrate and the sides of the first structural layer; forming a second sacrificial layer on a portion of the upper surface of the second portion of the substrate, wherein the second sacrificial layer covers the exposed side of the first structural layer; forming a second structural layer on the second portion of the substrate, the second sacrificial layer and the first structural layer; after forming the second structural layer, performing a second polishing process to expose the second sacrificial layer; and The second sacrificial layer is removed by a selective etching process to form flow channels. 2. The manufacturing method according to claim 1, characterized in that, In the step of performing the second polishing process, the first structural layer and the second structural layer are also exposed; Before removing the second sacrificial layer using a selective etching process, the method further includes: forming a capping layer on the second sacrificial layer, the first structure layer and the second structure layer. 3. The manufacturing method according to claim 1, characterized in that, The step of forming the first structural layer includes: forming a first material layer on the first portion of the substrate and the first sacrificial layer, wherein the first material layer covers a side surface of the first sacrificial layer; and forming a first support layer on the first material layer; wherein the first structure layer includes: the first material layer and the first support layer; The step of forming the second structural layer includes: forming a second material layer on the second portion of the substrate, the second sacrificial layer and the first structural layer, the second material layer covering the a side surface of the second sacrificial layer; and forming a second support layer on the second material layer; wherein the second structure layer includes: the second material layer and the second support layer. 4. The manufacturing method according to claim 3, characterized in that, In the step of removing the first sacrificial layer to expose the side surface of the first structure layer, the exposed side surface of the first structure layer is the side surface of the first material layer; In the step of forming the second sacrificial layer, the second sacrificial layer covers the exposed side surface of the first material layer. 5. The manufacturing method according to claim 3, characterized in that, In the step of performing the second polishing process, the first material layer, the first support layer, the second material layer and the second support layer are also exposed; Before removing the second sacrificial layer by a selective etching process, the method further includes: in the second sacrificial layer, the first material layer, the first support layer, the second material layer and forming a cap layer on the second support layer. 6. The manufacturing method according to claim 2 or 5, characterized in that, The material of the cap layer includes: insulating dielectric material or semiconductor material; The capping layer has a thickness ranging from 1 nanometer to 10 micrometers. 7. The manufacturing method according to claim 2 or 5, characterized in that, In the step of removing the second sacrificial layer by a selective etching process, a selective etching solution is injected from the edge of the second sacrificial layer to remove the second sacrificial layer. 8. The manufacturing method according to claim 2 or 5, characterized in that, Before removing the second sacrificial layer by a selective etching process, the method further includes: etching the capping layer to form a through hole penetrating the capping layer and exposing the second sacrificial layer; Wherein, in the step of removing the second sacrificial layer by a selective etching process, a selective etching solution is injected from the through hole to remove the second sacrificial layer. 9. The manufacturing method according to claim 3, characterized in that, A part of the first material layer is between the first support layer and the flow channel, and another part of the first material layer is between the first support layer and the first part of the substrate; A portion of the second material layer is between the second support layer and the flow channel, and another portion of the second material layer is between the second support layer and the second portion of the substrate . 10. The manufacturing method according to claim 9, characterized in that, The material of the first material layer includes: metal material or semiconductor material; The material of the second material layer includes: metal material or semiconductor material; The part of the first material layer between the first support layer and the flow channel serves as the first electrode of the flow channel structure device; the part of the first material layer between the first support layer and the flow channel is used as the first electrode of the flow channel structure device; The part between the layer and the first part of the substrate serves as the first lead of the first electrode; the part of the second material layer between the second support layer and the flow channel serves as the first lead of the first electrode; The second electrode of the flow channel structure device; the part of the second material layer between the second support layer and the second part of the substrate serves as the second lead of the second electrode. 11. The manufacturing method according to claim 3, wherein, The material of the first material layer and the material of the second material layer respectively include: insulating dielectric material. 12. The manufacturing method according to claim 1, wherein, The thickness of the first sacrificial layer is determined according to the required height of the flow channel; The thickness of the first sacrificial layer ranges from 100 nanometers to 100 micrometers. 13. The manufacturing method according to claim 1, wherein, The thickness of the second sacrificial layer is determined according to the required width of the flow channel; The thickness of the second sacrificial layer ranges from 0.1 nanometer to 1 micrometer. 14. The manufacturing method according to claim 3, characterized in that, The thickness of the first material layer ranges from 1 nanometer to 500 nanometers; The thickness of the first support layer ranges from 100 nanometers to 100 micrometers; The thickness of the second material layer ranges from 1 nanometer to 500 nanometers; The thickness of the second support layer ranges from 100 nanometers to 100 micrometers. 15. A flow channel structure device formed by the manufacturing method according to claim 9, characterized in that, comprising: a substrate comprising a first portion and a second portion adjacent to the first portion; A first structural layer and a second structural layer on the substrate; wherein the first structural layer comprises: a first material layer on a first portion of the substrate and a first material layer on the first material layer a first support layer, the second structural layer comprising: a second material layer on the second portion of the substrate and a second support layer on the second material layer; a flow channel between the first material layer and the second material layer; the first support layer and the second support layer are respectively on both sides of the flow channel; Wherein, a part of the first material layer is between the first support layer and the flow channel, and another part of the first material layer is between the first support layer and the first part of the substrate A part of the second material layer is between the second support layer and the flow channel, and another part of the second material layer is between the second support layer and the second part of the substrate between. 16. The flow channel structure device of claim 15, further comprising: A cap layer covering the first material layer, the first support layer, the second material layer and the second support layer; wherein the cap layer covers the flow channel. 17. The flow channel structure device according to claim 16, wherein, The material of the cap layer includes: insulating dielectric material or semiconductor material; The capping layer has a thickness ranging from 1 nanometer to 10 micrometers. 18. The flow channel structure device of claim 16, further comprising: A through hole passing through the cap layer and communicating with the flow channel. 19. The flow channel structure device according to claim 15, wherein, The material of the first material layer includes: metal material or semiconductor material; The material of the second material layer includes: metal material or semiconductor material; The part of the first material layer between the first support layer and the flow channel serves as the first electrode of the flow channel structure device; the part of the first material layer between the first support layer and the flow channel is used as the first electrode of the flow channel structure device; The part between the layer and the first part of the substrate serves as the first lead of the first electrode; the part of the second material layer between the second support layer and the flow channel serves as the first lead of the first electrode; The second electrode of the flow channel structure device; the part of the second material layer between the second support layer and the second part of the substrate serves as the second lead of the second electrode. 20. The flow channel structure device according to claim 15, wherein, The material of the first material layer and the material of the second material layer respectively include: insulating dielectric material. 21. The flow channel structure device according to claim 15, wherein, The height of the flow channel ranges from 100 nanometers to 100 micrometers; The width of the flow channel ranges from 0.1 nanometer to 1 micrometer. 22. The flow channel structure device according to claim 15, wherein, The thickness of the first material layer ranges from 1 nanometer to 500 nanometers; The thickness of the first support layer ranges from 100 nanometers to 100 micrometers; The thickness of the second material layer ranges from 1 nanometer to 500 nanometers; The thickness of the second support layer ranges from 100 nanometers to 100 micrometers. 23. A flow channel sensor, characterized by comprising: the flow channel structure device according to any one of claims 15 to 22. 24. A biochemical analysis device, comprising: the flow channel structure device according to any one of claims 15 to 22. 25. A chip for molecular detection, comprising: a flow channel structure device as claimed in claim 19, a signal collection unit and a signal processing unit; The sample to be detected is added into the flow channel of the flow channel structure device, and the target molecules in the sample to be detected generate electricity under the action of electrical excitation when the electrodes of the flow channel structure device are electrically excited. signal or optical signal; The signal collecting unit is used for collecting the electrical signal or the optical signal, and transmitting the electrical signal or the optical signal to the signal processing unit; The signal processing unit is configured to perform signal processing on the electrical signal or the optical signal to identify the information of the target molecule. 26. A molecular detection method, comprising: using the chip of claim 25 for molecular detection. 27. The molecular detection method according to claim 26, wherein the step of using the chip for molecular detection comprises: processing the samples to be tested; adding the sample to be detected into the chip; Applying electrical excitation to the electrodes in the flow channel structure device in the chip, so that the target molecule in the sample to be detected generates an electrical signal or an optical signal under the action of the electrical excitation; and The signal processing unit of the chip obtains the electrical signal or the optical signal through the signal collection unit, and performs signal processing on the electrical signal or the optical signal to identify the information of the target molecule.

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