CN110797340A - Semiconductor memory device with a memory cell having a plurality of memory cells - Google Patents

Abstract

The present invention provides a semiconductor memory structure, comprising: a substrate, a word line, a bit line contact and a bit line, wherein a through trench is formed between two adjacent word lines, and the trench includes a contact window and a groove between the windows. The recess has a re-recessed surface relative to the contact window, and the re-recessed depth is between 5.8 nm and 8.5 nm, so that the adjacent bit line contacts are not electrically connected to each other; in the extension direction of the word line, the side etching of the bit line contact The sum of the depths is proportional to the re-recess depth of the grooves between the windows. The present invention also provides another semiconductor memory structure, wherein the contact window in the trench has a re-concave surface relative to the groove between the windows, and the re-concave surface is lower than the surface of the isolation structure in the trench; in the extension direction of the word line , the bit line contact has a vertical cut profile. The invention effectively solves the problem of serious side etching of the bit line contact caused by the formation of the relatively low re-recessed surface of the groove between the windows by controlling the ratio of the etchant gas or selecting different etchants.

Description

semiconductor memory

technical field

The present invention relates to the field of semiconductor integrated circuits, in particular to a structure of a semiconductor storage device and a manufacturing method thereof.

Background technique

A semiconductor memory generally includes a plurality of memory cells and word lines and bit lines connected to the memory cells. During the manufacturing process of the bit line, it is necessary to over-etch the protective layer between two adjacent word lines and completely expose the underlying active region and isolation structure, so as to form the bit line contact window. The etching of the protective layer, the active region and the isolation structure is usually done together with the same etchant. Due to the difference in etching selectivity between the active region (eg Si) and the isolation structure (eg SiO ₂ ) of the etchant, trenches are easily formed on the surface of the isolation structure. When the trench is deep, more bit line contact layer material will be filled in the trench when the subsequent bit line contact layer (such as polysilicon) is deposited, and then when the bit line contact layer is etched to form the bit line contact, Bit line contact residues are easily generated in the trench, which indirectly leads to short circuits between adjacent bit line contacts. On the other hand, in order to prevent the short circuit from continuing to etch, serious side etching of the bit line contact itself will be caused, which will increase the resistance of the bit line and the active region and affect the fast response performance of the memory. It can be seen that the deeper the trench is, the greater the possibility of generating bit line contact residue and severe side etching of the bit line contact. Especially for bit lines with a narrow width of 20 nm, the influence of the above phenomenon is particularly prominent.

Therefore, how to reduce the depth of the groove or how to control the depth of the groove within an acceptable range is a technical problem that needs to be solved in the field of memory bit line manufacturing.

SUMMARY OF THE INVENTION

The main purpose of the present application is to provide a method for manufacturing a memory bit line and a structure thereof, so as to solve or alleviate one or more technical problems in the prior art, and at least provide a beneficial option.

In order to achieve the above object, according to one aspect of the present application, a semiconductor memory structure is provided, comprising:

a substrate, a plurality of active regions spaced apart from each other are defined by an upper surface of the substrate;

an isolation structure formed in the substrate and insulating the active regions from each other;

The word lines are embedded in the substrate and are laid in parallel along the extension direction of the word lines so as to intersect the active region and the isolation structure, and two adjacent word lines are formed with a through trench intersecting an intermediate region of the active region, a portion of the trench on the active region including a contact window recessed from an upper surface of the active region for overlapping a bit line; and

a bit line contact formed on the active region in the contact window;

Wherein, the part of the trench on the isolation structure includes an inter-window groove recessed from the upper surface of the isolation structure, and the inter-window groove has a re-concave surface relative to the contact window, which is lower than the On the surface of the active region in the trench, the depth from the lowest point of the recess between the windows to the surface of the active region in the trench is between 5.8 nm and 8.5 nm, so that the A plurality of adjacent said bit line contacts are not electrically connected to each other.

Further, the semiconductor memory structure also includes:

a bit line, formed on the substrate and in a continuous wave shape, the bit line contact is electrically connected between the staggered parts of the bit line and the active region;

Wherein, the two sidewalls formed by the bit line contact along the extension direction of the bit line have a cut-out shape that is undercut in the extension direction of the word line.

In some embodiments, the ratio of the sum of the undercut depths of the two sidewalls of the bit line contact in the extension direction of the word line to the top width of the bit line contact ranges from 25% to 25%. 50%.

In some implementation manners, the sum of the undercut depths of the two sidewalls cut along the extension direction of the word line of the bit line contact is proportional to the re-recessed depth of the recess between the windows.

In some embodiments, corresponding to the maximum value of the re-recessed depth of the recess between the windows of 8.5 nm, the maximum value of the sum of the undercut depths of the two sidewalls of the bit line contact is the maximum value of the bit line contact. 50% of the top width.

In some embodiments, the memory structure further includes:

A protective layer covers the surface of the active region and the isolation structure except the trench region, and the bit line is stacked on the protective layer and the contact of the bit line.

In some embodiments, the trench is formed by etching a portion of the protective layer between two adjacent word lines, and the depth of the contact window is formed in the trench by etching the active region. The depth of the groove between the windows is formed by etching the part of the isolation structure in the trench;

Wherein, the etchant for etching the protective layer, the active region and the isolation structure includes trifluoromethane and carbon tetrafluoride, and the ratio of the trifluoromethane to the carbon tetrafluoride ranges between 0.5～1.6;

The etching selectivity ratio of the etchant to the isolation structure and the active region ranges from 1.1 to 2.3, and decreases as the ratio of the trifluoromethane to the carbon tetrafluoride increases;

The depth of the groove between the windows decreases as the ratio of the trifluoromethane to the carbon tetrafluoride increases.

According to a second aspect of the present application, another semiconductor memory structure is provided, comprising:

a substrate, a plurality of active regions spaced apart from each other are defined by an upper surface of the substrate;

an isolation structure formed in the substrate and insulating the active regions from each other;

The word lines are embedded in the substrate and are laid in parallel along the extension direction of the word lines so as to intersect the active region and the isolation structure, and two adjacent word lines are formed with a through trench intersecting a middle region of the active region, the trench including a contact window recessed from an upper surface of the active region; and

a bit line contact formed on the active region in the contact window;

Wherein, the trench further includes an inter-window groove of the isolation structure between the active regions, and the contact window window has a re-concave surface relative to the inter-window groove, so that the groove is in the trench. A plurality of adjacent said bit line contacts are not electrically connected to each other.

Further, the semiconductor memory structure also includes:

a bit line, formed on the substrate and in a continuous wave shape, the bit line contact is electrically connected between the staggered parts of the bit line and the active region;

Wherein, the two sidewalls formed by the bit line contact along the extension direction of the bit line have a cross-sectional shape perpendicular to the extension direction of the word line.

In some implementations, the memory structure further includes:

A protective layer covers the surface of the active region and the isolation structure except the trench region, and the bit line is stacked on the protective layer and the contact of the bit line.

In some embodiments, the trench is formed by etching a portion of the protective layer between two adjacent word lines, and the depth of the contact window is formed by etching the active region in the forming part of the trench, the depth of the groove between the windows is formed by etching the part of the isolation structure in the trench;

Wherein, the etchant for etching the protective layer includes carbon tetrafluoride, fluoromethane and oxygen, and the ratio of the carbon tetrafluoride, the fluoromethane and the oxygen ranges from (40 to 50): ( 10～24):(30～48);

The etchant for etching the active region and the isolation structure includes chlorine gas and/or hydrogen bromide gas, wherein the ratio of the chlorine gas and the hydrogen bromide gas includes 1:1.

In the semiconductor memory structure provided by the embodiment of the present invention, by controlling the proportion of the etching gas, the re-recessed depth of the groove between the windows in the trench is reduced, and the excessive filling of the bit line contact material into the re-recessed area is prevented to solve the problem. In the subsequent bit line contact etching process, due to the residual bit line contact material in the re-recessed region, the short circuit between the bit line contacts and the serious side etching of the bit line contacts are caused. In addition, in the semiconductor memory structure provided by another embodiment of the present invention, the surface of the recess between the windows in the trench is higher than the re-recessed surface of the contact window, thereby effectively avoiding the above-mentioned short circuit between the bit line contacts and side-to-side contact. the occurrence of the erosion problem.

The above summary is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments and features described above, further aspects, embodiments and features of the present invention will be readily understood by reference to the drawings and the following detailed description.

Description of drawings

In the drawings, unless stated otherwise, the same reference numbers refer to the same or like parts or elements throughout the several figures. The drawings are not necessarily to scale. It should be understood that these drawings depict only some embodiments according to the disclosure and should not be considered as limiting the scope of the invention.

1a is a top view of a semiconductor memory structure according to an embodiment of the present invention;

Figure 1b is a cross-sectional view along line A-A in Figure 1a;

Figure 1c is a cross-sectional view taken along line B-B in Figure 1a;

Figure 1d is a cross-sectional view along line C-C in Figure 1a;

Fig. 2 is the relation diagram of STI groove depth and bit line contact undercut;

3 is a graph showing the relationship between the ratio of the trench etchant trifluoromethane and carbon tetrafluoride gas, the SiO ₂ /Si etching selectivity ratio, and the depth of the STI groove;

4a is a top view of a structure of a semiconductor memory according to another embodiment of the present invention;

Figure 4b is a cross-sectional view along line A-A in Figure 4a;

Figure 4c is a cross-sectional view along line B-B in Figure 4a;

Figure 4d is a cross-sectional view along line C-C in Figure 4a;

5a is a top view of the semiconductor memory structure shown in FIG. 1 after an active region and an isolation structure are formed in a substrate;

Figure 5b is a cross-sectional view along line C-C in Figure 5a;

6a is a top view of the semiconductor memory structure shown in FIG. 1 after word lines are formed in the substrate and a protective layer is deposited on the surface;

Figure 6b is a cross-sectional view along line A-A in Figure 6a;

Figure 6c is a cross-sectional view along line B-B in Figure 6a;

Figure 6d is a cross-sectional view along line C-C in Figure 6a;

7a is a top view of the semiconductor memory structure shown in FIG. 1 after forming a through trench;

Figure 7b is a cross-sectional view along line A-A in Figure 7a;

Figure 7c is a cross-sectional view taken along line B-B in Figure 7a;

Figure 7d is a cross-sectional view along line C-C in Figure 7a;

8a is a top view of the semiconductor memory structure shown in FIG. 1 after depositing a bit line contact material in a through trench;

Figure 8b is a cross-sectional view along line A-A in Figure 8a;

Figure 8c is a cross-sectional view taken along line B-B in Figure 8a;

Figure 8d is a cross-sectional view along line C-C in Figure 8a;

9a is a top view of the semiconductor memory structure shown in FIG. 1 after depositing a bit line material and forming a barrier layer on the surface of the protective layer and the bit line contact material;

Figure 9b is a cross-sectional view along line A-A in Figure 9a;

Figure 9c is a cross-sectional view taken along line B-B in Figure 9a;

Figure 9d is a cross-sectional view along line C-C in Figure 9a;

FIG. 10a is a top view of the semiconductor memory structure shown in FIG. 1 after etching the bit line material and the bit line contact material using the barrier layer;

Figure 10b is a cross-sectional view along line A-A in Figure 10a;

Figure 10c is a cross-sectional view along line B-B in Figure 10a;

Figure 10d is a cross-sectional view along line C-C in Figure 10a;

Description of reference numbers:

Embodiment 1 of the present invention :

200: the semiconductor memory structure of the present invention;

210: substrate;

211: active area;

211A, 211B, 211C: source and drain regions;

212: isolation structure;

213: ditches;

213A: Contact window;

213B: groove between windows;

213Aa: the surface of the active area in the contact window;

213Ba: Re-concave surface of grooves between windows;

220: word line;

221: the insulating layer of the word line;

222: the barrier layer of the word line;

223: conductor layer of the word line;

230: bit line contact;

230A: sidewall of the bit line contact;

240: bit line;

241: the barrier layer of the bit line;

242: conductor layer of the bit line;

250: protective layer;

260: A first barrier layer.

Embodiment 2 of the present invention :

300: the semiconductor memory structure of the present invention;

311: active area;

311A, 311B, 311C: source and drain regions;

312: isolation structure;

313: ditches;

313A: Contact window;

313B: groove between windows;

313Aa: Re-concave surface of the contact window;

313Ba: the surface of the isolation structure in the groove between the windows;

330: bit line contact;

330A: Sidewall of the bit line contact.

Manufacturing method of the structure of Embodiment 1 of the present invention

270: the second barrier layer;

P100: bit line contact material;

P200: bit line barrier material;

P300: bit line conductor layer material;

P400: first barrier layer material;

P500: the second barrier layer material;

a: Bit line contact top width;

b: width of the narrowest part of the bit line contact line

c: Re-recessed depth of grooves between windows.

Detailed ways

In the following, only certain exemplary embodiments are briefly described. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not restrictive.

As described in the background art, due to the deep groove of the isolation structure, the problems of residual bit line contact and serious side etching of the bit line contact are likely to occur. To solve the above technical problems, embodiments of the present invention provide a semiconductor memory structure.

The structure of the semiconductor memory device and the manufacturing method thereof according to one embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

Embodiment 1

The present invention provides a semiconductor memory structure including: a substrate 210, a word line 220, a bit line contact 230, a bit line 240, a protective layer 250 and a first barrier layer 260, as shown in Figures 1a-1d.

The upper surface of the substrate 210 defines a plurality of active regions 211, the active regions 211 are spaced apart from each other to form an active region array, and the active regions 211 are formed on the surface of the substrate 210 and do not penetrate the substrate 210, as shown in FIG. 1a , 1b. In one embodiment, the material of the active region 211 includes doped Si.

An isolation structure 212 is provided between the active regions 211 , and the isolation structure 212 is formed in the substrate 210 and insulates the active regions 211 from each other, as shown in FIGS. 1 a and 1 c . In one embodiment, the isolation structure 212 may be Shallow Trench Isolation (STI), and the isolation material includes silicon dioxide (SiO ₂ ).

The word lines 220 are embedded in the substrate 210 and laid along the extending direction of the word lines 220 to intersect with the plurality of active regions 211 and the isolation structures 212 . The word lines 220 are parallel to each other and intersect the active regions 211 at a certain angle. And a single active region 211 intersects with two word lines 220, and two adjacent word lines 220 divide the single active region 211 into three source-drain regions 211A, 211B and 211C, see FIGS. 1a and 1b. The word line 220 includes an insulating layer 221, a blocking layer 222, a seed layer (not shown) and a conductor layer 223 in sequence from the sidewall to the central axis, as shown in FIG. 1b. In one embodiment, the material of the insulating layer 221 includes silicon dioxide, the material of the insulating layer 222 includes titanium (Ti) or titanium nitride (TiN), the material of the conductor layer 223 includes metal tungsten (W), the seed layer and the conductor The material of layer 223 is the same.

A through trench 213 intersecting the middle region of the active region 211 is formed between two adjacent word lines 220, and the trench 213 passes through the plurality of source and drain regions 211A and the isolation structure 212, as shown in FIG. 1a. The portion of the trench 213 on the source-drain region 211A includes a contact window 213A recessed from the upper surface of the source-drain region 211A to overlap the bit line 240; The upper surface of the inter-window groove 213B is concave, and the inter-window groove 213B has a re-concave surface 213Ba relative to the contact window 213A, and the re-concave surface 213Ba of the inter-window groove 213B is lower than the source-drain in the trench 213 The surface 213Aa of the electrode region 211A, the re-recessed surface 213Ba of the recess 213B between the windows and the surface 213Aa of the source and drain regions 211A are all lower than the surfaces of the active region 211 and the isolation structure 212 outside the trench 213, as shown in FIGS. 1b and 1c shown. In one embodiment, the re-concave surface 213Ba of the inter-window groove 213B is shaped as a concave arc, as shown in FIG. 1c. In one embodiment, the depth range from the lowest point of the recess 213B between the windows to the surface 213Aa of the source-drain region 211A in the trench 213 ranges from 5.8 nm to 8.5 nm, so that a plurality of adjacent bit lines in the trench 213 are formed. Contacts 230 are not electrically connected to each other. A bit line contact 230 is formed on the source-drain region 211A in the contact window 213A and does not completely fill the contact window 213A, as shown in FIG. 1b. The bit line contact 230 is used to realize electrical connection between the bit line 240 and the source and drain regions 211A. In one embodiment, the sidewalls of the contact windows 213A are not in contact with the sidewalls of the word lines 220 . The bit line contacts 230 are formed by deposition such as CVD or PVD. In one embodiment, the material of the bit line contact 230 includes polysilicon (Poly-Si).

The bit lines 240 are formed on the substrate 210 and extend in a continuous wave shape, and are regularly arranged at certain intervals. A single bit line 240 is interlaced with a plurality of active regions 211 and a plurality of word lines 220, as shown in the figure. 1a. The bit line contact 230 is electrically connected between the intersecting parts of the bit line 240 and the active region 211 , see FIGS. 1 a and 1 b ; the two sidewalls 230A of the bit line contact 230 formed along the extending direction of the bit line 240 are formed on the word line 220 See Figure 1d for a vertical section profile in the direction of extension. The bit line 240 may be a multi-layer composite structure. In one embodiment, the bit line 240 includes a titanium nitride layer, a metal tungsten layer, and the like in sequence away from the bit line contact 230 .

In one embodiment, a protective layer 250 is further deposited on the surface of the active region 211 , the isolation structure 212 and the word line 220 outside the trench 213 region to protect and insulate the surface of the active region 211 and the word line 220 . The bit line 240 is stacked on the passivation layer 250 and the bit line contact 230 . In one embodiment, the material of the protective layer 250 includes silicon nitride (Si ₃ N ₄ ) or the like. The trench 213 is formed by etching the portion of the protective layer 250 between two adjacent word lines 220, the depth of the contact window 213A is formed by etching the portion of the active region 211 in the trench 213, the recess 213B between the windows is formed The depth is formed by etching the portion of the isolation structure 212 in the trench 213 .

In one embodiment, the surface of the bit line 240 is also covered with a first barrier layer 260, and its main function is to insulate the surface of the bit line; The barrier layer 260 can be used as a hard mask to etch the bit line material and the bit line contact material. In another embodiment, a second barrier layer 270 is further formed on the first barrier layer 260, and together with the first barrier layer 260, serves as a hard mask for etching the bit line material and the bit line contact material. In one embodiment, the material of the first barrier layer 260 includes silicon nitride, and the material of the second barrier layer 270 includes silicon dioxide.

The two sidewalls 230A of the bit line contact 230 formed along the extension direction of the bit line 240 have a cut-out shape that is undercut in the extension direction of the word line 220 , as shown in FIG. 1d . Since the re-recessed surface 213Ba of the inter-window recess 213B is lower than the surface 213Aa of the source-drain region 211A in the trench 213, after the bit line contact 230 is formed by etching, further etching is required to remove the remaining recess between the windows. The bit line contact material on the re-recessed surface 213Ba of the groove 213B can avoid short circuits between a plurality of adjacent bit line contacts 230, and in this process, it also causes the two sidewalls 230A of the bit line contacts 230 to break down. over-etching, thereby forming an undercut of the bit line contact 230 .

The undercut phenomenon will affect the resistance value of the bit line contact 230, and the resistance value increases with the increase of the undercut ratio, which in turn affects the signal transmission between the bit line 240 and the source and drain regions 211A, so that the response of the semiconductor memory Reduced performance. In addition, the bit line contact 230 has to bear a certain mechanical strength in the subsequent manufacturing process, and severe bit line contact side etching will reduce the yield of the product. In order to ensure that the bit line contact 230 has a suitable resistance value and sufficient mechanical strength, it is necessary to analyze the relevant factors of the formation of the bit line contact undercut.

As shown in FIG. 1d , set the width of the narrowest part between the two sidewalls 230A of the bit line contact 230 in the extending direction of the word line 220 to be b, and the width of the top of the bit line contact 230 to be a, then the bit line The sum of the undercut depths of the two sidewalls 230A of the contact 230 is (a-b), which can be characterized by the ratio of the sum of the undercut depths (a-b) to the top width a of the bit line contact 230, that is, the undercut ratio (a-b)/a The degree of undercut of the bit line contact 230 . In the following, the ratio of the undercut ratio (a-b)/a is used to characterize the undercut depth of the bit line contact 230 .

Through the applicant's in-depth research, it is found that the undercut ratio (a-b)/a of the bit line contact 230 is proportional to the re-recessed depth c of the recess 213B between the windows. FIG. 2 is a graph showing the relationship between the undercut ratio of the bit line contact 230 and the re-recessed depth of the inter-window groove 213B according to an embodiment of the present invention. As shown in FIG. 2 , the undercut ratio of the bit line contact 230 is proportional to the re-recessed depth of the recess 213B between the windows. The larger the etch ratio, the greater the sum of the undercuts on the two sidewalls 230A of the bit line contact 230 with a certain width, and accordingly, the more serious the undercut degree of the bit line contact 230 is. For example, when the re-recessed depth of the inter-window recess 213B is 5.8 nm, the undercut ratio of the bit line contact 230 is 25%; when the re-recessed depth of the inter-window recess 213B is 9.0 nm, the bit line contact 230 The ratio of lateral erosion can reach 55%. Therefore, in order to ensure that the bit line contact 230 has a width that meets the performance requirements, when forming the trench 213, it is necessary to control and reduce the re-recessed depth of the recess 213B between the windows as much as possible to reduce the severity of the bit line contact 230 undercut. In one embodiment, preferably, the re-recessed depth of the inter-window grooves 213B ranges from 5.8 nm to 8.5 nm, and the undercut ratio of the bit line contact 230 is the cut of the bit line contact 230 in the extending direction of the word line 220 . The ratio of the sum of the undercut depths of the two sidewalls 230A to the top width of the bit line contact 230 ranges from 25% to 50%. It should be noted here that the re-recessed depth c of the inter-window groove 213B is the distance from the lowest point of the inter-window groove 213B to the surface 213Aa of the source-drain region 211A in the trench 213 .

Further, the re-recessed depth of the inter-window groove 213B is related to the etching selectivity ratio of the etchant to the isolation structure 212 and the source and drain regions 211A. FIG. 3 is a graph showing the relationship between the gas volume ratio of the etchant CHF ₃ /CH ₄ and the SiO ₂ /Si etching selectivity ratio and the re-recessed depth of the inter-window groove 213B according to an embodiment of the present invention. It can be seen from FIG. 3 that there are differences in the etching selectivity ratio of SiO ₂ /Si with different CHF ₃ /CH ₄ ratios. With the increase of the CHF ₃ /CH ₄ ratio, the etching selectivity ratio of SiO ₂ /Si decreases, that is, the difference between the etching rate and etching depth of SiO ₂ and Si decreases, and accordingly the re-recessing of the grooves 213B between the windows decreases. The penetration depth is also reduced. For example, when the CHF ₃ /CH ₄ ratio is 0.5, the etching selectivity ratio of SiO ₂ /Si is 2.3, and the re-recessed depth of the resulting inter-window grooves 213B is 9.0 nm; when the CHF ₃ /CH ₄ ratio is 1.6 , the etching selectivity ratio of SiO ₂ /Si is 1.1, and the re-recessed depth of the inter-window groove 213B is only 5.8 nm. Therefore, selecting an appropriate CHF ₃ /CH ₄ ratio can effectively reduce the etching selectivity ratio of SiO ₂ /Si, thereby reducing the re-recessed depth of the grooves 213B between the windows. But on the other hand, it can be seen that with the increase of the CHF ₃ /CH ₄ ratio, the etch selectivity ratio of SiO ₂ /Si and the degree of decrease of the re-recessed depth of the groove 213B between the windows gradually tend to slow down, that is, further increase The CHF ₃ /CH ₄ ratio cannot further reduce the etching selectivity ratio of SiO ₂ /Si and the re-recessed depth of the grooves 213B between the windows. From the actual effect, the etching selectivity ratio of SiO ₂ /Si cannot appear. The same and the case where the re-recess depth of the inter-window groove 213 is zero. In an embodiment of the present invention, preferably, the CHF ₃ /CH ₄ ratio ranges from 0.5 to 1.6.

Besides, the re-recessed depth of the inter-window groove 213B is also related to the type of etchant.

Embodiment 2

Another embodiment of the present invention selects different etchant gases in order to further reduce the etching selectivity ratio of SiO ₂ /Si and the re-recessed depth of the grooves 213B between the windows.

A semiconductor memory structure includes: a substrate 210, a word line 220, a bit line contact 330, a bit line 240, a protective layer 250 and a first barrier layer 260, as shown in Figures 4a-4d.

The upper surface of the substrate 210 defines a plurality of active regions 311, the active regions 311 are spaced apart from each other to form an active region array, and the active regions 311 are formed on the surface of the substrate 210 and do not penetrate the substrate 210, as shown in FIG. 4a , shown in 4b. In one embodiment, the material of the active region 311 includes doped Si.

An isolation structure 312 is provided between the active regions 311 , and the isolation structure 312 is formed in the substrate 210 and insulates the active regions 311 from each other, as shown in FIGS. 4 a and 4 c . In one embodiment, the isolation structure 312 may be Shallow Trench Isolation (STI), and the isolation material includes silicon dioxide (SiO ₂ ).

The word lines 220 are embedded in the substrate 210 and laid along the extending direction of the word lines 220 to intersect with the plurality of active regions 311 and the isolation structures 312 , and the word lines 220 are parallel to each other and intersect the active regions 311 at a certain angle, And a single active region 311 intersects with two word lines 220, and two adjacent word lines 220 divide the single active region 311 into three source-drain regions 311A, 311B and 311C, see FIGS. 4a and 4b. The word line 220 includes an insulating layer 221, a blocking layer 222, a seed layer (not shown) and a conductor layer 223 in sequence from the sidewall to the central axis, as shown in FIG. 4b. In one embodiment, the material of the insulating layer 221 includes silicon dioxide, the material of the insulating layer 222 includes titanium (Ti) or titanium nitride (TiN), the material of the conductor layer 223 includes metal tungsten (W), the seed layer and the conductor The material of layer 223 is the same.

A through trench 313 intersecting the middle region of the active region 311 is formed between two adjacent word lines 220, and the trench 313 passes through the plurality of source and drain regions 311A and the isolation structure 312, as shown in FIG. 4a. The portion of the trench 313 on the source-drain region 311A includes a contact window 313A recessed from the upper surface of the source-drain region 311A to overlap the bit line 240; The upper surface of 312 has a recessed inter-window groove 313B, and the window of the contact window 313A has a re-concave surface 313Aa relative to the inter-window groove 313B, and the re-concave surface 313Aa of the contact window 313A is lower than the inter-window groove 313B The surface 313Ba of the contact window 313A, the re-recessed surface 313Aa of the contact window 313A and the surface 313Ba of the recess 313B between the windows are all lower than the surface of the active region 311 and the isolation structure 312 outside the trench 313, as shown in Figures 4b and 4c. In one embodiment, the re-concave surface 313Aa of the contact window 313A is shaped as a concave arc, as shown in FIG. 4b. In one embodiment, the depth range from the lowest point of the contact window 313A to the surface 313Ba of the recess 313B between the windows is between 5.8 nm and 8.5 nm, so that the plurality of adjacent bit line contacts 230 in the trench 213 are not electrically connected to each other. .

A bit line contact 330 is formed on the source-drain region 311A in the contact window 313A and does not completely fill the contact window 313A, as shown in FIG. 4b. The bit line contact 330 is used to realize electrical connection between the bit line 240 and the source and drain regions 311A. In one embodiment, the sidewalls of the contact windows 313A are not in contact with the sidewalls of the word lines 220 . The bit line contacts 330 are formed by deposition such as CVD or PVD. In one embodiment, the material of the bit line contact 330 includes polysilicon (Poly-Si).

The bit lines 240 are formed on the substrate 210 and extend in a continuous wave shape, and are regularly arranged at certain intervals. A single bit line 240 is interlaced with a plurality of active regions 311 and a plurality of word lines 220, as shown in the figure 4a. The bit line contact 330 is electrically connected between the intersecting parts of the bit line 240 and the active region 311 , see FIGS. 4 a and 4 b; See Figure 4d for a vertical section profile in the extension direction. The bit line 240 may be a multi-layer composite structure. In one embodiment, the bit line 240 includes a titanium nitride layer, a metal tungsten layer, and the like in sequence away from the bit line contact 330 .

In one embodiment, a protective layer 250 is further deposited on the surface of the active region 311 , the isolation structure 312 and the word line 220 outside the trench 313 region to protect and insulate the surface of the active region 311 and the word line 220 . The bit line 240 is stacked on the passivation layer 250 and the bit line contact 330 . In one embodiment, the material of the protective layer 250 includes silicon nitride (Si ₃ N ₄ ) or the like. The trench 313 is formed by etching the portion of the protective layer 250 between two adjacent word lines 220, the depth of the contact window 313A is formed by etching the portion of the active region 311 in the trench 313, and the inter-window groove 313B The depth is formed by etching the portion of the isolation structure 312 in the trench 313 .

In one embodiment, the surface of the bit line 240 is also covered with a first barrier layer 260, the main function of which is to insulate the surface of the bit line; The barrier layer 260 can be used as a hard mask to etch the bit line material and the bit line contact material. In another embodiment, a second barrier layer 270 is further formed on the first barrier layer 260, and together with the first barrier layer 260, serves as a hard mask for etching the bit line material and the bit line contact material. In one embodiment, the material of the first barrier layer 260 includes silicon nitride, and the material of the second barrier layer 270 includes silicon dioxide.

To sum up, the difference from the semiconductor memory structure shown in Embodiment 1 is that the re-recessed surface is formed on the source-drain region 311A in the contact window 313A, and the re-recessed surface 313Aa of the contact window 313A is lower than the trench 313 The surface of the inner isolation structure 312 is the surface 313Ba of the recess 313B between the windows; on the other hand, the two sidewalls 330A formed along the extension direction of the bit line 240 of the bit line contact 330 are not formed with undercuts in the extension direction of the word line 220 , instead has a vertical cut profile, as shown in Fig. 4d.

Compared with Embodiment 1, since the surface 313Ba of the inter-window recess 313B between the bit line contacts 330 is higher than the re-recessed surface 313Aa of the contact window 313A, the bit line contact 330 will not be formed by etching when the bit line contact 330 is formed. Bit line contact material remains on the surface 313Ba of the inter-window recess 313B. Therefore, there is no need to perform over-etching to remove the bit line contact residues and the resulting bit line contact side etching, and the two sidewalls 330A of the bit line contact 330 have a better vertical profile.

The trench 313 is formed by sequentially etching the protective layer 250 , the source and drain regions 311A and the isolation structure 312 with different etchants. In one embodiment, a mixed gas of carbon tetrafluoride (CF ₄ ), fluoromethane (CH ₃ F) and oxygen (O ₂ ) is selected as the first etchant to perform etching on the protective layer 250 (eg, silicon nitride). For etching, the preferred volume ratio of carbon tetrafluoride, fluoromethane and oxygen ranges from (40 to 50): (10 to 24): (30 to 48); then select chlorine (Cl ₂ ) and/or bromide The mixed gas of hydrogen (HBr) is used as the second etchant to etch the source and drain regions 311A (eg doped Si) and the isolation structure 312 (eg SiO ₂ ). When the mixed gas of chlorine and hydrogen bromide is selected, In one embodiment, preferably, the volume ratio of chlorine gas to hydrogen bromide is in the range of 1:1.

In another aspect of the present invention, a method for manufacturing the semiconductor memory structure corresponding to Embodiment 1 and Embodiment 2 is also provided.

Manufacturing method of memory structure of Embodiment 1

A typical embodiment of the present application provides a method for manufacturing the semiconductor memory structure of Embodiment 1, which includes the following steps S201 to S206.

In step S201, the active region 211 and the isolation structure 212 are formed. Specifically, the substrate 210 is provided, and a plurality of active regions 211 are formed from the surface of the substrate 210 to the inside of the substrate 210 without penetrating the substrate 210 . The active regions 211 are spaced apart from each other and form an active region array. Between the active regions 211 , isolation structures 212 are provided from the surface of the substrate 210 to the interior of the substrate 210 , wherein the depth of the isolation structures 212 is greater than the depth of the active regions 211 , and the surface of the isolation structures 212 is closer to the active region 211 . The surfaces are flush, as shown in Figures 5a, 5b. The purpose of disposing the isolation structures 212 is to insulate the active regions 211 from each other. In one embodiment, the isolation structures 212 may be Shallow Trench Isolation (STI), and the isolation material includes silicon dioxide.

In step S202, the word lines 220 and the protective layer 250 are formed. Specifically, a plurality of buried word lines 220 are formed in the substrate 210. The word lines 220 extend linearly and pass through the plurality of active regions 211 and the isolation structures 212. The word lines 220 are parallel to each other and to the active regions. 211 intersect at an angle, and a single active region 211 intersects with two adjacent word lines 220, which divide the single active region 211 into three source-drain regions 211A, 211B, and 211C , as shown in Figures 6a-6c. The word line 220 includes an insulating layer 221, a blocking layer 222, a seed layer (not shown) and a conductor layer 223 in sequence from the sidewall to the central axis, as shown in FIG. 6b. In one embodiment, the material of the insulating layer 221 includes silicon dioxide, the material of the insulating layer 222 includes titanium or titanium nitride, the material of the conductor layer 223 includes metal tungsten, and the material of the seed layer is the same as that of the conductor layer 223 .

A protective layer 250 is deposited on the substrate 210 and covers the surfaces of the active regions 211, the isolation structures 212 and the word lines 220, as shown in FIGS. 6a-6d. In one embodiment, the material of the protective layer 250 includes silicon nitride.

In step S203, a contact window 213A is formed, as shown in Figs. 7a-7d. The purpose of forming the contact window 213A is to subsequently deposit and form the bit line contact 230 in the contact window 213A, and make the bit line contact 230 electrically connect the bit line 240 and the source-drain region 211A, so as to transmit the signal in the bit line 240 to the source Drain region 211A. The contact windows 213A themselves only need to be formed on the regions of the respective source and drain regions 211A, but in actual production, trench etching is generally used to form the contact windows 213A. Specifically, the protective layer 250 between the two adjacent word lines 220 is etched to form a through trench 213. Generally, in order to completely remove the protective layer 250 between the two word lines 220, the protective layer 250 needs to be processed Etching is performed to ensure that the source and drain regions 211A are sufficiently exposed. During this process, the source and drain regions 211A and the isolation structure 212 are etched simultaneously. The portion of the trench 213 on the source-drain region 211A includes a contact window 213A recessed from the upper surface of the source-drain region 211A to overlap the bit line 240; The upper surface of the inter-window groove 213B is concave, and the inter-window groove 213B has a re-concave surface 213Ba relative to the contact window 213A, and the re-concave surface 213Ba of the inter-window groove 213B is lower than the source-drain in the trench 213 The surface 213Aa of the electrode region 211A, the re-recessed surface 213Ba of the inter-window recess 213B and the surface 213Aa of the source-drain region 211A are all lower than the surfaces of the active region 211 and the isolation structure 212 outside the trench 213 . In one embodiment, the re-concave surface 213Ba of the inter-window groove 213B is shaped as a concave arc, as shown in FIG. 7c. In one embodiment, the depth range from the lowest point of the recess 213B between the windows to the surface 213Aa of the source-drain region 211A in the trench 213 ranges from 5.8 nm to 8.5 nm, so that a plurality of adjacent bit lines in the trench 213 are formed. Contacts 230 are not electrically connected to each other.

Usually, the protective layer 250 is etched by using a mixed gas of trifluoromethane (CHF ₃ ) and carbon tetrafluoride (CF ₄ ) as an etchant. In one embodiment, the material of the protective layer 250 is silicon nitride ( Si ₃ N ₄ ). At the same time, CHF ₃ /CF ₄ also etches the source and drain regions 211A and the isolation structure 212 . In one embodiment, the material of the source and drain regions 211A includes doped Si, and the material of the isolation structure 212 (eg, STI) includes silicon dioxide (SiO ₂ ). Since the etching selectivity ratio of CHF ₃ /CF ₄ to SiO ₂ is greater than that of Si, after the etching is completed, the etching depth of SiO ₂ is greater than that of Si, resulting in the formation on the surface of SiO ₂ The surface 213Ba is then recessed, as shown in Figures 7c, 7d.

Step S204, depositing bit line contact material. Specifically, the bit line contact material P100 is deposited in the through trenches 213 and fills the trenches 213 . The upper surface of the bit line contact material P100 is flush with the surface of the protective layer 250 , as shown in FIGS. 8 a to 8 d . It can be seen that the groove 212A is also filled with the bit line contact material P100. The bit line contact material P100 is conductive, and in one embodiment, the bit line contact material P100 includes doped polysilicon (Poly-Si).

Step S205, depositing bit line material and forming a barrier layer. First, a bit line blocking layer material P200, a bit line conductor layer material P300, a first barrier layer material P400, and a second barrier layer material P500 (not shown) are sequentially deposited on the entire surface of the substrate 210. Next, a photoresist etching pattern of the bit line is formed on the surface of the second barrier layer material P500, and the second and first barrier layer materials P500 and P400 are etched under the pattern to form the second barrier layer 270 and the first barrier layer, respectively. A barrier layer 260, referring to FIGS. 9a-9d. In one embodiment, the bit line blocking layer material P200 includes titanium (Ti) or titanium nitride (TiN), the bit line conductor layer material P300 includes metal tungsten (W), and the first barrier layer 260 material P400 includes silicon nitride (Si ₃ N ₄ ), and the material P500 of the second barrier layer 270 includes silicon dioxide (SiO ₂ ).

In step S206, the bit line material and the bit line contact material are etched. Using the second barrier layer 270 and the first barrier layer 260 as a hard mask, continue to etch the bit line conductor layer material P300, the bit line barrier layer material P200 and the bit line contact material P100 to form the bit line 240 and bit line contacts 230, as shown in Figures 10a-10d. It should be noted here that when etching is performed using the second barrier layer 270 (eg, SiO ₂ ) as a hard mask, depending on the thickness of SiO ₂ , SiO ₂ may be completely consumed after the etching is completed. In one embodiment, the thickness of the second barrier layer 270 is 10-20 nm, and the thickness of the first barrier layer 260 is 150-200 nm.

Since the re-recessed surface 213Ba of the inter-window recess 213B is filled with the bit line contact material P100, after the etching of the bit line contact material P100 is completed and the bit line contact 230 is formed, there are still bits remaining on the re-recessed surface 213Ba. The line contacts the material P100 and can cause a short between the bit line contacts 230 . Further removal of the residual bitline contact material P100 results in undercutting of the sidewall 230A of the bitline contact 230, as shown in FIG. 10d. In order to reduce the undercut degree of the bit line contact 230, it is necessary to effectively control the re-recess depth of the recess 213B between the windows.

As mentioned above, by controlling the ratio of the etchant CHF ₃ /CF ₄ used in the formation of the trenches 213 , the re-recessed depth of the recesses 213B between the windows can be controlled within a reasonable range, so as to avoid bit lines For the occurrence of severe lateral erosion of the contact 230, please refer to the foregoing description of FIG. 2 and FIG. 3 for related content, which will not be repeated here.

Manufacturing method of memory structure of Embodiment 2

Another typical embodiment of the present application provides a method for fabricating the semiconductor memory structure in the above-mentioned Embodiment 2, which is similar to the method for fabricating the memory structure in Embodiment 1, except that in step S203, the etchant used is Instead of a mixture of CHF ₃ /CF ₄ , the etching is performed step by step with different etchants. First, the protective layer 250 (eg, silicon nitride) is etched with a mixed gas of CF ₄ /CH ₃ F/O ₂ , and then the source and drain regions 211A and the isolation structures 212 are etched with chlorine gas and/or hydrogen bromide gas. After etching, a memory structure in which the surface 313Ba of the inter-window recess 313B in the trench 313 is higher than the re-recessed surface 313Aa of the contact window 313A is finally formed, as shown in FIG. 4 .

The manufacturing method of the memory structure of Embodiment 2 is the same as the manufacturing method of the memory structure of Embodiment 1. Please refer to the foregoing description of the manufacturing method of the structure of Embodiment 1, which will not be repeated here.

In the description of this specification, description with reference to the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples", etc., mean specific features described in connection with the embodiment or example , structure, material or feature is included in at least one embodiment or example of the present invention. Furthermore, the particular features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, those skilled in the art may combine and combine the different embodiments or examples described in this specification, as well as the features of the different embodiments or examples, without conflicting each other.

In addition, the terms "first" and "second" are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, a feature delimited with "first", "second" may expressly or implicitly include at least one of that feature. In the description of the present invention, "plurality" means two or more, unless otherwise expressly and specifically defined.

The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited to this. Any person skilled in the art who is familiar with the technical field disclosed in the present invention can easily think of various changes or Replacement, these should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims (11)

1. A semiconductor memory structure, comprising:

a substrate having a plurality of active regions defined by an upper surface of the substrate and spaced apart from each other;

an isolation structure formed in the substrate and insulating the active regions from each other;

word lines buried in the substrate and laid in parallel in the direction in which the word lines extend to intersect the active regions and the isolation structures, a through trench intersecting a middle region of the active regions being formed between two adjacent word lines, a portion of the trench on the active regions including a contact window recessed from an upper surface of the active regions to overlap bit lines; and

a bit line contact formed on the active region in the contact window;

wherein the portion of the trench on the isolation structure comprises an inter-window groove recessed from the upper surface of the isolation structure, the inter-window groove has a re-recessed surface relative to the contact window, lower than the surface of the active region in the trench, and the depth from the lowest point of the inter-window groove to the surface of the active region in the trench is between 5.8nm and 8.5nm, so that a plurality of adjacent bit line contacts in the trench are not electrically connected with each other.

2. The semiconductor memory structure of claim 1, further comprising:

the bit lines are formed on the substrate and are in a continuous wavy shape, and the bit line contacts are electrically connected between the staggered parts of the bit lines and the active regions;

and two side walls of the bit line contact formed along the extension direction of the bit line are provided with cut-off outlines etched laterally in the extension direction of the word line.

3. The semiconductor memory structure of claim 2, wherein a ratio of a sum of undercut depths of the two sidewalls of the bit line contact cut in the word line extending direction to a top width of the bit line contact ranges from 25% to 50%.

4. The semiconductor memory structure of claim 3, wherein a sum of undercut depths of the bit line contacts of the two sidewalls cut in the word line extending direction is in direct proportion to a re-recessing depth of the inter-window groove.

5. The semiconductor memory structure of claim 4, wherein a sum of undercut depths of the two sidewalls of the bit line contact is a maximum of 50% of a top width of the bit line contact corresponding to a maximum re-recessing depth of the inter-window trench of 8.5 nm.

6. The semiconductor memory structure of claim 2, further comprising:

and the protective layer covers the surfaces of the active region and the isolation structure except the ditch region, and the bit line is superposed on the protective layer and the bit line contact.

7. The semiconductor memory structure of claim 6, wherein the trenches are formed by etching portions of the protection layer between two adjacent word lines, the depth of the contact windows is formed by etching portions of the active regions in the trenches, and the depth of the inter-window grooves is formed by etching portions of the isolation structures in the trenches;

the etchant for etching the protective layer, the active region and the isolation structure comprises trifluoromethane and carbon tetrafluoride, and the ratio of the trifluoromethane to the carbon tetrafluoride is in the range of 0.5-1.6;

the etching selectivity ratio of the etching agent to the isolation structure and the active region ranges from 1.1 to 2.3, and is reduced along with the increase of the ratio of the trifluoromethane to the carbon tetrafluoride;

the depth of the inter-window groove decreases as the ratio of the trifluoromethane to the carbon tetrafluoride increases.

8. A semiconductor memory structure, comprising:

a substrate having a plurality of active regions defined by an upper surface of the substrate and spaced apart from each other;

an isolation structure formed in the substrate and insulating the active regions from each other;

word lines embedded in the substrate and laid in parallel along the extension direction of the word lines to intersect the active regions and the isolation structures, wherein a through trench intersecting the middle region of the active regions is formed between two adjacent word lines, and the trench comprises a contact window recessed from the upper surface of the active regions; and

a bit line contact formed on the active region in the contact window;

wherein the trench further comprises inter-window recesses between the active regions of the isolation structure, and re-recessed surfaces are provided in the contact window relative to the inter-window recesses, so that a plurality of adjacent bit line contacts in the trench are not electrically connected to each other.

9. The semiconductor memory structure of claim 8, further comprising:

the bit lines are formed on the substrate and are in a continuous wavy shape, and the bit line contacts are electrically connected between the staggered parts of the bit lines and the active regions;

wherein, the two side walls of the bit line contact formed along the extension direction of the bit line have a cross-sectional shape perpendicular to the extension direction of the word line.

10. The semiconductor memory structure of claim 9, further comprising:

and the protective layer covers the surfaces of the active region and the isolation structure except the ditch region, and the bit line is superposed on the protective layer and the bit line contact.

11. The semiconductor memory structure of claim 10, wherein the trenches are formed by etching portions of the protection layer between two adjacent word lines, the depth of the contact windows is formed by etching portions of the active regions in the trenches, and the depth of the inter-window grooves is formed by etching portions of the isolation structures in the trenches;

the etching agent for etching the protective layer comprises carbon tetrafluoride, fluoromethane and oxygen, wherein the proportion of the carbon tetrafluoride, the fluoromethane and the oxygen is (40-50): (10-24): (30-48);

the etchant for etching the active region and the isolation structure comprises chlorine gas and/or hydrogen bromide gas, wherein the proportion range of the chlorine gas and the hydrogen bromide gas comprises 1: 1.

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