CN110808742A - Efficient decoder framework suitable for 5G LDPC code - Google Patents

Abstract

The present invention discloses for the first time a high-throughput, low-complexity decoder architecture commonly used in 5G LDPC codes. First, using the partial orthogonality of the base matrix of the 5G LDPC code, the layer merging technology reduces the number of clock cycles and reduces the area consumption of the parity information memory. Second, since the row weight of 5G LDPC is very irregular, a distributed storage structure is adopted to reduce storage resource consumption. Finally, in order to solve the problem of high delay and high complexity caused by large-scale reading and writing of the Internet, a shift structure is used to realize the soft message memory, which greatly reduces the number of input and output of the Internet. In addition, information rearrangement is applied in the Internet to optimize its internal architecture. Compared with the conventional design, the area of the decoder disclosed in the present invention is greatly reduced, and it can provide a higher throughput rate, and increase the throughput rate-area ratio to 2.68 times.

Description

An Efficient Decoder Architecture for 5G LDPC Codes

Technical field

The present invention relates to the decoder architecture design in the technical field of communication coding, in particular to a decoder architecture with high throughput and low complexity suitable for 5G LDPC codes.

Background technique

Error-correcting codes are a very important part of modern communication systems. In the latest 5G communication standards, LDPC codes are adopted as channel coding schemes due to their superior error correction performance and relatively low decoding complexity. Different from conventional LDPC codes, 5G LDPC codes need to be able to satisfy code rate compatibility in order to support Hybrid Automatic Repeat Request (HARQ). Therefore, its basis matrix is a concatenation of a high rate LDPC code matrix and a low density generator matrix (LDGM). The row weight and column weight of the 5G LDPC code are extremely irregular, and the row weight of each check node and the column weight of each variable node are very different. The 3rd Generation Partnership Project (3GPP) provides two basis matrices for 5G LDPC codes, basis matrix 1 (BG1) and basis matrix 2 (BG2). The two basis matrices have similar structures. BG1 is used for codewords with higher code rate and code length, and BG2 is used for codewords with lower code rate and code length.

Existing LDPC decoder architectures are mainly divided into three types, fully parallel architecture, fully serial architecture and partially parallel architecture. In order to obtain a good compromise between throughput and hardware complexity, a layered decoding architecture based on partial parallelism is commonly used at present. Hierarchical decoding can also speed up the convergence speed without affecting the decoding performance, thereby reducing the number of iterations required, thereby improving throughput. Although the decoding architecture design of LDPC has been extensively studied, however, there is currently no decoder specifically designed for 5G LDPC codes. Considering the particularity of its structure, if a general decoding structure is adopted, it will cause a great waste of resources and an unsatisfactory throughput rate. Therefore, there is still a lot of research space in the design and optimization of 5G LDPC code decoders.

SUMMARY OF THE INVENTION

Object of the invention: The present invention aims to provide a 5G LDPC decoder with high throughput and low complexity in view of the above problems. The specific contents of the invention are as follows:

A high-throughput, low-complexity decoder architecture commonly used in 5G LDPC codes, characterized in that it includes the following units:

1) a controller for generating all control signals in the decoder;

2) Soft message memory for storing the soft decision message of each bit. To be able to support massively parallel reading and initialization of soft decision messages for all bits, the memory is implemented by a register bank. In order to reduce the resource consumption input to the Internet, the soft-decision messages corresponding to the extension bits and the soft-decision messages corresponding to the core bits are stored separately. The memory storing the soft-decision message corresponding to the extended bit is implemented by a shift architecture, so the address of the required data can be fixed. Based on this, the memory corresponding to this part only needs to input and output a set of data at a time;

用于判定每层行重的大小。其次，对于行重小于等于的层，将其校验节点输出的所有校验消息存在第一个子存储器中。对于行重大于

的层，对于每个校验节点输出的校验消息，将其中的地址消息存在第二个子存储器中，其余部分的校验消息存在第一个子存储器中。值得注意的是，因为第二个子存储器只应用于行重大于

的层，所以其深度远小于第一个子存储器；3) A verification information memory, which is used to store the verification information calculated by each verification node. To be able to support simultaneous read and write operations, the unit is implemented using dual-port random access memory (DRAM). In order to reduce the area consumption, a distributed structure is adopted. First, preset a threshold

Used to determine the size of the row weight of each layer. Second, for row weights less than or equal to It stores all check messages output by its check nodes in the first sub-memory. For row weights greater than

For the check message output by each check node, the address message is stored in the second sub-memory, and the rest of the check messages are stored in the first sub-memory. It's worth noting that because the second submemory is only used for row weights greater than

, so its depth is much smaller than the first sub-memory;

4) Read the Internet, which is used to read the soft message value from the soft message memory, and select the maximum row weight corresponding to the current execution layer. Group soft messages are output. In order to reduce the consumption of the interconnection network, the input messages corresponding to each output in each layer are reordered in a way that minimizes the number of inputs required to generate each output. The sorting is done offline, so it does not occupy hardware resources;

5) A shifter, which shifts each group of soft-decision messages according to their corresponding shift factors, so that the inside can be arranged in the correct order. The shift factor of each group of messages in the current layer is the shift coefficient of the column of the corresponding base matrix in the current layer minus the previous non-negative shift coefficient of the column. Therefore, the re-shifting when writing the message to the soft message memory is omitted. In addition, before the input data is loaded into the soft message memory, it needs to be reversely shifted according to the last shift coefficient of the column of the corresponding base matrix, so as to ensure the correctness of the position of each group of messages when they are shifted for the first time. The output data needs to be shifted according to the last shift coefficient of the column of the corresponding base matrix before output to ensure that the output code words are sorted in the correct order;

6) a variable node unit, used to generate a variable message that the variable node transmits to the check node;

7) A check node unit for generating a check message to be passed to the variable node. To reduce storage width, the output data is arranged in a compressed format. For example, for the minimum sum decoder, in each check node, only the sign bit of each check message, the minimum input variable message and its corresponding address, and the second small input variable message are output;

8) a decompressor for converting the check information from a compressed form to an uncompressed form;

组更新后的软消息生成软消息存储器中所需的消息。9) Write to the Internet, based on the current execution layer

The group updated soft message generates the desired message in the soft message memory.

In the proposed architecture, the partial orthogonality of the basis matrix of the 5G LDPC code is utilized, and the two layers of the orthogonal part are regarded as one layer for decoding. As a result, the required number of clock cycles can be greatly reduced, thereby increasing throughput. In addition, the depth of the verification message memory can also be reduced accordingly.

The decoder architecture proposed by the present invention has the following beneficial effects:

First, the number of layers of the decoder is reduced, which in turn reduces the number of clock cycles required and improves the throughput;

Secondly, the width and depth of the verification information memory are greatly reduced, and its area consumption is reduced;

Finally, the area and latency of reading and writing the interconnect are optimized.

Based on the above advantages, the decoder architecture proposed by the present invention greatly reduces the area and delay required by the 5G LDPC decoder, and improves the throughput-area-efficiency ratio.

Description of drawings

1 is a schematic diagram of a top-level architecture of a decoder of the present invention;

Fig. 2 is the orthogonal characteristic schematic diagram of basis matrix 2;

Fig. 3 is the concrete structural representation of check information memory in the decoder of the present invention;

4 is a schematic diagram of the shift structure of the soft message memory in the decoder of the present invention;

FIG. 5 is a schematic diagram of the structure of the BG2 matrix.

Detailed ways

The decoder architecture proposed by the present invention will be further described below with reference to the accompanying drawings. It is particularly noted that the implementations described with reference to the accompanying drawings are exemplary, and are intended to be used to explain the present invention, but not to be construed as a limitation of the present invention.

组软消息。其次，每组软消息在移位器中被循环移位，移位因子为该组消息对应基矩阵的列在当前层的移位系数减去该列的上一个非负移位系数。经过移位后的消息被送入到变量节点单元用于产生变量消息，这些变量消息会被送到校验节点单元产生校验消息。对于不同的译码算法，校验消息的产生方式会有不同，因此本发明不指定校验节点单元的实现方式。校验消息随后有两个用途。其一为将其存入校验信息存储器中，用于在下一次译码迭代中产生变量消息。为降低校验信息存储器位宽，其按照压缩格式排列。例如对于最小和译码器，在每个校验节点中，只输出校验消息的符号位，最小输入变量消息以及其对应的地址，和第二小输入变量消息。其二是在经过解压缩器对其进行解压后与当前迭代的变量消息结合，产生更新后的软判决消息值。更新后的软判决消息会在写入互联网络中进行排序和选择，以保证其被存储到正确的软消息译码器地址中。在完成所有译码层操作后，译码便完成了一次迭代。当到达了最大迭代次数T_max后，译码终止并输出译码码字。值得注意的是，译码码字在输出前需要根据其对应基矩阵的列的最后一个移位系数进行移位，以保证输出数据按照正确顺序排序。1 is a schematic diagram of the top-level architecture of the decoder of the present invention, wherein a layered decoding structure is adopted, and the number of layers is equal to the number of rows of the corresponding codeword base matrix, denoted as L. The parallel coefficient of the decoder is equal to the expansion factor of the base matrix, denoted as z. In the proposed decoding architecture, all control signals are generated by the controller. First, the message from the channel is shifted by the input shifter and loaded into the soft message memory. The input shifter performs reverse shifting according to the last shift coefficient on the column of the base matrix corresponding to each group of messages. Each decoding iteration consists of L decoding layers. In each decoding layer, first, the soft-decision message is read from the soft message memory and input to the read internetwork, which generates the maximum row weight corresponding to the current execution layer according to the current decoding layer

Group soft messages. Secondly, each group of soft messages is cyclically shifted in the shifter, and the shift factor is the shift coefficient of the column of the base matrix corresponding to the group of messages in the current layer minus the previous non-negative shift coefficient of the column. The shifted messages are sent to the variable node unit for generating variable messages, and these variable messages will be sent to the check node unit to generate check messages. For different decoding algorithms, the generation methods of the check message will be different, so the present invention does not specify the realization method of the check node unit. The verification message then serves two purposes. One is to store it in the parity information memory for generating variable messages in the next decoding iteration. In order to reduce the bit width of the parity information memory, it is arranged in a compressed format. For example, for the minimum sum decoder, in each check node, only the sign bit of the check message, the minimum input variable message and its corresponding address, and the second small input variable message are output. The second is to combine it with the variable message of the current iteration after it is decompressed by the decompressor to generate an updated soft decision message value. The updated soft-decision messages are sorted and selected in the write internetwork to ensure that they are stored in the correct soft-message decoder address. After all decoding layer operations are completed, the decoding completes one iteration. When the maximum number of iterations T _max is reached, the decoding is terminated and the decoded codeword is output. It is worth noting that the decoded codeword needs to be shifted according to the last shift coefficient of the column of the corresponding base matrix before output, so as to ensure that the output data is sorted in the correct order.

采用层合并也不会引起存储器宽度的增加。对于BG2矩阵，采用层合并可以将L从42降低到31。因此，译码周期数和校验信息存储器的消耗均可减少26.2％。对于BG1矩阵，减少百分比为28.3％。FIG. 2 is a schematic diagram of the orthogonal characteristic of the basis matrix 2 . As you can see, rows 21 to 42 of this matrix are orthogonal, which means that no one variable node is connected to two consecutive layers in the orthogonal part at the same time. Therefore, we can treat two consecutive layers in the orthogonal part as one layer, which brings two benefits. First, by reducing the number of decoding layers, the required number of cycles can be reduced to improve throughput; second, the reduction in the number of decoding layers can correspondingly reduce the depth of the parity information memory, thereby reducing storage resource consumption. Considering that the row weights of the orthogonal parts are all less than

There is also no increase in memory width caused by layer merging. For BG2 matrices, L can be reduced from 42 to 31 with layer binning. Therefore, the number of decoding cycles and the consumption of the parity information memory can be reduced by 26.2%. For the BG1 matrix, the percentage reduction is 28.3%.

其中q为校验消息的量化比特数。这种设计方式对于行重较低的层来说是一种浪费。因此，本发明为校验信息存储器提出了一种分布式的存储方式，具体结构如图二所示。首先，预设一个阈值

用于判定每层行重的大小。其次，对于行重小于等于

的层，将其校验节点输出的所有校验消息存在第一个子存储器中。对于行重大于

的层，对于每个校验节点输出的校验消息，将其中的地址消息存在第二个子存储器中，其余部分的校验消息存在第一个子存储器中。值得注意的是，因为第二个子存储器只应用于行重大于的层，所以其深度远小于第一个子存储器。基于此，校验信息存储器的资源消耗可进一步降低。例如，对于BG1矩阵可将

设为15，此时校验信息存储器大小可降低15.2％；对于BG2矩阵可将设为8，此时校验信息存储器大小可降低13.7％。当与层合并技术相结合时，对于BG1和BG2矩阵，校验信息存储器的大小可分别降低39.1％和36.3％。FIG. 3 is a schematic diagram of a specific structure of a check information memory in the decoder of the present invention. Since the line weight of 5G LDPC codes is extremely irregular, there is a large difference between the line weights of each line. Usually the width of the memory needs to match the maximum line weight. When the minimum sum decoder is used for decoding, the width of the parity information memory can be expressed as

where q is the number of quantized bits of the check message. This design is wasteful for layers with lower row weights. Therefore, the present invention proposes a distributed storage method for the verification information storage, and the specific structure is shown in FIG. 2 . First, preset a threshold

Used to determine the size of the row weight of each layer. Second, for row weights less than or equal to

It stores all check messages output by its check nodes in the first sub-memory. For row weights greater than

For the check message output by each check node, the address message is stored in the second sub-memory, and the rest of the check messages are stored in the first sub-memory. It's worth noting that because the second submemory is only used for row weights greater than layer, so its depth is much smaller than the first sub-memory. Based on this, the resource consumption of the verification information storage can be further reduced. For example, for the BG1 matrix, we can use

Set to 15, at this time, the size of the parity information memory can be reduced by 15.2%; for the BG2 matrix, the If it is set to 8, the size of the verification information memory can be reduced by 13.7%. When combined with the layer merging technique, the size of the parity information memory can be reduced by 39.1% and 36.3% for the BG1 and BG2 matrices, respectively.

FIG. 4 is a schematic diagram of the shift structure of the soft message memory in the decoder of the present invention. Since the size of the internet network plays a leading role in the overall area, power consumption and delay of the decoder, in order to reduce its resource consumption, the present invention proposes two improvement methods. First, reduce the number of incoming and outgoing messages to the Internet. Taking the BG2 matrix as an example, FIG. 5 is a schematic structural diagram of the BG2 matrix. Since it contains 52 columns, the number of input message groups to read the internet is 52. Considering that the lower right corner (matrix I) of BG2 is an identity matrix, each iterative layer will only use a set of soft decision messages corresponding to this partial matrix in sequence. Based on this, the present invention independently stores the soft decision message corresponding to the partial matrix, and implements the partial memory by means of cyclic shift. The specific structure is shown in FIG. 4 . With this architecture, the storage addresses of the soft messages required by all iteration layers in this part can be fixed to the same one. Therefore, this part of the memory only outputs and inputs one set of data at a time, thereby greatly reducing the number of inputs and outputs of the Internet. For the BG2 matrix, the number of inputs to read the internet and the number of outputs to write to the internet can be reduced from 52 to 16. Second, in order to minimize the area and delay required to generate each output in the interconnected network, the input messages corresponding to each output in each layer are reordered in a way that minimizes the number of inputs required to generate each output. . This sorting is done offline and therefore does not consume hardware resources.

Embodiment: Take a 5G LDPC code defined by BG2 with a code length of 2600 and a code rate of 1/5 as an example to implement the decoder architecture disclosed in the present invention. The decoder is described in Verilog language, the RTL obtained is synthesized by Synopsys tool, and the technology adopted is TSMC 90nm CMOS technology. The comprehensive results show that after using the optimization method disclosed in the present invention, the working frequency of the decoder is increased from 121Mhz to 164MHz, the area is reduced from 1.831mm ² to 1.236mm ² , and the throughput rate is increased from 524Mbps to 947Mbps. For a more intuitive comparison, we also compared the throughput-to-power ratio. By using the optimization method disclosed in the present invention, the throughput-power consumption ratio of the decoder is increased from 286.1 Mbps/mm ² to 766.2 Mbps/mm ² , which is increased to 2.68 times.

The above is only a preferred embodiment of the present invention, but the protection scope of the present invention is not limited to this. Any person skilled in the art who is familiar with the technical scope disclosed by the present invention can easily think of changes and Substitutions should be covered within the protection scope of the present invention.

Claims (7)

1. a general high-throughput, low-complexity decoder architecture for 5G LDPC codes, adopts a layered decoding structure, and is characterized in that, comprises the following units: 1) a controller for generating all control signals in the decoder; 2) Soft message memory for storing the soft decision message of each bit. To be able to support massively parallel read and initialization operations, the memory is implemented by register banks; 3) A verification information memory, which is used to store the verification information calculated by each verification node. In order to support simultaneous read and write operations, the unit is implemented with dual-port random access memory (DRAM); 4) Read the Internet, which is used to read soft messages from the soft message memory, and select the maximum row weight corresponding to the current execution layer.

Group soft messages for output; 5) a shifter, which is shifted according to the shift factor corresponding to each group of soft-decision messages, so that the interior can be arranged in the correct order; 6) a variable node unit, used to generate a variable message that the variable node transmits to the check node; 7) a check node unit for generating a check message corresponding to each variable node; 8) a decompressor for converting the check message from a compressed form to an uncompressed form; 9) Write to the Internet, based on the currently generated

The group-updated soft message generates a message that is input into the soft message memory. 2. the decoder architecture of high throughput rate according to claim 1, low complexity, it is characterized in that, utilize the partial orthogonality of the base matrix of 5G LDPC code, two layers of orthogonal part are regarded as one layer to decode. As a result, the required number of clock cycles can be reduced, thereby increasing throughput. In addition, the depth of the verification message memory according to claim 1 can also be correspondingly reduced. 3. soft message memory according to claim 1, is characterized in that, in order to reduce the resource consumption that is input into the described read internet network of claim 1 and write internet network, the soft decision message corresponding to the expansion bit and corresponding Soft decision messages for core bits are stored separately. The memory for storing the soft-decision message corresponding to the extended bit is implemented by a shift architecture, so the storage address of the required data can be fixed. Based on this, this part of the memory only needs to input and output one set of data at a time. 4. The shifter of claim 1, wherein 1) The shift factor of each group of messages in the current layer is the shift coefficient of the column of the corresponding base matrix in the current layer minus the previous non-negative shift coefficient of the column. Therefore, the re-shifting required when writing the message to the soft message memory is omitted; 2) The input data needs to be reversely shifted according to the last shift coefficient of the column of its corresponding base matrix before being loaded into the soft message memory, to ensure the correctness of the position of each group of messages during the first shift; 3) The output data needs to be shifted according to the last shift coefficient of the column of the corresponding base matrix before output, so as to ensure that the output code words are sorted in the correct order. 5. The check node unit according to claim 1, wherein the output data is arranged in a compressed format. For example, for the minimum sum decoder, in each check node, only the sign bit of the check message, the minimum input variable message and its corresponding address, and the second small input variable message are output. 6. verification information memory according to claim 1, in order to reduce area consumption, adopts distributed structure to realize, it is characterized in that: 1) Preset a threshold

Used to determine the size of the row weight of each layer; 2) For row weight less than or equal to

layer, store all the check messages output by its check nodes in the first sub-memory; 3) For row weights greater than layer, for the check message output by each check node, the address message is stored in the second sub-memory, and the rest of the messages are stored in the first sub-memory; 4) The second sub-memory should only be used for row weights greater than

, so its depth is much smaller than the first sub-memory. 7. The reading internet network according to claim 1 and the writing internet network are characterized in that, in order to reduce the hardware resource consumption of the internet, according to the mode of minimizing the number of inputs required to generate each output, each Each output is reordered corresponding to the input message in each layer. The sorting is done offline and therefore does not consume hardware resources.

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