CN110838445A - Semiconductor device and method of forming the same - Google Patents

Abstract

The invention discloses a method for forming a semiconductor device, which comprises the following steps: providing a semiconductor substrate and a grid structure, wherein the grid structure is formed above the semiconductor substrate; etching the semiconductor substrate positioned at two sides of the grid structure to form a first groove; forming a source/drain in the first groove, wherein a region below the grid structure and between the source/drain is a channel; etching part of the source/drain or part of the semiconductor substrate to form a second groove, wherein the second groove is adjacent to one side of the rest of the source/drain, which is close to the grid structure; forming a diffusion barrier structure at the bottom of the second groove, wherein the ion type in the diffusion barrier structure is opposite to that in the source/drain, the top of the diffusion barrier structure is higher than the bottom of the source/drain, and the bottom of the diffusion barrier structure is not higher than the bottom of the source/drain; and forming a dielectric layer in the second groove. The diffusion barrier structure can effectively prevent current from leaking at the lower part of the channel and the lower part of the source/drain, avoid electric leakage and improve the performance of the semiconductor device.

Description

Semiconductor device and method of forming the same

technical field

The present invention relates to the field of semiconductor manufacturing, in particular to a semiconductor device and a method for forming the same.

Background technique

With the improvement of the integration of semiconductor devices, the size of the device is gradually reduced, and the size of the key structure is also reduced. If the width of the channel is narrowed, the short channel effect (SCE) occurs, and the normal function of the device cannot be satisfied.

At present, the source/drain on both sides of the channel are doped with ions, but due to the technical characteristics of doping, the ion concentration in the source/drain is not uniform, and the ion concentration in the lower part of the source/drain is lower than that in the upper part, and In the lower part of the source/drain near the channel, the ion concentration is lower. After a voltage is applied, it is easy to leak electricity, which reduces the performance of the semiconductor device.

Therefore, there is an urgent need for a method for forming a semiconductor device and a semiconductor device capable of solving device leakage.

SUMMARY OF THE INVENTION

Embodiments of the present invention disclose a semiconductor device and a method for forming the same. A diffusion barrier structure is formed between the lower part of the source/drain and the lower part of the channel to avoid leakage of the semiconductor device.

The invention discloses a method for forming a semiconductor device, comprising: providing a semiconductor substrate and a gate structure, wherein the gate structure is formed above the semiconductor substrate; and etching the semiconductor substrate on both sides of the gate structure to form a first recess groove; source/drain is formed in the first groove, the area under the gate structure and between the source/drain is the channel; part of the source/drain or part of the semiconductor substrate is etched to form the second groove, the second The groove is adjacent to the side of the remaining source/drain close to the gate structure; a diffusion barrier structure is formed at the bottom of the second groove, and the ion type in the diffusion barrier structure is opposite to the ion type in the source/drain, and the diffusion barrier structure The top portion is higher than the lower portion of the source/drain, the bottom portion of the diffusion barrier structure is not higher than the lower portion of the source/drain; and a dielectric layer is formed in the second groove.

According to one aspect of the invention, the ion concentration in the diffusion barrier structure is lower than that in the source/drain adjacent to the diffusion barrier structure, and the ion concentration in the diffusion barrier structure is higher than the ion concentration in the channel.

According to one aspect of the present invention, the distance between the top of the source/drain and the bottom of the source/drain is l ₁ , the distance between the top of the diffusion barrier structure and the bottom of the source/drain is l ₂ , 2≤l ₁ :l ₂ ≤5 .

According to one aspect of the present invention, the width dimension of the diffusion barrier structure ranges from 15 nm to 25 nm.

According to one aspect of the present invention, the process steps of forming the diffusion barrier structure include: after forming the second groove, ion implanting the remaining source/drain or semiconductor substrate at the bottom of the second groove to form the diffusion barrier region; and The diffusion barrier region is annealed to form a diffusion barrier structure.

According to one aspect of the present invention, the process of performing the ion implantation includes a penetration resistant ion implantation process.

According to one aspect of the present invention, the direction of ion implantation is perpendicular to the top surface of the gate structure.

According to an aspect of the present invention, the ion species in the diffusion barrier structure include: boron ion, phosphorus ion or arsenic ion, and the ion concentration in the diffusion barrier structure ranges from 5×10 ¹² /cm ³ to 3×10 ¹³ /cm ³ .

According to one aspect of the present invention, the ions in the diffusion barrier structure further include: one or more combinations of C, Ge, N, and F ions.

According to one aspect of the present invention, the annealing process is a laser pulse thermal annealing process, and the conditions of the annealing process include: the annealing temperature ranges from 900°C to 1100°C, and the annealing time ranges from 10s to 100s.

According to one aspect of the present invention, after the source/drain is formed and before the second groove is formed, the method further includes: forming an interlayer dielectric layer between adjacent gate structures; and etching away part of the interlayer dielectric layer to expose the source /drain or semiconductor substrate to form a second groove.

According to an aspect of the present invention, after the source/drain is formed and before the interlayer dielectric layer is formed, the method further includes forming spacers on both sidewalls of the gate structure.

According to one aspect of the present invention, the process of forming the source/drain includes an epitaxial growth process.

According to an aspect of the present invention, the material of the dielectric layer formed in the second groove includes Si, SiGe, or SiC.

Correspondingly, the present invention also provides a semiconductor device, comprising: a semiconductor substrate, a source/drain, a channel and a gate structure, the gate structure is arranged above the semiconductor substrate, and the source/drain is formed on both sides of the gate structure In the semiconductor substrate of , the channel is formed under the gate structure and between the source/drain; the diffusion barrier structure, the diffusion barrier structure is adjacent to the side of the source/drain close to the gate structure, the ion type in the diffusion barrier structure Contrary to the type of ions in the source/drain, the top of the diffusion barrier structure is higher than the bottom of the source/drain, the bottom of the diffusion barrier structure is not higher than the bottom of the source/drain; and a dielectric layer, the dielectric layer is disposed above the diffusion barrier structure .

According to one aspect of the invention, the ion concentration in the diffusion barrier structure is lower than that in the source/drain adjacent to the diffusion barrier structure, and the ion concentration in the diffusion barrier structure is higher than the ion concentration in the channel.

According to one aspect of the present invention, the distance between the top of the source/drain and the bottom of the source/drain is l ₁ , the distance between the top of the diffusion barrier structure and the bottom of the source/drain is l ₂ , 2≤l ₁ :l ₂ ≤5 .

According to one aspect of the present invention, the width dimension of the diffusion barrier structure ranges from 15 nm to 25 nm.

According to an aspect of the present invention, the ion species in the diffusion barrier structure include: boron ion, phosphorus ion or arsenic ion, and the ion concentration in the diffusion barrier structure ranges from 5×10 ¹² /cm ³ to 3×10 ¹³ /cm ³ .

According to one aspect of the present invention, the ions in the diffusion barrier structure further include: one or more combinations of C, Ge, N, and F ions.

Compared with the existing technical solutions, the technical solutions of the present invention have the following advantages:

In the embodiment of the present invention, when the semiconductor device is formed, a diffusion barrier structure is formed at the bottom of the second groove, the ion type in the diffusion barrier structure is opposite to that in the source/drain, and the ion type in the diffusion barrier structure is opposite to that in the source/drain. Contrary to the type, it can inhibit the impurity ions located in the lower part of the source/drain from diffusing into the channel, thereby avoiding the formation of an ion diffusion region between the lower part of the channel and the lower part of the source/drain, and ensuring that after the voltage is applied, the current does not flow from the source/drain and The lower part of the channel leaks. At the same time, the top of the diffusion barrier structure is higher than the bottom of the source/drain, and the bottom of the diffusion barrier structure is not higher than the bottom of the source/drain. Since the leakage current mostly occurs in the lower part of the source/drain and the channel, it is formed at this position. The diffusion barrier structure will not affect the normal migration of electrons, and can also ensure that the leakage of current is blocked.

Further, the ion concentration in the diffusion barrier structure is lower than that in the source/drain adjacent to the diffusion barrier structure, and the ion concentration in the diffusion barrier structure is higher than that in the channel. The ion concentration in the diffusion barrier structure is lower than the ion concentration in the source/drain adjacent to the diffusion barrier structure, so as to ensure that the function of the source/drain is not inhibited, and at the same time, the purpose of blocking current leakage is achieved.

Correspondingly, in the semiconductor device prepared in the embodiment of the present invention, the ion type in the diffusion barrier structure is opposite to the ion type in the source/drain, and the diffusion barrier structure is opposite to the ion type in the source/drain, which can suppress the ion type located at the lower part of the source/drain. Impurity ions diffuse into the channel so that current does not leak from the source/drain and the lower part of the channel after a voltage is applied.

Description of drawings

1-7 are schematic cross-sectional structures of a method for forming a semiconductor device according to an embodiment of the present invention.

Detailed ways

As mentioned above, there is a problem in the existing semiconductor devices that the current easily leaks in the source/drain and the lower part of the channel.

After research, it is found that the reason for the above problem is that the ion concentration in the lower part of the source/drain is lower than the ion concentration in the upper part, and the impurity ions in the lower part of the source/drain are easy to diffuse into the channel to form an impurity diffusion region. When a voltage is applied, current flows between the magazine diffusion regions, causing leakage and reducing the performance of the semiconductor device.

In order to solve this problem, the present invention provides a method for forming a semiconductor device. A diffusion barrier structure is formed between the lower part of the source/drain and the lower part of the channel, which can effectively avoid leakage and improve the performance of the device.

Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be understood that the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments should not be construed as limiting the scope of the invention unless specifically stated otherwise.

In addition, it should be understood that, for ease of description, the dimensions of various components shown in the drawings are not necessarily drawn to an actual scale relationship, for example, the thickness or width of some layers may be exaggerated relative to other layers.

The following description of exemplary embodiments is illustrative only and is not intended to limit the invention, its application or use in any way.

Techniques, methods, and apparatuses known to those of ordinary skill in the relevant art may not be discussed in detail, but where applicable, these techniques, methods, and apparatuses should be considered part of this specification.

It should be noted that like numerals and letters refer to like items in the following figures, so once an item is defined or described in one figure, it will not need to be further explained in the description of subsequent figures discuss.

Referring to FIG. 1 , a gate structure 110 is formed on a semiconductor substrate 100 .

The semiconductor substrate 100 serves as a process basis for forming semiconductor devices. The material of the semiconductor substrate 100 is at least one of the following materials: polysilicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), and silicon-on-insulator (S-SiGeOI) Silicon germanium (SiGeOI), etc. In the embodiment of the present invention, the material of the semiconductor substrate 100 is polysilicon, and the semiconductor substrate 100 also includes other structures, such as: metal plugs, metal connection layers, dielectric layers and other structures, or includes these structures. other semiconductor devices, which are not specifically limited here.

It should be noted that, in other embodiments of the present invention, 100 may also be a fin formed by a semiconductor substrate, and a dielectric layer or a sacrificial layer, etc. may also be formed between the semiconductor substrate 100 and the gate structure 110 . No specific restrictions are made here. Specifically, in the embodiment of the present invention, 100 is a fin formed by a semiconductor substrate.

The gate structure 110 plays a control role. The gate structure 110 may include a gate, a high-k dielectric layer and/or a work function layer, etc., which are not specifically limited here.

Referring to FIG. 2 , source/drain 120 is formed.

After subsequent voltage application, the source/drain 120 realizes circuit conduction. The process steps of forming the source/drain 120 include: etching the semiconductor substrate 100 on both sides of the gate structure 110 to form a first groove (not shown), and then forming the source/drain 120 in the first groove.

The source/drain 120 is formed inside the semiconductor substrate 100 on both sides of the gate structure 110. The cross-sectional shape of the source/drain 120 is related to the type of the MOS device to be finally formed. The cross-sectional shape of the source/drain 120 includes a Σ-shape or a U-shape. No specific restrictions are made here. Likewise, the material of the source/drain 120 is also related to the specific type of MOS device, which is not specifically limited here.

In an embodiment of the present invention, the process of forming the source/drain 120 includes an epitaxial growth process. The source/drain 120 can be made more dense using an epitaxial growth process.

Generally, after the source/drain 120 is formed, an annealing process for the source/drain 120 is also included.

The lower portion of the gate structure 110 and the region between the source/drain 120 is a channel region (not shown) for electron transfer.

Referring to FIG. 3 , spacers 130 are formed on both sides of the gate structure 110 , and an interlayer dielectric layer 140 is formed between adjacent gate structures 110 .

The sidewalls 130 are formed to occupy space for the subsequent formation of the second groove. The material of the side wall 130 includes one or a combination of two of SiN and SiON. Specifically, in the embodiment of the present invention, the material of the side wall 130 is SiN.

Meanwhile, the lower portion of the sidewall spacer 130 may all be in contact with the source/drain 120, or may be in contact with a part of the source/drain 120 and a part of the semiconductor substrate 100 at the same time, which is not specifically limited here. Specifically, in the embodiment of the present invention, all the lower portions of the sidewall spacers 130 are in contact with the source/drain 120 .

It should be noted that, in other embodiments of the present invention, the sidewall spacers 130 may also be formed before the first grooves are formed, and then the first grooves and the source/drain 120 are formed.

The interlayer dielectric layer 140 is formed to isolate the adjacent gate structures 110 . In the embodiment of the present invention, the material of the interlayer dielectric layer 140 is SiO ₂ .

It should be noted that, in another embodiment of the present invention, the sidewall spacers 130 may not be formed, but the interlayer dielectric layer 140 may be formed directly between the adjacent gate structures 110 after the source/drain 120 is formed.

Referring to Figure 4, the sidewall spacers are removed by etching.

The sidewalls are removed in preparation for the formation of the second groove 10 . In the embodiment of the present invention, after the spacer is removed, part of the source/drain 120 or part of the semiconductor substrate 100 is exposed. In the embodiment of the present invention, since all the lower portions of the sidewall spacers are in contact with the source/drain 120 , after the sidewall spacers are removed, all the exposed portions are the source/drain 120 . In another embodiment of the present invention, after the spacers are removed, part of the source/drain 120 and part of the semiconductor substrate 100 are exposed.

The process of etching and removing the sidewall spacers is a conventional process in semiconductor production. In the embodiment of the present invention, the process of etching the sidewall spacers includes a plasma dry etching process. During etching, the process has good directionality and is easy to control, and will not cause damage to the sidewall of the gate structure 110 . Obviously, the dry etching process has a certain etching selectivity ratio for the sidewall spacer and the interlayer dielectric layer 140 to ensure that the interlayer dielectric layer 140 is not removed by etching when the sidewall spacer is etched.

In yet another embodiment of the present invention, since no spacers are formed, after the interlayer dielectric layer 140 is formed, part of the interlayer dielectric layer 140 close to the two sidewalls of the gate structure 110 is directly etched to form the second groove 10. The source/drain 120 or the semiconductor substrate 100 is exposed.

Referring to FIG. 5 , a portion of the source/drain 120 or a portion of the semiconductor substrate 100 is etched to form the second groove 10 .

The second groove 10 is formed for the subsequent formation of the diffusion isolation structure. The second recess 10 is formed adjacent to the side of the remaining source/drain 120 close to the gate structure 110 .

The process of etching to form the second groove 10 is the same as the process of etching the sidewall spacers.

Referring to FIG. 6 , a diffusion barrier structure 150 is formed at the bottom of the second groove 10 .

The formed diffusion barrier structure 150 is used to prevent current from leaking from the lower part of the source/drain and the lower part of the channel after a voltage is applied, so as to prevent leakage.

Generally, after the source/drain 120 is formed, the source/drain 120 needs to be ion implanted. However, the distribution of ions in the source/drain 120 is not uniform, the upper part of the source/drain 120 has a higher ion concentration and the lower part has a lower ion concentration. In a method of forming a semiconductor device, ions in the lower part of the source/drain 120 are easily diffused to the channel region, and an impurity diffusion region is formed between the lower part of the source/drain 120 and the lower part of the channel. When a voltage is applied, current flows between the impurity diffusion regions, resulting in leakage of current. Therefore, after the diffusion barrier structure 150 is formed, the leakage of electrons is blocked, and the performance of the semiconductor device is improved.

Therefore, the embodiment of the present invention has certain requirements on the position of the diffusion barrier structure 150 . Specifically, in the embodiment of the present invention, the top of the diffusion barrier structure 150 is higher than the bottom of the source/drain 120 , and the bottom of the diffusion barrier structure 150 is not higher than the bottom of the source/drain 120 . If the top of the diffusion barrier structure 150 is too high, normal circuit conduction will be hindered. And in the embodiment of the present invention, the distance ruler between the top of the source/drain 120 and the bottom is l ₁ , the distance between the top of the diffusion barrier structure 150 and the bottom of the source/drain 120 is l ₂ , 2≤l ₁ :l ₂ ≤5. Specifically, in this embodiment of the present invention, l ₁ :l ₂ =2. In another embodiment of the present invention, l ₁ :l ₂ =5. The positional relationship between the top and bottom of the diffusion barrier structure 150 not only ensures the normal migration of electrons in the channel when a voltage is applied, but also prevents current leakage.

It should be noted that since the shape of the source/drain 120 is not fixed, here, the bottom of the source/drain 120 refers to the lowest position of the source/drain 120, as shown in FIG. 6 .

Meanwhile, the embodiment of the present invention also has certain requirements on the width of the diffusion barrier structure 150 . The width dimension of the diffusion barrier structure 150 is w, 15nm≤w≤25nm. Specifically, in the embodiment of the present invention, w=15 nm. In another embodiment of the present invention, w=25nm. In yet another embodiment of the present invention, w=20 nm.

In the embodiments of the present invention, there are many methods for forming the diffusion barrier structure 150 . Specifically, in the embodiment of the present invention, after the second groove 10 is formed, ion implantation is performed on the remaining source/drain 120 or the semiconductor substrate 100 at the bottom of the second groove 10 to form a diffusion barrier region (not shown). ), and then annealing the diffusion barrier region to form the diffusion barrier structure 150 . In another embodiment of the present invention, after forming the second groove 10, a part of the material layer (not shown) is formed at the bottom of the second groove 10, and then ion implantation is performed on the material layer to form the diffusion barrier region ( not shown), the diffusion barrier region is then annealed to form the diffusion barrier structure 150 .

Specifically, in the embodiment of the present invention, the process of performing ion implantation on the remaining source/drain 120 at the bottom of the second groove 10 or the semiconductor substrate 100 is an anti-punchthrough implantation process (Anti-punchthrough Implantation, APT). In addition, during the ion implantation, a vertical implantation method is adopted, that is, the angle between the direction of the ion implantation and the top of the gate structure 110 is 90°. This vertical implantation prevents ions from diffusing into the source/drain 120 , the channel or the inside of the gate structure 110 . The direction and location of ion implantation are shown in FIG. 6 .

The implanted ion species and implant power are related to the type of MOS device formed. In an embodiment of the present invention, the type of ions in the source/drain 120 is opposite to the type of ions in the diffusion barrier structure 150 . The opposite ion type exists in the diffusion barrier structure 150 as in the source/drain 120, so that the diffusion barrier structure 150 can suppress the diffusion of impurity ions in the source/drain 120 to the channel and avoid formation between the lower part of the source/drain 120 and the lower part of the channel Impurity ion diffusion region, so as to prevent the current from leaking from the lower part of the source/drain 120 after the voltage is applied, so as to prevent the leakage.

In the embodiment of the present invention, if it is an NMOS device or an N-type FinFET structure, the implanted ions are boron (B) ions. less than or equal to 20Kv, that is, the range includes the endpoint values, and the following range expressions have the same meaning here), the concentration range of B ions is 5×10 ¹² /cm ³ to 3×10 ¹³ /cm ³ . If it is a PMOS device or a P-type FinFET structure, the implanted ions are phosphorus (P) ions or arsenic (As) ions. The conditions of ion implantation include: power 35Kv ~ 75Kv, phosphorus (P) ions or arsenic (As) ions The concentration range is 5×10 ¹² /cm ³ to 3×10 ¹³ /cm ³ . Specifically, in the embodiment ^of the present invention, the structure is an N ^- type FinFET structure, and the implanted ions are boron (B) ions. In another embodiment of the present invention, the structure is a P-type FinFET structure, the implanted ions are phosphorus (P) ions, and the conditions of the ion implantation include: a power of 35Kv, and a phosphorus (P) ion concentration of 3×10 ¹³ /cm ³ .

In the embodiment of the present invention, the diffusion barrier structure 150 further includes other impurity ions, such as one or more combinations of C, Ge, N, and F ions. These ions can fill in the gaps of atoms, improve the bonding force between atoms, increase the strength of the diffusion barrier structure 150, and also avoid the breaking of chemical bonds during annealing. Specifically, in the embodiment of the present invention, the diffusion barrier structure 150 further includes C and F. In another embodiment of the present invention, the diffusion barrier structure 150 further includes N and Ge. In yet another embodiment of the present invention, the diffusion barrier structure 150 contains F.

In an embodiment of the present invention, the ion concentration of the diffusion barrier structure 150 is lower than the ion concentration in the source/drain 120 adjacent to the diffusion barrier structure 150 . This does not inhibit the realization of the source/drain 120 function. Meanwhile, the ion concentration of the diffusion barrier structure 150 is higher than that in the channel.

The process of annealing the diffusion barrier region is a laser pulse thermal annealing process. The laser pulse thermal annealing process can achieve the goal of rapid heating and ion activation in a short time, and can reduce the degree of diffusion of other impurities. In the embodiment of the present invention, the annealing temperature ranges from 900° C. to 1100° C., and the annealing time ranges from 10 s to 100 s. Specifically, in the embodiment of the present invention, the annealing temperature is 900° C., and the annealing time is 10 s. In another embodiment of the present invention, the annealing temperature is 1100° C., and the annealing time is 100 s.

Referring to FIG. 7 , a dielectric layer 160 is formed in the second groove 10 .

The purpose of forming the dielectric layer 160 is to fill the second groove 10 to complete the structure of the device. Since the formation of the second groove 10 needs to remove part of the source/drain 120 , in the embodiment of the present invention, the formed dielectric layer 160 needs to be related to the type of the device or structure and match the type of the source/drain 120 . If the device is an NMOS device or an N-type FinFET structure, the material of the dielectric layer 160 is SiC, which contains P ions in a concentration range of 5×10 ¹⁸ /cm ³ to 6×10 ¹⁹ /cm ³ . If the device is a PMOS device or a P-type FinFET structure, the material of the dielectric layer 160 is Si and/or SiGe, and the concentration of B ions contained therein ranges from 2×10 ¹⁸ /cm ³ to 3×10 ¹⁹ /cm ³ . Specifically, in the embodiment of the present invention, the device has an N-type FinFET structure, the material of the dielectric layer 160 is SiC, and the concentration of P ions contained therein is 5×10 ¹⁸ /cm ³ . In another embodiment of the present invention, the device has a P-type FinFET structure, and the material of the dielectric layer 160 is Si and/or SiGe, which contains B ions with a concentration of 2×10 ¹⁸ /cm ³ .

It should be noted that, in the embodiment of the present invention, after the dielectric layer 160 is formed, an interlayer dielectric layer also needs to be formed to fill the second groove 10 .

To sum up, the embodiments of the present invention disclose a method for forming a semiconductor device. A diffusion barrier structure is formed between the lower part of the source/drain and the channel, which can prevent the leakage of current after voltage is applied, avoid leakage, and improve the performance of semiconductor devices.

Correspondingly, please continue to refer to FIG. 7 , the present invention further provides a semiconductor device including: a semiconductor substrate 100 , a source/drain 120 , a channel (not shown) and a gate structure 110 .

The gate structure 110 is disposed above the semiconductor substrate 100 , and the source/drain 120 is formed in the semiconductor substrate 100 on both sides of the gate structure 110 .

The function and material of the semiconductor substrate 100 , the function and material of the source/drain 120 , the position of the channel and the function of the gate structure 110 are referred to above.

In the embodiment of the present invention, a diffusion barrier structure 150 is further included. The diffusion barrier structure 150 can prevent impurity ions in the source/drain 120 from diffusing into the channel, preventing current from leaking from the channel and the lower part of the source/drain after voltage is applied, and preventing current leakage.

The embodiment of the present invention has certain requirements on the position of the diffusion barrier structure 150 . The diffusion barrier structure 150 is adjacent to a side of the source/drain 120 close to the gate structure 110 . Specifically, in the embodiment of the present invention, the top of the diffusion barrier structure 150 is higher than the bottom of the source/drain 120 , and the bottom of the diffusion barrier structure 150 is not higher than the bottom of the source/drain 120 .

And in the embodiment of the present invention, the distance ruler between the top of the source/drain 120 and the bottom is l ₁ , the distance between the top of the diffusion barrier structure 150 and the bottom of the source/drain 120 is l ₂ , 2≤l ₁ :l ₂ ≤5. Specifically, in this embodiment of the present invention, l ₁ :l ₂ =2. In another embodiment of the present invention, l ₁ :l ₂ =5. The positional relationship between the top and bottom of the diffusion barrier structure 150 not only ensures the normal migration of electrons in the channel when a voltage is applied, but also prevents electric leakage.

The embodiment of the present invention also has certain requirements on the width of the diffusion barrier structure 150 . The width dimension of the diffusion barrier structure 150 is w, 15nm≤w≤25nm. Specifically, in the embodiment of the present invention, w=15 nm. In another embodiment of the present invention, w=25nm. In yet another embodiment of the present invention, w=20 nm.

In an embodiment of the present invention, the ion concentration of the diffusion barrier structure 150 is lower than the ion concentration in the source/drain 120 adjacent to the diffusion barrier structure 150, while being higher than the ion concentration in the channel.

In the embodiment of the present invention, if it is an NMOS device or an N-type FinFET structure, the implanted ions are boron (B) ions, and the conditions of ion implantation include: power 12Kv～20Kv, and the concentration range of B ions is 5×10 ¹² /cm ³ to 3×10 ¹³ /cm ³ . If it is a PMOS device or a P-type FinFET structure, the implanted ions are phosphorus (P) ions or arsenic (As) ions. The conditions of ion implantation include: power 35Kv ~ 75Kv, phosphorus (P) ions or arsenic (As) ions The concentration range is 5×10 ¹² /cm ³ to 3×10 ¹³ /cm ³ . Specifically, in the embodiment ^of the present invention, the structure is an N ^- type FinFET structure, and the implanted ions are boron (B) ions. In another embodiment of the present invention, the structure is a P-type FinFET structure, the implanted ions are phosphorus (P) ions, and the conditions of the ion implantation include: a power of 35Kv, and a phosphorus (P) ion concentration of 3×10 ¹³ /cm ³ .

In the embodiment of the present invention, the diffusion barrier structure 150 further includes other impurity ions, such as one or more combinations of C, Ge, N, and F ions. These ions can fill in the gaps of atoms, improve the bonding force between atoms, increase the strength of the diffusion barrier structure 150, and also avoid the breaking of chemical bonds during annealing. Specifically, in the embodiment of the present invention, the diffusion barrier structure 150 further includes C and F. In another embodiment of the present invention, the diffusion barrier structure 150 further includes N and Ge. In yet another embodiment of the present invention, the diffusion barrier structure 150 contains F.

Likewise, the type of ions in the diffusion barrier structure 150 is the opposite of the type of ions in the source/drain 120 . The diffusion barrier structure 150 has the opposite ion type to that in the source/drain 120, so that the diffusion barrier structure 150 can suppress the diffusion of ions in the source/drain 120 to the channel, so that after the voltage is applied, the current does not leak from the lower part of the source/drain 120, Avoid leakage.

The embodiment of the present invention further includes a dielectric layer 160 . In order to fill the second groove 10, the dielectric layer 160 completes the structure of the device. For the material of the dielectric layer 160 and the type of ions contained therein, please refer to the above.

To sum up, the embodiment of the present invention discloses a semiconductor device. A diffusion barrier structure is formed between the lower part of the source/drain and the channel, which can prevent the leakage of current after voltage is applied, avoid leakage, and improve the performance of the semiconductor device. performance.

So far, the present invention has been described in detail. Some details that are well known in the art have not been described in order to avoid obscuring the concept of the present invention. Those skilled in the art can fully understand how to implement the technical solutions disclosed herein based on the above description.

While some specific embodiments of the present invention have been described in detail by way of example, those skilled in the art will appreciate that the above examples are provided for illustration only and not for the purpose of limiting the scope of the invention. Those skilled in the art will appreciate that modifications may be made to the above embodiments without departing from the scope and spirit of the present invention. The scope of the invention is defined by the appended claims.

Claims (20)

1. A method of forming a semiconductor device, comprising:

providing a semiconductor substrate and a gate structure, wherein the gate structure is formed above the semiconductor substrate;

etching the semiconductor substrate positioned at two sides of the grid structure to form a first groove;

forming a source/drain in the first groove, wherein a region below the grid structure and between the source/drain is a channel;

etching part of the source/drain or part of the semiconductor substrate to form a second groove, wherein the second groove is adjacent to one side, close to the grid structure, of the rest of the source/drain;

forming a diffusion barrier structure at the bottom of the second groove, wherein the ion type in the diffusion barrier structure is opposite to that in the source/drain, the top of the diffusion barrier structure is higher than the bottom of the source/drain, and the bottom of the diffusion barrier structure is not higher than the bottom of the source/drain; and

and forming a dielectric layer in the second groove.

2. The method according to claim 1, wherein a concentration of ions in the diffusion barrier structure is lower than a concentration of ions in the source/drain adjacent to the diffusion barrier structure, and wherein a concentration of ions in the diffusion barrier structure is higher than a concentration of ions in the channel.

3. The method of claim 1, wherein a distance between the top of the source/drain and the bottom of the source/drain is/₁The distance between the top of the diffusion barrier structure and the bottom of the source/drain is l₂，2≤l₁:l₂≤5。

4. The method of claim 3, wherein a width dimension of the diffusion barrier structure is in a range of 15nm to 25 nm.

5. The method of claim 1, wherein the process step of forming the diffusion barrier structure comprises:

after the second groove is formed, carrying out ion implantation on the source/drain or the semiconductor substrate which is positioned at the bottom of the second groove and is remained so as to form a diffusion barrier region; and

and carrying out annealing treatment on the diffusion barrier region to form the diffusion barrier structure.

6. The method according to claim 5, wherein the ion implantation process comprises a penetration-preventing ion implantation process.

7. The method of claim 6, wherein the direction of the ion implantation is perpendicular to a top surface of the gate structure.

8. The method of claim 5, wherein the ion species in the diffusion barrier structure comprises: boron ions, phosphorus ions or arsenic ions, the concentration range of the ions in the diffusion barrier structure is 5 x 10¹²/cm³～3×10¹³/cm³。

9. The method of claim 8, wherein the ions in the diffusion barrier structure further comprise: C. one or more combinations of Ge, N and F ions.

10. The method as claimed in claim 5, wherein the annealing process is a laser pulse thermal annealing process, and the conditions of the annealing process include: the annealing temperature range is 900-1100 ℃, and the annealing time range is 10-100 s.

11. The method of claim 1, wherein after forming the source/drain and before forming the second recess, further comprising:

forming an interlayer dielectric layer between the adjacent grid structures; and

and etching and removing part of the interlayer dielectric layer to expose the source/drain or the semiconductor substrate so as to form the second groove.

12. The method of claim 11, further comprising forming spacers on two sidewalls of the gate structure after forming the source/drain and before forming the interlayer dielectric layer.

13. The method of claim 1, wherein the process of forming the source/drain comprises an epitaxial growth process.

14. The method of claim 1, wherein a material forming the dielectric layer in the second recess comprises Si, SiGe, or SiC.

15. A semiconductor device, comprising:

the semiconductor device comprises a semiconductor substrate, a source/drain, a channel and a grid structure, wherein the grid structure is arranged above the semiconductor substrate, the source/drain is formed in the semiconductor substrate on two sides of the grid structure, and the channel is formed below the grid structure and positioned between the source/drain;

the diffusion barrier structure is adjacent to one side, close to the grid structure, of the source/drain, the ion type in the diffusion barrier structure is opposite to that in the source/drain, the top of the diffusion barrier structure is higher than the bottom of the source/drain, and the bottom of the diffusion barrier structure is not higher than the bottom of the source/drain; and

and the dielectric layer is arranged above the diffusion barrier structure.

16. The semiconductor device according to claim 15, wherein a concentration of ions in the diffusion barrier structure is lower than a concentration of ions in the source/drain adjacent to the diffusion barrier structure, and wherein a concentration of ions in the diffusion barrier structure is higher than a concentration of ions in the channel.

17. According to claim 15The semiconductor device, wherein a distance between the top of the source/drain and the bottom of the source/drain is l₁The distance between the top of the diffusion barrier structure and the bottom of the source/drain is l₂，2≤l₁:l₂≤5。

18. The semiconductor device of claim 17, wherein the diffusion barrier structure has a width dimension in a range of 15nm to 25 nm.

19. The method of claim 15, wherein the ion species in the diffusion barrier structure comprises: boron ions, phosphorus ions or arsenic ions, wherein the concentration range of the ions in the diffusion barrier structure is as follows: 5X 10¹²/cm³～3×10¹³/cm³。

20. The method of forming a semiconductor device according to claim 19, wherein the ions in the diffusion barrier structure further comprise: C. one or more combinations of Ge, N and F ions.

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