CN110931050B

CN110931050B - disk unit

Info

Publication number: CN110931050B
Application number: CN201910025320.5A
Authority: CN
Inventors: 下川英夫; 吉田贤治
Original assignee: Toshiba Corp; Toshiba Electronic Devices and Storage Corp
Current assignee: Toshiba Corp; Toshiba Electronic Devices and Storage Corp
Priority date: 2018-09-19
Filing date: 2019-01-11
Publication date: 2021-09-10
Anticipated expiration: 2039-01-11
Also published as: US10657995B2; JP7043377B2; US20200090690A1; CN110931050A; JP2020047344A

Abstract

Embodiments provide a magnetic disk device with high performance. A magnetic disk device of an embodiment includes a magnetic disk having a plurality of tracks, a 1 st actuator and a 2 nd actuator, and a control circuit. The magnetic disk has a plurality of tracks. The control circuit determines the 1 st sector number, which is the number of writable sectors of the 1 st track among the plurality of tracks, and writes the 2 nd data of a size corresponding to the 1 st sector number among the 1 st data received from the host into the 1 st track using the 1 st actuator. The control circuit determines the number of writable sectors of a 2 nd track different from the 1 st track among the plurality of tracks, that is, the 2 nd sector number, and writes, to the 2 nd track, the 3 rd data of the 1 st data having a size corresponding to the 2 nd sector number received after the 2 nd data, using the 2 nd actuator.

Description

Magnetic disk device

RELATED APPLICATIONS

The present application has priority to application based on japanese patent application No. 2018-175240 (application date: 2018, 9/19). The present application includes the entire contents of the base application by reference to the base application.

Technical Field

The present embodiment relates to a magnetic disk device.

Background

There is known a magnetic disk device including two or more actuators capable of moving two or more magnetic heads independently.

Disclosure of Invention

One embodiment provides a high-performance magnetic disk device.

According to one embodiment, a magnetic disk device includes a magnetic disk, a 1 st magnetic head, a 2 nd magnetic head, a 1 st actuator, a 2 nd actuator, a buffer memory, and a control circuit. The magnetic disk has a plurality of tracks. The 2 nd head is different from the 1 st head. The 1 st actuator moves the position of the 1 st head. The 2 nd actuator is an actuator different from the 1 st actuator for moving the position of the 2 nd head. The buffer memory receives the 1 st data from the host. The control circuit determines the 1 st sector number, which is the number of writable sectors that the 1 st track of the plurality of tracks has, and writes the 2 nd data of a size corresponding to the 1 st sector number of the 1 st data to the 1 st track using the 1 st actuator. The control circuit determines the number of writable sectors of a 2 nd track different from the 1 st track among the plurality of tracks, that is, the 2 nd sector number, and writes, to the 2 nd track, the 3 rd data of the 1 st data having a size corresponding to the 2 nd sector number received after the 2 nd data, using the 2 nd actuator.

Drawings

Fig. 1 is a diagram showing an example of the configuration of a magnetic disk device according to the embodiment.

Fig. 2 is a diagram showing an example of the configuration of a magnetic disk according to the embodiment.

Fig. 3 is a diagram for explaining the track of the magnetic head according to the embodiment.

Fig. 4 is a diagram for explaining an outline of a data distribution method implemented by the control circuit of the embodiment.

Fig. 5 is a flowchart for explaining the operation of the magnetic disk device according to the embodiment of the write command (write command).

Fig. 6 is a flowchart for explaining a writing process using the 1 st actuator according to the embodiment.

Fig. 7 is a flowchart for explaining a write process using the 2 nd actuator according to the embodiment.

Fig. 8 is a diagram for explaining the timing of writing data in each track according to the embodiment.

Fig. 9 is a flowchart for explaining the operation of the disk device according to the embodiment in response to a read command (read command).

Fig. 10 is a flowchart for explaining a read process using the actuator 1 according to the embodiment.

Fig. 11 is a flowchart for explaining a read process using the actuator 2 of the embodiment.

Fig. 12 is a diagram for explaining the timing (timing) of reading out each track data according to the embodiment.

Fig. 13 is a diagram for explaining an example of an allocation (allocate) method of a region in the buffer memory according to the embodiment.

Fig. 14 is a diagram for explaining another example of the allocation method of the area in the buffer memory according to the embodiment.

Fig. 15 is a schematic diagram for explaining an embodiment of SMR.

Fig. 16 is a schematic diagram for explaining an example of a plurality of bands of the embodiment.

Detailed Description

The magnetic disk device according to the embodiment will be described in detail below with reference to the drawings. The present invention is not limited to the embodiments.

(embodiment mode)

Fig. 1 is a diagram showing an example of the configuration of a magnetic disk device 1 according to the embodiment. As shown in fig. 1, the magnetic disk apparatus 1 includes two magnetic disks 101, two pairs of magnetic heads 102 for reading and writing data, two actuators 104 for moving the magnetic heads 102 of the different pairs, and the like.

The two magnetic disks 101 include a magnetic disk 101a and a magnetic disk 101 b. The two pairs of heads 102 include 1 pair of

heads

102a and 1 pair of heads 102 b. The two actuators 104 include a 1 st actuator 104a and a 2 nd actuator 104 b.

The two magnetic disks 101 are attached to a rotary shaft 103 of a Spindle motor (Spindle motor) at a predetermined pitch in an axial direction of the rotary shaft 103, and are integrally rotated at the same rotational speed by rotational driving of the rotary shaft 103.

The number of the magnetic disks 101 included in the magnetic disk device 1 is not limited to 2.

Fig. 2 is a diagram showing an example of the configuration of the magnetic disk 101 according to the embodiment. The magnetic disk 101 has magnetic materials on both sides, and servo information is written by a servo writer or the like before shipment. The servo information is, for example, a Burst pattern (Burst pattern). Fig. 2 shows Servo zones (Servo zones) 200a arranged radially as an example of the arrangement of the Servo zones in which Servo information is written. A plurality of tracks 200b of concentric circles are provided at predetermined intervals in the radial direction of the magnetic disk 101. A plurality of sectors are continuously formed on the circumference of each track 200 b. Each sector has a magnetic region, and data can be freely rewritten.

The description will be made with reference to fig. 1.

The magnetic heads 102a are respectively provided on the front and back surfaces of the magnetic disk 101 a. Each magnetic head 102a is attached to the tip of the 1 st actuator 104 a. Each magnetic head 102a writes a signal corresponding to data and reads a signal corresponding to data to the magnetic disk 101 a.

The magnetic heads 102b are respectively provided on the front and back surfaces of the magnetic disk 101 b. The two magnetic heads 102b are attached to the tip of the 2 nd actuator 104 b. Each magnetic head 102b writes data to and reads data from the magnetic disk 101 b.

The magnetic disk device 1 includes two VCM (Voice Coil motors) 105. Two VCM (Voice Coil Motor)105 include VCM105a and VCM105 b.

The 1 st actuator 104a is driven by the VCM105a to rotate around the shaft 106.

Fig. 3 is a diagram for explaining the track of the magnetic head 102a according to the embodiment. This figure is a view seen from the magnetic disk 101a side in the direction extending from the shaft 106.

As shown in fig. 3, the 1 st actuator 104a can be rotated within a range determined centering on the shaft 106 by the VCM105a, whereby the magnetic head 102a can be moved on the broken line T. The magnetic head 102a may be positioned on any track in the radial direction of the magnetic disk 101 a.

The 2 nd actuator 104b is driven by the VCM105b to rotate around the shaft 106. The 2 nd actuator 104b is also driven by the VCM105b as with the 1 st actuator 104 a. Thereby, the magnetic head 102b can move on the same track as the magnetic head 102 a.

The description will be made with reference to fig. 1.

The magnetic disk device 1 further includes a control circuit 20.

The control circuit 20 communicates with the host computer 2 via an interface such as a connection pin provided in a housing (not shown) of the magnetic disk apparatus 1 for external connection, and controls each unit of the magnetic disk apparatus 1 in accordance with a command or the like from the host computer 2. The commands include a write command instructing writing of data, and a read command instructing reading of data.

For example, a server device, a portable arithmetic device, a processor, and the like correspond to the host computer 2.

The control circuit 20 includes a preamplifier (PreAmp)21 and a read channel circuit (RDC)22 for each actuator 104. That is, the control circuit 20 includes the preamplifier 21a and the RDC22a corresponding to the 1 st actuator 104 a. The control circuit 20 includes a preamplifier 21b corresponding to the 2 nd actuator 104b and an RDC22 b.

The control circuit 20 further includes a DSP (Digital Signal Processor) 23, a buffer memory 24, a Hard Disk Controller (HDC)25, an MPU (Micro Processing Unit) 26, and a memory 27.

The preamplifier 21a amplifies a signal read from the magnetic disk 101a by the magnetic head 102a (read element), outputs the signal, and supplies the signal to the RDC22 a. The preamplifier 21a amplifies the signal supplied from the RDC22a and supplies the signal to the magnetic head 102a (write element).

The RDC22a includes an ECC (Error Correction Circuit) 28a that performs encoding and decoding for Error Correction. The RDC22a encodes the data recorded on the magnetic disk 101a by the ECC28a, and supplies the encoded data as a signal to the preamplifier 21 a. In addition, the RDC22a decodes the signal read from the magnetic disk 101a and supplied from the preamplifier 21a by the ECC28a, thereby performing detection and correction of errors contained in the signal. The RDC22a outputs the error-corrected signal to the HDC25 as digital data.

The manner of encoding and decoding for error correction used by ECC28a is not limited to a specific manner. For example, LDPC (Low Density Parity Check) may be employed. The size of the data block, which is the unit of encoding/decoding by the ECC28a, is not limited to a specific size. ECC28a may perform encoding/decoding in units of sectors or tracks. The ECC28a may perform encoding/decoding in units of sectors and also in units of tracks. In addition, encoding or decoding for error correction may also be performed by the MPU 26.

The preamplifier 21b amplifies a signal read from the magnetic disk 101b by the magnetic head 102b (read element), outputs the signal, and supplies the signal to the RDC22 b. In addition, the preamplifier 21b amplifies the signal supplied from the RDC22b and supplies it to the magnetic head 102b (write element).

RDC22b is provided with ECC28 b. The RDC22b encodes the data recorded on the magnetic disk 101b by the ECC28b, and supplies the encoded data as a signal to the preamplifier 21 b. In addition, the RDC22b decodes the signal read from the magnetic disk 101b and supplied by the preamplifier 21b by the ECC28b, thereby performing detection and correction of an error contained in the signal. The RDC22b outputs the error-corrected signal to the HDC25 as digital data.

The manner of encoding and decoding for error correction used by ECC28b is not limited to a specific manner. ECC28b uses the same way of encoding and decoding for error correction as ECC28a, for example.

The DSP23 controls the spindle motor and the VCM105a and the VCM105b, and performs positioning control such as seek (seek) and tracking (following). Specifically, the DSP23 demodulates servo information obtained from a signal from the RDC22, and calculates a VCM driving command value in accordance with an error between a position demodulated from the servo information and a target position, thereby performing the positioning control.

The buffer memory 24 is used as a buffer for data transceived between it and the host 2. That is, the data received from the host 2 is stored in the buffer memory 24, and the data received from the host 2 and stored in the buffer memory 24 is written to the magnetic disk 101. The data read from the disk 101 is stored in the buffer memory 24, and the data read from the disk 101 and stored in the buffer memory 24 is output to the host 2.

The buffer memory 24 is made up of, for example, a memory capable of high-speed operation. The type of memory constituting the buffer memory 24 is not limited to a specific type. The buffer Memory 24 may be, for example, a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random Access Memory).

The HDC25 is connected to the host 2 through a predetermined interface, and performs communication with the host 2. The standard to which the interface conforms is not limited to a particular standard. HDC25 saves the data received from RDC22a, RDC22b in buffer 24. The HDC25 transfers the data from the

RDCs

22a and 22b stored in the buffer memory 24 to the host 2.

In addition, the HDC25 saves the data received with the write command from the host 2 to the buffer memory 24. That is, the buffer memory 24 accepts data from the host 2. The HDC25 outputs the data from the host 2 held in the buffer memory 24 to the RDC22a and the RDC22 b.

The MPU26 is a processor that executes firmware (firmware program). The MPU26 analyzes the command received from the host 2 by the HDC25, and monitors the state of the main body of the magnetic disk apparatus 1 and controls each unit of the magnetic disk apparatus 1.

The memory 27 functions as an area for storing firmware and various kinds of management information. The memory 27 is composed of a volatile memory, a nonvolatile memory, or a combination thereof. The volatile memory may be, for example, SRAM, DRAM, etc. The non-volatile memory may be a flash memory or the like.

As described above, the pair of heads 102a and the pair of heads 102b are respectively attached to different actuators 104. Each actuator 104 is driven by a different VCM 105. In addition, a preamplifier 21 and an RDC22 are provided at each actuator 104.

Thus, the control circuit 20 can independently execute access to the magnetic disk 101a using the 1 st actuator 104a and access to the magnetic disk 101b using the 2 nd actuator 104 b.

The control circuit 20 executes access to the magnetic disk 101a using the 1 st actuator 104a and access to the magnetic disk 101b using the 2 nd actuator 104b in parallel (in parallel). This increases the speed (rate) of access to the magnetic disk 101, compared to the case where only 1 actuator 104 is driven to access the magnetic disk 101.

In order to execute access to the magnetic disk 101a using the 1 st actuator 104a and access to the magnetic disk 101b using the 2 nd actuator 104b in parallel, it is necessary to distribute data received serially from the host 2 to the 1 st actuator 104a and the 2 nd actuator 104 b.

Fig. 4 is a diagram for explaining an outline of a data distribution method implemented by the control circuit 20 of the embodiment.

Here, a case where the control circuit 20 receives data from the host 2 in the sequential write (sequential write) access mode will be described. Sequential writing refers to an access pattern in which data is written in logical address order. The logical address is position information indicating a position in a logical address space provided by the disk device 1 to the host 2. The Logical Address may also be referred to as a LBA (Logical Block Address).

In this specification, each data in units of sectors is distinguished by a sector number. In this specification, the sector number is position information indicating the position of a range of sector sizes in the logical address space, and is not position information attached to a sector on the magnetic disk 101. That is, the sector number is one kind of logical address.

According to the example shown in fig. 4, data is stored in consecutive sectors, i.e., sector #1 to sector #10, of the buffer memory 24. That is, data corresponding to 10 sectors is stored in the buffer memory 24.

The control circuit 20 distributes the data stored in the buffer memory 24 to the 1 st actuator 104a and the 2 nd actuator 104b in units of tracks.

Specifically, the control circuit 20 writes data corresponding to 1 track having consecutive sector numbers to the magnetic disk 101a by using the 1 st actuator 104a, and writes data corresponding to 1 track having a sector number subsequent to the data to the magnetic disk 101b by using the 2 nd actuator 104 b.

Here, the track sometimes includes a defective sector. A defective sector refers to a sector that is unreadable or difficult to read. The number of defective sectors included in each track is not constant. Therefore, the number of accessible sectors in each track varies depending on the number of defective sectors.

The control circuit 20 calculates the size (the number of sectors) that can be written in each track based on the number of defective sectors. Then, the control circuit 20 determines the write destination of each data in units of sectors stored in the buffer memory 24 based on the calculated size.

According to the example of fig. 4, the control circuit 20 (for example, MPU26) calculates the number of sectors in which data can be stored for each of a track 300a in the magnetic disk 101a and a track 300b in the magnetic disk 101 b.

The control circuit 20 determines that two of the 6 sectors of the track 300a are defective sectors, and thereby determines that the track 300a has 4 sectors capable of storing data. Further, the control circuit 20 determines that the track 300b does not include a defective sector, and thereby determines that the track 300b has 6 sectors capable of storing data.

The control circuit 20 determines the write destination of 4 data (data of sectors #1 to # 4) having consecutive sector numbers among the data stored in the buffer memory 24 as the track 300 a. The control circuit 20 determines the write destination of 6 data (data of sectors #5 to # 10) having a sector number subsequent to the data written to the track of the magnetic disk 101a as the track 300 b.

Writing to the track 300a is performed using the 1 st actuator 104 a. Writing to the track 300b is performed using the 2 nd actuator 104 b. That is, in the embodiment, each data received from the host 2 is allocated to the 1 st actuator 104a and the 2 nd actuator 104b in units of tracks.

As a technique for comparison with the embodiment, a technique of allocating each data received from the host 2 to a plurality of actuators in units of sectors may be considered. This technique is labeled as comparative example.

According to the comparative example, for example, data with an odd sector number is assigned to the 1 st actuator 104a, and data with an even sector number is assigned to the 2 nd actuator 104 b.

Here, since the number of sectors capable of storing data in the track 300a is 4, when data of sectors #1, #3, #5, #7, and #9 among data of sectors #1 to #10 is written to the magnetic disk 101a, data of sectors #1, #3, #5, and #7 is written to the track 300a, and data of sector #9 is written to a track different from the track 300a in the magnetic disk 101 a. Since the number of sectors capable of storing data in the track 300b is 6, all data having an even sector number among the data of the sectors #1 to #10 are written in the track 300 b.

That is, according to the comparative example, data of sectors #1 to #10 are written to two tracks in the

magnetic disk

101a and 1 track in the magnetic disk 101 b. Therefore, when writing and reading data in the sectors #1 to #10, the disk 101a needs to be accessed for two tracks, and a longer seek time is required. That is, according to the comparative example, the performance of the magnetic disk apparatus is degraded.

In contrast, according to the embodiment, writing and reading are performed only on the track 300a of the magnetic disk 101a and the track 300b of the magnetic disk 101 b. According to the embodiment, the number of target tracks to be written or read per actuator 104 can be suppressed as compared with the comparative example. Therefore, according to the embodiment, the performance of the magnetic disk device 1 can be improved as compared with the comparative example.

Further, according to the comparative example, as the write destination of the data of the sectors #1 to #10, it is necessary to store not only the track 300a but also the track storing the data of the sector #9 with respect to the magnetic disk 101 a.

In contrast, according to the embodiment, it is sufficient that only the track 300a is stored in the magnetic disk 101a as the write destination of the data of the sectors #1 to # 10. Therefore, according to the embodiment, management of the storage destination of the data becomes simpler as compared with the comparative example.

The method of determining the defective sector is not limited to a specific method.

In the embodiment, as an example, the position of a defective sector detected by inspection before shipment and the position of a defective sector generated and detected during operation are recorded as the defective sector information 271. The method of detecting a defective sector is not limited to a specific method. The defective sector information 271 is stored in the memory 27, for example. The control circuit 20 determines whether or not each sector included in the target track is a defective sector by referring to the defective sector information 271. Then, the control circuit 20 calculates the number of sectors capable of storing data included in the target track based on the determination result.

Next, the operation of the magnetic disk device 1 of the embodiment will be described.

Fig. 5 is a flowchart for explaining the operation of the magnetic disk device 1 according to the embodiment of the write command.

The control circuit 20 (e.g., HDC25) starts receiving data requested to be written in response to the write command from the host 2, and starts storing the received data in the buffer memory 24 (S101). The control circuit 20 (for example, MPU26) determines a track to be written for each actuator 104 (S102).

In the explanation of fig. 5 to 7, the write destination track where writing is performed using the 1 st actuator 104a is labeled as track #1_ x. In addition, the write destination track where writing is performed using the 2 nd actuator 104b is labeled as track #2_ x. "x" is an integer greater than 1, and corresponds to the order of writing.

For example, the 1 st actuator 104a performs writing of data to the track #1_1, the track #1_2, and the track #1_3 in the magnetic disk 101a in this order. Further, the 2 nd actuator 104b performs writing of data to the track #2_1, the track #2_2, and the track #2_3 in the magnetic disk 101b in this order.

Here, as an example, the first writing is executed using the 1 st actuator 104 a. The initial write may also be performed using the 2 nd actuator 104 b.

In addition, the data in track units written to the track #1_ x is denoted as track data #1_ x. In addition, the data in track units written to the track #2_ x is denoted as track data #2_ x.

Following S102, the control circuit 20 starts the writing process of each actuator 104 (S103). When the writing process of each actuator 104 is completed, the work corresponding to the write command is completed.

Fig. 6 is a flowchart for explaining a writing process using the 1 st actuator 104a according to the embodiment.

First, the control circuit 20 (for example, MPU26) initializes i as a loop counter for the subsequent loop processing to 1 (S201). Then, the control circuit 20 (e.g., MPU26) determines the sector number of the head of the predetermined track data #1_ i to be written to the track #1_ i (S202).

Next, the control circuit 20 (e.g., MPU26) refers to the defective sector information 271 (S203). In S203, the control circuit 20 determines the number of defective sectors included in the track #1_ i.

Next, the control circuit 20 (e.g., MPU26) determines the size of the track data #1_ i (S204). For example, the control circuit 20 subtracts the number of defective sectors determined in S203 from the number of sectors included in the track #1_ i, thereby calculating the number of writable sectors in the track #1_ i. Then, the control circuit 20 determines the number of writable sectors in the calculated track #1_ i as the size of the track data #1_ i.

The first sector number of the track data #1_ i is determined in S202, and the size of the track data #1_ i is determined in S204. Thereby, data to be written to the track #1_ i, that is, the track data #1_ i, among the data to be written is determined.

The timing track data #1_ i completed in S204 is not necessarily stored in the buffer memory 24. Therefore, the control circuit 20 (e.g., MPU26) determines whether a part or all of the track data #1_ i exists in the buffer memory 24 (S205).

For example, if the data of the first sector number of the track data #1_ i is stored in the buffer memory 24, the control circuit 20 may determine that a part or all of the track data #1_ i exists in the buffer memory 24. If the data of the first sector number of the track data #1_ i is not stored in the buffer memory 24, the control circuit 20 may determine that a part or all of the track data #1_ i is not present in the buffer memory 24.

The method of determining whether or not a part or all of the track data #1_ i exists in the buffer memory 24 is not limited to the above method. The control circuit 20 may determine whether a part or all of the track data #1_ i exists in the buffer memory 24 based on an arbitrary determination reference.

If it is determined that a part or all of the track data #1_ i does not exist in the buffer memory 24 (No in S205), the process of S205 is executed again. Thus, the start of the processing in S206 is delayed until it is determined that a part or all of the track data #1_ i exists in the buffer memory 24.

If it is determined that a part or all of the track data #1_ i exists in the buffer memory 24 (yes in S205), the control circuit 20 starts writing the track data #1_ i (S206). That is, the control circuit 20 writes the track data #1_ i stored in the buffer memory 24 to the track #1_ i in order from the data of the first sector number.

Here, the writing speed of data to the magnetic disk 101 by the 1 actuator 104 is slower than the transfer speed of data from the host 2 to the magnetic disk device 1. Therefore, even if the data writing is started when only a part of the track data #1_ i is stored in the buffer memory 24, the control circuit 20 stores the remaining data of the track data #1_ i in the buffer memory 24 at a speed faster than the writing speed to the magnetic disk 101. Therefore, the control circuit 20 can write data of each sector number included in the track data #1_ i to the magnetic disk 101 continuously in time.

When the writing of the track data #1_ i is completed (S207), the control circuit 20 (e.g., the MPU26) determines whether the track data #1_ i is the last track data (S208).

That is, in S208, the control circuit 20 determines whether or not the track data #1_ i is the last track data assigned to the 1 st actuator 104a among the data for which writing is requested in accordance with the write command.

When it is determined that the track data #1_ i is the last track data (Yes in S208), the write process using the 1 st actuator 104a is completed.

When determining that the track data #1_ i is not the last track data (no in S208), the control circuit 20 (e.g., the MPU26) determines whether or not the determination of the track data #2_ i is completed (S209). The determination of the track data #2_ i is to determine the sector number of the data at the head of the track data #2_ i and the size of the track data #2_ i, and specifically corresponds to the processing of S303 to S305 in the case where j is i in the series of processing shown in fig. 7.

The track data #2_ i is data to be received from the host 2 subsequent to the track data #1_ i. The sector number of the data at the head of the track data #2_ i immediately follows the sector number of the data at the end of the track data #1_ i. If the size of the track data #2_ i can be determined, the sector number of the leading data of the track data #1_ (i +1) received from the host 2 subsequent to the track data #2_ i, and the like can be determined.

If it is determined that the determination of the track data #2_ i is not completed (no in S209), the control circuit 20 repeats the process in S209. Thereby, the control circuit 20 delays the start of the processing of the next processing (S210) until the determination of the track data #2_ i is completed.

If it is determined that the determination of the track data #2_ i is completed (yes in S209), the control circuit 20 (e.g., the MPU26) increments the value of i by 1(S210), and the process in S202 is executed again. In S202, the control circuit 20 can obtain the sector number of the first data of the track data #1_ i by adding the size of the track data #2_ (i-1) to the sector number of the first data of the track data #2_ (i-1), for example.

Fig. 7 is a flowchart for explaining a writing process using the 2 nd actuator 104b according to the embodiment.

First, the control circuit 20 (for example, MPU26) initializes j as a cycle counter for the subsequent cycle processing to 1 (S301). Then, the control circuit 20 (e.g., MPU26) determines whether the determination of the track data #1_ j has been completed (S302). The determination of the track data #1_ j is to determine the sector number of the data at the head of the track data #1_ j and the size of the track data #1_ j, and specifically corresponds to the processing of S202 to S204 in the case where i is j in the series of processing shown in fig. 6.

Track data #2_ j, which is predetermined track data written to the track #2_ j, is received from the host 2 following the track data #1_ j. The sector number of the data at the head of the track data #2_ j is immediately after the sector number of the data at the end of the track data #1_ j. Therefore, if the size of the track data #1_ j can be determined, the sector number of the leading data of the track data #2_ j to be received from the host 2 subsequent to the track data #1_ j, and the like can be determined.

If it is determined that the determination of the track data #1_ j is not completed (no at S302), the control circuit 20 repeats the process at S302. Thereby, the control circuit 20 delays the start of the next process (S303) until the determination of the track data #1_ j is completed.

When determining that the track data #1_ j is completely specified (yes in S302), the control circuit 20 (e.g., the MPU26) specifies the leading sector number of the track data #2_ j (S303).

Next, the control circuit 20 (e.g., MPU26) refers to the defective sector information 271 (S304). In S304, the control circuit 20 determines the number of defective sectors included in the track #2_ j.

Next, the control circuit 20 (e.g., MPU26) determines the size of the track data #2_ j (S305). For example, the control circuit 20 subtracts the number of defective sectors determined in S304 from the number of sectors included in the track #2_ j, thereby calculating the number of writable sectors in the track #2_ j. Then, the control circuit 20 determines the calculated number of writable sectors in the track #2_ j as the size of the track data #2_ j.

Next, the control circuit 20 (e.g., MPU26) determines whether a part or all of the track data #2_ j exists in the buffer memory 24 (S306). The method of determination in S306 is not limited to a specific method. In S306, the determination may be performed by the same method as S205.

If it is determined that a part or all of the track data #2_ j does not exist in the buffer memory 24 (no in S306), the process in S306 is executed again. Thus, the start of the processing in S307 is delayed until it is determined that a part or all of the track data #2_ j is present in the buffer memory 24.

When it is determined that a part or all of the track data #2_ j exists in the buffer memory 24 (yes in S306), the control circuit 20 starts writing of the track data #2_ j (S307). That is, the control circuit 20 writes the track data #2_ j stored in the buffer memory 24 to the track #2_ j sequentially from the data of the first sector number. Even if the data writing is started when only a part of the track data #2_ j is stored in the buffer memory 24, the control circuit 20 stores the remaining data of the track data #2_ j in the buffer memory 24 at a speed faster than the writing speed to the magnetic disk 101. Therefore, the control circuit 20 can write data of each sector number included in the track data #2_ j to the magnetic disk 101 continuously in time.

When the writing of the track data #2_ j is completed (S308), the control circuit 20 (e.g., the MPU26) determines whether the track data #2_ j is the last track data (S309).

That is, in S309, the control circuit 20 determines whether or not the track data #2_ j is the last track data written using the 2 nd actuator 104b among the data for which writing is requested in accordance with the write command.

When it is determined that the track data #2_ j is the last track data (yes in S309), the write process using the 2 nd actuator 104b is completed because there is no more track data to be written by the 2 nd actuator 104 b.

When it is determined that the track data #2_ j is not the last track data (no in S309), the control circuit 20 (e.g., the MPU26) increments the value of j by 1(S310), and executes the process in S302 again.

Fig. 8 is a diagram for explaining the timing of writing each track data of the embodiment realized by the above-described operation.

The timing of storing data to be written in the buffer memory 24 is shown in the upper line 1 of the figure. Thus, the storage of the track data #1_1 is started at time t0, and the storage of the track data #1_1 is completed at time t 1. Likewise, the saving of the track data #2_1 starts at time t1 and completes at time t 2. Likewise, the saving of the track data #1_2 starts at time t2 and completes at time t 3. Likewise, the saving of the track data #2_2 starts at time t3 and completes at time t 4.

The progress of the writing process using the 1 st actuator 104a is shown in the upper 2 nd row of the present drawing. The progress of the writing process using the 2 nd actuator 104b is shown in the 3 rd row from the top in the figure.

At time t0, the control circuit 20 performs preparation for transfer of track data #1_1 (S401). The processing of S401 and S405 described later corresponds to the processing of S202 to S204.

At the timing when the preparation for transfer of the track data #1_1 (S401) is completed, since a part of the track data #1_1 is held in the buffer memory 24, the control circuit 20 performs writing of the track data #1_1 immediately after S401 (S402).

The control circuit 20 also performs preparation for transfer of the track data #2_1 at time t0 (S403). The processing of S403 and S407 described later corresponds to the processing of S303 to S305. Since the track data #1_1 is determined by the processing of S401, the control circuit 20 can determine the track data #2_1 in S403.

At the timing when the processing of S403 is completed, the saving of the track data #2_1 to the buffer memory 24 has not yet been started. The control circuit 20 starts writing of the track data #2_1 at a timing after a part of the track data #2_1 is stored in the buffer memory 24, that is, at a timing slightly after the time t1 (S404).

At the timing when the writing of the track data #1_1 (S402) is completed, the determination of the track data #2_1 (S403) is completed. Accordingly, the control circuit 20 performs preparation for transfer of the track data #1_2 (S405). That is, the control circuit 20 determines the track data #1_ 2.

At the timing when the preparation for the transfer of the track data #1_2 (S405) is completed, the control circuit 20 starts the writing of the track data #1_2 immediately after S405 since all the track data #1_2 is stored in the buffer memory 24 (S406).

At the timing when the writing of the track data #2_1 (S404) is completed, the determination of the track data #1_2 (S405) is completed. Accordingly, the control circuit 20 performs preparation for transfer of the track data #2_2 (S407). That is, the control circuit 20 determines the track data #2_ 2.

At the timing when the processing of S407 is completed, the saving of the track data #2_2 to the buffer memory 24 has not yet been started. The control circuit 20 starts writing of the track data #2_2 at a timing after a part of the track data #2_2 is stored in the buffer memory 24, that is, at a timing slightly after the time t3 (S408).

When the processing in S406 and S408 is completed, the writing of all the data stored in the buffer memory 24 to the disk 101 is completed.

The allocation of data received from the host 2 in units of tracks is realized in this manner.

Fig. 9 is a flowchart for explaining the operation of the magnetic disk device 1 according to the embodiment of the read command.

The control circuit 20 (for example, MPU26) first specifies a track of a read source for each actuator 104 (S501). After that, the control circuit 20 starts the readout process of each actuator 104 (S502).

In the explanation of fig. 9 to 11, the case where the track data #1_ x, #2_ x explained in fig. 5 to 7 are read-out targets will be explained.

The method of determining the track of the read source is not limited to a specific method. For example, the control circuit 20 stores the correspondence between logical addresses and sectors in the magnetic disk 101. In general, data to be read is specified by a read command within a range of logical addresses. The control circuit 20 determines the track of the read source based on the correspondence between the logical address and each sector in the magnetic disk 101 and the range of the logical address specified by the read command.

The data to be read is sequentially stored in the buffer memory 24 by the read processing of each actuator 104. The HDC25 transmits the data stored in the buffer memory 24 to the host 2 in the order of logical addresses (sector numbers) (S503). When all the data transmission is completed, the work corresponding to the read command is finished.

Fig. 10 is a flowchart for explaining a reading process using the 1 st actuator 104a according to the embodiment.

First, the control circuit 20 (for example, MPU26) initializes k as a loop counter for the subsequent loop processing to 1 (S601). Then, the control circuit 20 (e.g., MPU26) determines the size of the track data #1_ k (S602). The size of the track data #1_ k can be determined by counting the number of sectors associated with logical addresses included in the track #1_ k. The method of determining the size of the track data #1_ k is not limited to this.

Next, the control circuit 20 (for example, the MPU26) allocates the area for storing the track data #1_ k in the buffer memory 24 (S603). In S603, the control circuit 20 allocates the area of the size obtained in S602.

Next, the control circuit 20 (e.g., HDC25) reads the track data #1_ k from the track #1_ k to the buffer memory 24 (S604). In S604, the track data #1_ k is stored in the area allocated in S603 in the buffer memory 24.

When the reading of the track data #1_ k is completed (S605), the control circuit 20 (e.g., the MPU26) determines whether the track data #1_ k is the last track data (S606).

That is, in S606, the control circuit 20 determines whether or not the track data #1_ k is the last track data read using the 1 st actuator 104a among the data for which reading is requested in accordance with the read command.

When it is determined that the track data #1_ k is the last track data (yes in S606), the read process using the 1 st actuator 104a is completed.

When determining that the track data #1_ k is not the last track data (no in S606), the control circuit 20 (e.g., the MPU26) increments the value of k by 1(S607), and executes the process in S602 again.

Fig. 11 is a flowchart for explaining a reading process using the actuator 104b of embodiment 2.

First, the control circuit 20 (for example, MPU26) initializes m as a loop counter for the subsequent loop processing to 1 (S701). Then, the control circuit 20 (e.g., MPU26) determines the size of the track data #1_ m (S702). The size of the track data #1_ m can be determined by counting the number of sectors associated with logical addresses included in the track #1_ m. The method of determining the size of the track data #1_ m is not limited to this.

Next, the control circuit 20 (e.g., MPU26) allocates an area for storing the track data #1_ m in the buffer memory 24 (S703). In S703, the control circuit 20 (e.g., MPU26) allocates an area of the size obtained in S702.

Next, the control circuit 20 (e.g., HDC25) reads the track data #1_ m from the track #1_ m to the buffer memory 24 (S704). In S704, track data #1_ m is stored in the area allocated in S703 in the buffer memory 24.

When the reading of the track data #1_ m is completed (S705), the control circuit 20 (e.g., the MPU26) determines whether the track data #1_ m is the last track data (S706).

That is, in S706, the control circuit 20 determines whether or not the track data #1_ m is the last track data read using the 2 nd actuator 104b among the data for which reading is requested in accordance with the read command.

When it is determined that the track data #1_ m is the last track data (yes in S706), the read process using the 2 nd actuator 104b is completed.

When determining that the track data #1_ m is not the last track data (no in S706), the control circuit 20 (e.g., the MPU26) increments the value of m by 1(S707), and executes the process in S702 again.

Fig. 12 is a diagram for explaining the timing of reading each track data of the embodiment by the operation described above.

The progress of the readout process using the 1 st actuator 104a is shown in the 1 st row from above in the present drawing. The progress of the readout process using the 2 nd actuator 104b is shown in the 2 nd row from the top in the present drawing. The timing of transferring each data from the buffer memory 24 to the host 2 is shown in the upper 3 rd line of the figure.

First, at time t10, the control circuit 20 performs preparation for transfer of track data #1_1 (S801). The processing of S801 and S803 described later corresponds to the processing of S602 to S603.

When the preparation for transfer of the track data #1_1 (S801) is completed, the control circuit 20 immediately performs readout of the track data #1_1 (S802).

When the process of S802 is completed, the control circuit 20 performs preparation for transfer of the track data #1_2 (S803). After that, the control circuit 20 immediately performs readout of the track data #1_2 (S804).

With regard to the 2 nd actuator 104b, the control circuit 20 performs preparation for transfer of the track data #2_1 at time t10 (S805). The processing of S805 and S807 described later corresponds to the processing of S702 to S703.

When the preparation for the transfer of the track data #2_1 (S805) is completed, the control circuit 20 immediately performs the readout of the track data #2_1 (S806).

When the process of S806 is completed, the control circuit 20 performs preparation for transfer of the track data #2_2 (S807). After that, the control circuit 20 immediately performs readout of the track data #2_2 (S808).

The track data stored in the buffer memory 24 is transferred to the host 2 in the logical address order. In this example, the track data #1_1, the track data #2_1, the track data #1_2, and the track data #2_2 are transferred to the host 2 in this order.

As such, at the time of processing of the read command, the read processing of each actuator 104 can be executed completely independently.

In the above description, a method of allocating an area in the buffer memory 24 is not mentioned. The method of allocating the area in the buffer memory 24 is not limited to a specific method.

Fig. 13 is a diagram for explaining an example of a method of allocating an area in the buffer memory 24 according to the embodiment. As shown in the figure, the area 240a for the track data #1_1, the area 240b for the track data #2_1, the area 240c for the track data #1_2, and the area 240d for the track data #2_2 are allocated so as to be continuous in this order in the buffer memory 24. According to this example, if the HDC25 reads data in the buffer memory 24 continuously from the head of the area 240a to the end of the area 240d, output in the logical address order can be realized.

Fig. 14 is a diagram for explaining another example of the allocation method of the area in the buffer memory 24 according to the embodiment. In the example of the present figure, the area 2400a for the 1 st actuator 104a and the area 2400b for the 2 nd actuator 104b are allocated in advance to the buffer memory 24. The region 2400a is used for the readout process using the 1 st actuator 104a, and the region 2400b is used for the readout process using the 2 nd actuator 104 b.

In this case, for example, the control circuit 20 (for example, MPU26) stores a pointer (pointer) indicating a position at which the subsequent track data is stored as a logical address at the end of each area, for example. For example, when the area 240f for track data #2_1 is allocated, the control circuit 20 stores the pointer 250a indicating the position of the head of the area 240f at the end of the area 240e for track data #1_ 1. When the area 240g for track data #1_2 is allocated, the control circuit 20 stores the pointer 250b indicating the position of the head of the area 240g at the end of the area 240f for track data #2_ 1. When the area 240h for track data #2_2 is allocated, the control circuit 20 stores the pointer 250c indicating the position of the head of the area 240h at the end of the area 240g for track data #1_ 2.

When the HDC25 completes the transfer of one track data to the host 2, the transfer source is caused to shift to the position indicated by the pointer held at the position subsequent to the track data in the buffer memory 24. This enables output in the order of logical addresses.

In the above description, the case where the magnetic disk apparatus 1 includes the two actuators 104 that can be controlled independently of each other has been described. The technique of the embodiment can be applied to a case where the magnetic disk device 1 includes 3 or more actuators 104 that can be independently controlled. When the magnetic disk apparatus 1 includes 3 or more actuators 104 that can be independently controlled, the control circuit 20 assigns data received serially from the host 2 to the 3 or more actuators on a track-by-track basis, for example. The allocation rule may be, for example, a round robin (round robin) scheme or may not be the round robin scheme.

In addition, the relationship between the plurality of actuators 104 and the plurality of magnetic heads 102 is not limited to the above-described relationship. The relationship of the plurality of actuators 104 to the plurality of heads 102 may be arbitrarily designed.

For example, the 1 st actuator 104a may move the head 102a for accessing the front surface of the magnetic disk 101a and the head 102b for accessing the front surface of the magnetic disk 101b, and the 2 nd actuator 104b may move the head 102a for accessing the back surface of the magnetic disk 101a and the head 102b for accessing the back surface of the magnetic disk 101 b.

In another example, the magnetic disk apparatus 1 may be provided with 4 actuators 104, and each of the 4 magnetic heads 102 may be moved by a different one of the 4 actuators 104.

In still another example, the magnetic disk apparatus 1 may include 1 magnetic disk 101, the front surface of the magnetic disk 101 may be accessed by a magnetic head 102a provided at the tip of a 1 st actuator 104a, and the back surface of the magnetic disk 101 may be accessed by a magnetic head 102b provided at the tip of a 2 nd actuator 104 b.

In still another example, two heads 102 may access the same surface of 1

disk

101, and 1 of the two heads 102 may be moved by the 1 st actuator 104a, and the other of the two heads 102 may be moved by the 2 nd actuator 104 b. In this case, each actuator 104 is driven to rotate about a different axis 106.

In the above description, the case where the disk device 1 receives data from the host 2 in the sequential write access mode has been described. The magnetic disk device 1 can perform the same operation as described above even when data is received from the host 2 in an access mode different from the sequential writing.

As a method of writing data to the Magnetic disk 101, a method called SMR (shifted Magnetic Recording) is known.

Fig. 15 is a schematic diagram for explaining an embodiment of SMR. The SMR is a recording method in which data is written by the magnetic head 102 (writing element) so that each track overlaps with a part of an adjacent track.

For example, track #2 partially overlaps track # 1. In addition, track #3 partially overlaps track # 2. That is, with SMR, 1 track overlaps with a part of an adjacent track where data has already been written.

Thus, the Track Pitch (TP) of each track is narrower than the core width (WHw) of the write elements of the head 102. As a result, the recording density is improved.

When the SMR is used, a plurality of bands (bands) are set in the recording area of the magnetic disk 101.

Fig. 16 is a schematic diagram for explaining an example of a plurality of bands of the embodiment. As shown in the figure, the magnetic disk 101 includes a plurality of bands (bands) 120 arranged in the radial direction. Each of the bands 120 has a concentric circular shape. Guard areas 130 are allocated between the bands 120. The protection area 130 is an area where data is not written. Each band 120 has a width to which data of a plurality of tracks can be written. Data corresponding to a plurality of tracks is written to each band 120 in the SMR manner. Data in units of bands 120 are written to the magnetic disk 101 continuously in time.

The technique according to the embodiment can also be applied to a magnetic disk device to which SMR is applied. In this case, for example, the control circuit 20 can allocate data in units of bands 120 to two bands 120 different from each other in the actuator 104 which performs access in units of tracks. This increases the speed of writing and reading data in units of bands.

In the case of SMR, data in the band 120 is written so that each track partially overlaps with an adjacent track. Therefore, for example, when it is desired to update a part of the data in a certain band 120, all the data in the band 120 is read out to the buffer memory 24, the data in the buffer memory 24 is updated, and the updated data is written to the magnetic disk 101.

In the conventional magnetic disk apparatus including only 1 actuator, for example, when 1 zone is constituted by 100 tracks, it is necessary to read data from 100 tracks, update the read data, and write the updated data to 100 tracks of another zone.

In the embodiment, if each band 120 is configured to include 50 tracks, and data corresponding to 1 band (data corresponding to 100 tracks) is written to two different bands 120 using two

actuators

104a and 104b, the

actuators

104a and 104b can update the data corresponding to the 1 band by reading data corresponding to 50 tracks and writing data corresponding to 50 tracks, respectively. The

actuators

104a and 104b can be operated in parallel as described above. When updating the tape data, the actuator 104a and the actuator 104b execute the processing in parallel, and thereby the speed of updating the tape data can be increased compared to the conventional one.

In addition, the magnetic disk 101 may be provided with a media cache (media cache) area in addition to the tape 120. For example, the data received from the host 2 and stored in the buffer memory 24 is temporarily written into the medium buffer area. The data in the medium buffer area is written to the predetermined band 120 via the buffer memory 24 at a predetermined timing (for example, a timing at which data corresponding to 1 band is accumulated in the medium buffer area). When reading data corresponding to 1 band in the media buffer area from the buffer memory 24 and writing the read data corresponding to 1 band to the magnetic disk 101, the control circuit 20 may allocate the data corresponding to 1 band read from the buffer memory 24 to two bands 120 different from each other in units of tracks to the actuator 104. The reading from the medium buffer area to the buffer memory 24 may be performed in sizes each smaller than the size corresponding to 1 band. That is, when the control circuit 20 writes data received from the host 2 to the buffer memory 24 to the magnetic disk 101 via the media buffer area, the data may be allocated to two different bands 120 of the actuator 104 on a track-by-track basis.

In the above description, the control circuit 20 may not store the data received from the host 2 in all the writable sectors in the track in which the writable sector number in the track is determined to be the size of the data (track data) written in the track.

For example, data received from the host 2 is written to the disk 101 after redundant data such as an error correction code is added. That is, the size of data written to the disk 101 is larger than the size of data received from the host 2 by an amount corresponding to redundant data.

In this case, the control circuit 20 obtains the number of writable sectors in the track, and then obtains the size obtained by subtracting the size of the redundant data from the size of the obtained number of sectors. For example, when the size of the redundant data is 1 sector, the control circuit 20 determines the size of the sectors, which is obtained by subtracting 1 from the number of writable sectors in the track, as the size of the track data.

That is, the MPU26 determines the number of writable sectors in a track, and then determines the size corresponding to the determined number of sectors as the size of track data. The size corresponding to the determined number of sectors is a size of data that does not include redundant data and can be stored in the determined number of sectors.

As described above, according to the embodiment, the buffer memory 24 accepts data (1 st data) received from the host 2. The control circuit 20 specifies the number of writable sectors (1 st number of sectors) in a certain track (1 st track) using the 1 st actuator 104a (e.g., S204 in fig. 6, S401 in fig. 8), and writes data (2 nd data) of the 1 st data having a size corresponding to the 1 st number of sectors in the 1 st track using the 1 st actuator 104a (e.g., S206 to S207 in fig. 6, S402 in fig. 8). The control circuit 20 determines the number of writable sectors (2 nd sector number) using the 2 nd actuator 104b in a track (2 nd track) different from the 1 st track (e.g., S305 in fig. 7 and S403 in fig. 8), and writes data (3 rd data) of the 1 st data, which is received after the 2 nd data and has a size corresponding to the 2 nd sector number, to the 2 nd track using the 2 nd actuator 104b (e.g., S307 to S308 in fig. 7 and S404 in fig. 8).

Thus, the data received serially from the host 2 is distributed to the plurality of actuators 104 in units of tracks. Therefore, as described above, the seek time can be reduced as compared with the comparative example. That is, the performance of the magnetic disk apparatus 1 can be improved.

In addition, according to the embodiment, the control circuit 20 determines the number of writable sectors (3 rd number of sectors) using the 1 st actuator 104a in another track (3 rd track) (for example, S405 in fig. 8), and writes data (4 th data) of a size corresponding to the 3 rd number of sectors received after the 3 rd data among the 1 st data to the 3 rd track using the 1 st actuator 104a (for example, S406 in fig. 8).

This enables data received serially from the host 2 to be allocated to the two actuators 104 on a track-by-track basis.

In addition, according to the embodiment, as described with reference to fig. 8, the control circuit 20 can start writing of data (3 rd data) using the 2 nd actuator 104b before writing of data (2 nd data) using the 1 st actuator 104a is completed. That is, the 1 st actuator 104a and the 2 nd actuator 104b can perform writing in parallel. This can increase the speed of writing data.

Further, the control circuit 20 determines defective sectors, and determines the 1 st sector number and the 2 nd sector number based on the determination result of the defective sectors.

This enables the size of data that can be written to the target track to be accurately determined even when the size changes due to an increase or decrease in defective sectors.

When the 1 st data is requested from the host 2, the control circuit 20 reads the 2 nd data from the 1 st track to the buffer memory 24 by using the 1 st actuator 104a (e.g., S604 to S605 in fig. 10, S802 in fig. 12), and reads the 3 rd data from the 2 nd track to the buffer memory 24 by using the 2 nd actuator 104b (e.g., S704 to S705 in fig. 11, S806 in fig. 12). Then, the control circuit 20 outputs the 2 nd data and the 3 rd data stored in the buffer memory 24 to the host 2 in this order (for example, fig. 12). That is, in the present embodiment, the 2 nd data and the 3 rd data are output to the host 2 in the order of logical addresses.

This makes it possible to efficiently perform the operation of reading the magnetic disk 101 using the plurality of actuators 104.

After the 2 nd data is completely read, the control circuit 20 reads data (4 th data) from another track to the buffer memory 24 using the 1 st actuator 104a (for example, S804 in fig. 12).

The control circuit 20 can execute the readout using the 1 st actuator 104a (e.g., S802 in fig. 12) and the readout using the 2 nd actuator 104b (e.g., S806 in fig. 12) in parallel.

This improves the speed of reading data from the magnetic disk 101, and as a result, the performance of reading data from the magnetic disk apparatus 1 is improved.

In the case of the SMR recording method, the control circuit 20 may allocate data received serially from the host 2 to the band 120 (1 st area) included in the disk 101a and the band 120 (2 nd area) included in the disk 101b on a track-by-track basis. That is, the 1 st track is included in the tape 120 included in the magnetic disk 101a, and the 2 nd track is included in the tape 120 included in the magnetic disk 101 b.

This can improve the performance of the magnetic disk apparatus 1 even when the SMR recording method is employed.

While the embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments may be implemented in various other ways, and various omissions, substitutions, and changes may be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the scope equivalent thereto.

Claims

1. A magnetic disk device is provided with:

a magnetic disk having a plurality of tracks;

a 1 st magnetic head;

a 2 nd magnetic head different from the 1 st magnetic head;

a 1 st actuator that moves a position of the 1 st head;

a 2 nd actuator which is different from the 1 st actuator and moves a position of the 2 nd head;

a buffer memory receiving 1 st data from a host; and

a control circuit that determines a 1 st sector number that is a writable sector number that a 1 st track of the plurality of tracks has, and writes 2 nd data of a size corresponding to the 1 st sector number of the 1 st data to the 1 st track using the 1 st actuator; determining a 2 nd sector number that is a writable sector number that a 2 nd track different from the 1 st track has among the plurality of tracks, writing, to the 2 nd track, 3 rd data of a size corresponding to the 2 nd sector number that is received subsequent to the 2 nd data among the 1 st data using the 2 nd actuator,

the control circuit determines a 3 rd sector number which is a writable sector number possessed by a 3 rd track different from either the 1 st track or the 2 nd track among the plurality of tracks, writes 4 th data of a size corresponding to the 3 rd sector number received after the 3 rd data among the 1 st data to the 3 rd track using the 1 st actuator,

starting the writing of the 4 th data after the writing of the 2 nd data is ended.

2. The magnetic disk apparatus according to claim 1,

the 3 rd track as a writing destination of the 4 th data is located on the same plane as the 1 st track.

3. The magnetic disk apparatus according to claim 1,

the control circuit starts writing of the 3 rd data before writing of the 2 nd data is completed.

4. The magnetic disk apparatus according to claim 1,

the control circuit determines a defective sector and determines the 1 st sector number and the 2 nd sector number based on a determination result of the defective sector.

5. The magnetic disk apparatus according to claim 1,

when the 1 st data is requested from the host, the control circuit reads the 2 nd data from the 1 st track to the buffer memory using the 1 st actuator, reads the 3 rd data from the 2 nd track to the buffer memory using the 2 nd actuator, and outputs the 2 nd data and the 3 rd data stored in the buffer memory to the host in the order of the 2 nd data and the 3 rd data.

6. The magnetic disk device according to claim 5,

the control circuit reads the 4 th data from the 3 rd track to the buffer memory using the 1 st actuator after the 2 nd data read is completed.

7. The magnetic disk device according to claim 5,

the control circuit performs the readout of the 2 nd data and the readout of the 3 rd data in parallel.

8. The magnetic disk apparatus according to claim 1,

the magnetic disk is provided with a 1 st region and a 2 nd region different from the 1 st region,

the control circuit performs writing to the 1 st area and the 2 nd area by way of SMR, shingled magnetic recording,

the 1 st track is included in the 1 st zone, and the 2 nd track is included in the 2 nd zone.

9. The magnetic disk apparatus according to claim 1,

the 1 st data is saved from the host to the buffer memory in logical address order,

the logical address of the beginning position of the 3 rd data follows the logical address of the end of the 2 nd data.

10. A magnetic disk device is provided with:

a magnetic disk having a plurality of 1 st storage areas;

a 1 st magnetic head;

a 2 nd magnetic head different from the 1 st magnetic head;

a 1 st actuator that moves a position of the 1 st head;

a buffer memory which accepts 1 st data received from the host; and

a control circuit that determines a 1 st size that is a size of data writable to a 2 nd storage area among the plurality of 1 st storage areas, and writes 2 nd data of the 1 st size among the 1 st data to the 2 nd storage area using the 1 st actuator; determining a 2 nd size that is a size of data writable to a 3 rd storage area different from the 2 nd storage area among the plurality of 1 st storage areas, writing 3 rd data received subsequent to the 2 nd data of the 2 nd size among the 1 st data to the 3 rd storage area using the 2 nd actuator,

the control circuit determines a 3 rd size that is a size of data writable to a 4 th storage area different from either the 2 nd storage area or the 3 rd storage area among the plurality of 1 st storage areas, writes 4 th data received subsequent to the 3 rd data among the 1 st data to the 4 th storage area using the 1 st actuator,

11. The magnetic disk device according to claim 10, wherein the 4 th storage area as a write destination of the 4 th data is located on the same plane as the 2 nd storage area.