CN110942793A

CN110942793A - Memory device

Info

Publication number: CN110942793A
Application number: CN201911012729.XA
Authority: CN
Inventors: 马向超; 吴瑞仁; 王坤
Original assignee: Beijing Xin Yi Technology Co Ltd
Current assignee: Beijing Xin Yi Technology Co Ltd
Priority date: 2019-10-23
Filing date: 2019-10-23
Publication date: 2020-03-31
Anticipated expiration: 2039-10-23
Also published as: CN110942793B

Abstract

The invention discloses a memory, which is a resistance change memory with a serial peripheral interface, and comprises: the semiconductor device comprises a plurality of memory chips and a packaging assembly, wherein the memory chips are cascaded so that each memory chip executes corresponding action according to an input status bit; the packaging assembly is used for packaging a plurality of storage chips. According to the memory provided by the embodiment of the invention, the cascade of a plurality of memory chips can be realized without an external chip selection control chip, and the capacity expansion is realized, so that a large-capacity product can be developed quickly, the time to market is reduced, the cost of chip cascade is effectively saved, the one-time cost of the chip can be saved to a certain extent, the complexity of a system is reduced, the resources of a printed circuit board are effectively saved, and the memory is simple and easy to realize.

Description

Memory device

Technical Field

The invention relates to the technical field of memory chip cascade, in particular to a memory.

Background

In the related art, the cascade connection of multiple memory chips is often implemented by adding one master-slave selection chip in a system, specifically: the master-slave selection chip identifies the currently required memory chip according to the address or other signals, and in order to ensure that only the currently required memory chip responds, an independent chip selection signal is correspondingly set for each memory chip, so that the cascade connection of a plurality of memory chips is realized, and further the capacity expansion is realized.

However, the added master-slave selection chip not only increases the cost of the cascade, but also increases the complexity of the system, and meanwhile, the chip selection signal also consumes the resources of the printed circuit board, further increasing the cost of the cascade.

Disclosure of Invention

The present invention is directed to solving, at least to some extent, one of the technical problems in the related art.

Therefore, the invention aims to provide a memory, which can realize the cascade connection of a plurality of memory chips without an external chip selection control chip and realize the capacity expansion, thereby quickly developing a large-capacity product, reducing the time to market, effectively saving the cost of chip cascade connection and saving the one-time cost of the chip to a certain extent.

In order to achieve the above object, an embodiment of the present invention provides a memory, where the memory is a resistance change memory with a serial peripheral interface, and the memory includes: the memory chips are cascaded, so that each memory chip executes corresponding action according to the input status bit; a package assembly for packaging the plurality of memory chips.

The memory of the embodiment of the invention can realize the cascade connection of a plurality of memory chips without an external chip selection control chip and realize the capacity expansion, thereby rapidly developing large-capacity products, reducing the time to market, effectively saving the cost of chip cascade connection, saving the one-time cost of the chip to a certain extent and reducing the complexity of a system; the corresponding memory chip can be directly controlled to execute actions according to the input status bit without chip selection signals, so that the resources of the printed circuit board are effectively saved, and the method is simple and easy to implement.

In addition, the memory according to the above embodiment of the present invention may further have the following additional technical features:

further, in one embodiment of the present invention, a memory chip of the plurality of memory chips includes: a plurality of SPI interfaces; an address register for receiving the status bit through the plurality of SPI (Serial Peripheral Interface) interfaces; and the input state machine is used for judging whether the state bit meets a preset condition or not, responding to a control action after meeting the preset condition, and not responding to the control action if not.

Further, in an embodiment of the present invention, the preset condition is that an address range determined by the status bit matches a preset address range.

Further, in one embodiment of the present invention, the plurality of memory chips are connected sequentially by bonding wires.

Further, in an embodiment of the present invention, the address range intervals preset by the plurality of memory chips are different.

Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

Drawings

The foregoing and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

FIG. 1 is a diagram illustrating a memory according to an embodiment of the present invention;

FIG. 2 is a schematic circuit diagram of a memory chip according to an embodiment of the invention;

FIG. 3 is a schematic diagram illustrating a cascade of memory chips according to an embodiment of the invention;

FIG. 4 is a diagram illustrating another cascade of memory chips according to an embodiment of the invention.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.

A proposed memory according to an embodiment of the present invention is described below with reference to the accompanying drawings.

Fig. 1 is a schematic structural diagram of a memory according to an embodiment of the present invention.

As shown in fig. 1, the memory 100 is a resistance change memory having a serial peripheral interface, and includes: a plurality of memory chips 110 and package assemblies 120.

The memory chips 110 are cascaded to enable each memory chip to execute corresponding actions according to input status bits; the package assembly 120 is used to package a plurality of memory chips. The memory 100 of the embodiment of the invention can realize the cascade connection of a plurality of memory chips without an external chip selection control chip, and realize the capacity expansion, thereby rapidly developing large-capacity products, reducing the time to market, effectively saving the cost of chip cascade connection, saving the one-time cost of the chip to a certain extent, reducing the complexity of the system, effectively saving the resources of a printed circuit board, and being simple and easy to realize.

In one embodiment of the present invention, a memory chip of the plurality of memory chips 110 includes: a plurality of SPI interfaces, an address register, and an input state machine.

The address register is used for receiving the status bits through a plurality of SPI interfaces; and the input state machine is used for judging whether the state bit meets a preset condition or not, responding to the control action after meeting the preset condition, and not responding to the control action if not.

Further, in one embodiment of the present invention, the preset condition is that the address range determined by the status bit matches a preset address range; the plurality of memory chips are connected through bonding wires in sequence; the address range intervals preset by the plurality of memory chips are different.

Specifically, as shown in fig. 2, a value written in the chip during testing or a status bit modified by a command is input to an address register through an SPI interface, and the status bit is used as an input signal of an input state machine after logical operation, and the input state machine determines whether to execute the command according to the input signal.

The state bit of the chip mainly determines the address range of the chip, when the input address range is matched with the preset address range of the chip, the chip is controlled to execute a command according to the input signal, and otherwise, the chip automatically quits and does not respond.

Furthermore, the embodiment of the invention can set the state bit of each memory chip as required in the memory chip testing stage, and directly package the chips together during chip packaging, thereby realizing cascade connection of a plurality of chips and packaging the chips into a large-capacity chip, and further packaging the low-capacity memory chip into the large-capacity chip rapidly and efficiently; of course, the embodiment of the invention can also realize cascade connection on the system printed circuit board by a plurality of packaged chips by writing the status bit by a user through an instruction after the system is out of the field, thereby increasing the expansibility and flexibility of system storage.

The two cascade modes will be further explained by specific embodiments.

The first cascade mode: the cascade connection of chips is realized on a package substrate, namely the capacity expansion is realized, specifically: as shown in fig. 3, corresponding address range intervals are set for different chips in a test stage, and all PADs are directly connected by bonding wires during packaging and then led to a responding package PAD, thereby implementing a large-capacity memory chip. The whole chip is externally represented as a chip with large capacity.

The second cascade mode: the method for implementing cascade at system level specifically includes: as shown in fig. 4, the user presets the status bit, i.e. the address range interval, of each chip by an instruction, and then welds all the interfaces with the same function on the same line on the system PCB board, and the system controller only responds to the memory chip with the matched address range when sending the memory related instruction, thereby implementing the memory cascade on the system.

It should be noted that, because the address ranges corresponding to each chip are different, the read write function can be implemented as long as the write operation and the read operation are not in the same address range, and thus, the embodiment of the present invention can implement the read write function. The read write function is a function in which one part is reading while the other part is writing.

In summary, the memory provided by the embodiment of the invention can realize the cascade connection of a plurality of memory chips without an external chip selection control chip, and realize the capacity expansion, thereby rapidly developing a large-capacity product, reducing the time to market, effectively saving the cost of chip cascade connection, and saving the one-time cost of the chip to a certain extent; meanwhile, the flexibility of system design is increased, capacity expansion and read write function are easy to realize, and the method is simple and easy to realize.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.

Claims

1. The memory is a resistive random access memory with a serial peripheral interface, and comprises:

the memory chips are cascaded, so that each memory chip executes corresponding action according to the input status bit;

a package assembly for packaging the plurality of memory chips.

2. The memory of claim 1, wherein a memory chip of the plurality of memory chips comprises:

a plurality of SPI interfaces;

an address register for receiving the status bits through the plurality of SPI interfaces;

and the input state machine is used for judging whether the state bit meets a preset condition or not, responding to a control action after meeting the preset condition, and not responding to the control action if not.

3. The memory of claim 1, wherein the predetermined condition is that an address range determined by the status bit matches a predetermined address range.

4. The memory of claim 1, wherein the plurality of memory chips are connected sequentially by bond wires.

5. The memory of claim 1, wherein the address range intervals preset by the plurality of memory chips are different.