CN110970435B - Semiconductor device and method of forming the same - Google Patents

Abstract

The present invention provides a semiconductor device and a method for forming the same. First, a trench isolation structure is formed in the substrate. Since the trench isolation structure has a first isolation portion connected to each other and a second isolation portion located below the first isolation portion, and the lateral width dimension of the second isolation portion in a direction perpendicular to the height is greater than the lateral width dimension of the first isolation portion in a direction perpendicular to the height, the second isolation portion protrudes laterally relative to the first isolation portion, thereby reducing the area of a leakage region, thereby increasing the equivalent resistance on the leakage path, thereby reducing leakage current and improving the storage performance of the semiconductor device. Furthermore, the source region extends from the top surface of the substrate to between a first depth position and a second depth position, further reducing the area of the leakage region and achieving a better effect of reducing leakage current.

Description

Semiconductor device and method for forming the same

Technical Field

The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor device and a method for forming the same.

Background Art

At present, the existing integrated circuit memory may generally include a plurality of transistors. In order to reduce the area of the integrated circuit memory to achieve maximum integration, a trench-type transistor structure is generally adopted. When the trench-type transistor structure is in use, a leakage region is formed between the trench isolation structure and the gate structure of the storage transistor. Electrons between the source and drain regions of the storage transistor may migrate into the leakage region, thereby generating leakage current, causing the storage performance of the integrated circuit memory to decrease. Moreover, the larger the area of the leakage region, the smaller the equivalent resistance on the leakage path, and thus the larger the leakage current generated, and the worse the storage capacity of the integrated circuit memory. How to reduce the leakage current has become a problem to be solved urgently.

Summary of the invention

The object of the present invention is to provide a semiconductor device and a method for forming the same, so as to improve the storage performance of the existing semiconductor device.

In order to achieve the above object, the present invention provides a semiconductor device, comprising:

The semiconductor device includes a substrate and a trench isolation structure formed in the substrate, wherein the trench isolation structure defines a plurality of active regions in the substrate;

The trench isolation structure includes a first isolation portion and a second isolation portion, wherein the first isolation portion extends from the top surface of the substrate to the inside of the substrate to a first depth position, and the second isolation portion extends from the bottom of the first isolation portion to a second depth position and is connected to the first isolation portion, and the lateral width dimension of the second isolation portion in a direction perpendicular to the height direction is greater than the lateral width dimension of the first isolation portion in a direction perpendicular to the height direction, so that the second isolation portion protrudes laterally relative to the first isolation portion in a direction toward the active area;

The active region includes a source region and a drain region, and the source region extends from the top surface of the substrate to between a first depth position and a second depth position, so that the source region is further sunken into the drain region.

Optionally, a gate structure is formed in the substrate between the source region and the drain region, and the gate structure extends from the top surface of the substrate to the interior of the substrate to a third depth position, and the second isolation portion is located between the first depth position and the second depth position of the substrate, and the third depth position is higher than the second depth position and lower than the first depth position, so that the spacing dimension between the second isolation portion and the gate structure is smaller than the spacing dimension between the first isolation portion and the gate structure.

Optionally, the source region and the drain region extend from the top surface of the substrate to a fourth depth position and a fifth depth position respectively into the interior of the substrate, the fourth depth position being lower than the first depth position and higher than the third depth position so that the gate structure is further sunken into the source region, and the fifth depth position being higher than the first depth position so that the source region is further sunken into the drain region.

Optionally, the second isolation portion of the trench isolation structure is arc-shaped.

Optionally, the trench isolation structure includes an isolation material layer filled in an isolation trench, and the isolation material layer includes one or more of silicon oxide, free silicon oxide or silicon carbide oxide.

Optionally, the semiconductor device is applied to an integrated circuit memory, and the active area is used to constitute a transistor in the integrated circuit memory.

The present invention also provides a method for forming a semiconductor device, comprising:

A substrate is provided, wherein at least one isolation trench is formed in the substrate, wherein the isolation trench includes a first trench portion and a second trench portion, wherein the first trench portion extends from the top surface of the substrate to the inside of the substrate to a first depth position, and the second trench portion extends from below the first trench portion to a second depth position and is connected to the first trench portion, and the lateral width dimension of the second trench portion in a direction perpendicular to the height direction is greater than the lateral width dimension of the first trench portion in a direction perpendicular to the height direction; and,

Filling an isolation material layer in the isolation trench to form a trench isolation structure, wherein a portion of the trench isolation structure corresponding to the first trench portion constitutes a first isolation portion, and a portion of the trench isolation structure corresponding to the second trench portion constitutes a second isolation portion, and the second isolation portion protrudes laterally relative to the first isolation portion;

An active region is formed in the substrate, the source region includes a source region and a drain region, and the source region extends from the top surface of the substrate to between a first depth position and a second depth position so that the source region is further sunken into the drain region.

Optionally, the step of forming the isolation trench includes:

Performing a first etching process to etch the substrate to form the first trench portion of the isolation trench;

forming a protection layer on the sidewalls of the first groove portion; and,

A second etching process is performed on the substrate below the first trench portion, wherein the second etching process etches the substrate below the first trench portion simultaneously in a lateral direction and a longitudinal direction to form the second trench portion of the isolation trench.

Optionally, the first etching process is anisotropic dry etching, and the second etching process is isotropic wet etching.

Optionally, the step of forming the protective layer includes:

forming a protective material layer on the substrate, wherein the protective material layer covers the substrate and extends to cover the sidewalls and bottom wall of the first groove portion; and,

The portion of the protective material layer covering the substrate and the portion covering the bottom wall of the first groove portion is removed, and the portion of the protective material layer covering the side wall of the first groove portion is retained to form the protective layer.

Optionally, a first region for forming a source region and a second region for forming a drain region are defined in the substrate, and the step of forming the active region includes:

Performing a first ion implantation process on the substrate to form a first doped region of a first conductivity type in the substrate, wherein the first doped region extends from the top surface of the substrate to the inside of the substrate to a fourth depth position, the fourth depth position is between the first depth position and the second depth position, and the first doped region located in the first region constitutes the source region; and

A second ion implantation process is performed on the substrate of the second area to implant second conductive type ions in the first doping region, wherein the second conductive type ions extend from the bottom boundary of the first doping region to the top surface of the substrate to a fifth depth position, so that the portion of the first doping region from the bottom boundary to the fifth depth position forms a second doping region of the second conductive type, and the portion of the first doping region from the fifth depth position to the top surface of the substrate constitutes a drain region of the first conductive type, and the fifth depth position is higher than the first depth position, so that the source region is further sunken into the drain region.

Optionally, after performing the first ion implantation process on the substrate and before performing the second ion implantation process on the substrate in the second region, the method for forming the semiconductor device further includes:

Etching the substrate between the first region and the second region to form a gate trench, wherein the gate trench extends from the top surface of the substrate to the inside of the substrate to a third depth position;

A gate structure is formed in the gate trench, wherein the third depth position is lower than the fourth depth position and higher than the second depth position, so that the gate structure is further sunken into the source region.

In the semiconductor device and the formation method thereof provided by the present invention, a trench isolation structure is first formed in the substrate, and an active area is defined by the trench isolation structure. Since the trench isolation structure has a first isolation portion connected to each other and a second isolation portion located below the first isolation portion, and the lateral width dimension of the second isolation portion in a direction perpendicular to the height is greater than the lateral width dimension of the first isolation portion in a direction perpendicular to the height, the second isolation portion protrudes laterally relative to the first isolation portion, thereby reducing the area of the leakage region, thereby increasing the equivalent resistance on the leakage path, thereby reducing the leakage current and improving the storage performance of the semiconductor device. Furthermore, the source region extends from the top surface of the substrate to between the first depth position and the second depth position, further reducing the area of the leakage region, achieving a better effect of reducing the leakage current, and the source region is further sunken in the drain region to adjust the channel length to ensure that the channel of the semiconductor device does not change, and has little effect on the conduction performance of the device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a semiconductor device;

2 is a flow chart of a method for forming a semiconductor device according to an embodiment of the present invention;

3 to 12 are cross-sectional schematic diagrams of a semiconductor structure formed by the method for forming a semiconductor device provided by an embodiment of the present invention;

The reference numerals are as follows:

1’-substrate; 111’-drain region; 112’-drain region;

2’-trench isolation structure; 21’-isolation trench;

3’-gate structure;

W’-leakage area; W-leakage area

1-substrate; 11-first doping region; 111-source region; 112-drain region;

2-trench isolation structure; 21-isolation trench; 211-first trench portion; 212-second trench portion; 22-first isolation portion; 23-second isolation portion;

3-gate structure; 31-gate trench; 32-gate dielectric layer; 33-gate electrode layer; 34-insulating layer;

41-protective material layer; 4-protective layer;

H1 - first depth value;

H2 - second depth value;

H3 - third depth value;

H4 - fourth depth value;

H5 - fifth depth value;

h-the lateral width dimension of the second isolation portion in the direction perpendicular to the height;

h’: the lateral width dimension of the first isolating portion in the direction perpendicular to the height.

DETAILED DESCRIPTION

Figure 1 shows a semiconductor device, which includes a substrate 1' and a trench isolation structure 2' formed in the substrate 1'. The trench isolation structure 2' is used to define an active area. The trench isolation structure 2' includes an isolation material layer formed in an isolation trench 21'. An active area 111', a drain area 112' and a gate structure 3' are formed in each of the active areas. The gate structure 3' is located between the source area 111' and the drain area 112' to form a transistor. As shown in FIG1 , the trench isolation structure 2’ extends from the top surface of the substrate 1’ to the interior of the substrate 1’, and the lateral width dimensions of the entire trench isolation structure 2’ are substantially the same, resulting in a very large area of the leakage region W’ between the trench isolation structure 2’ and the gate structure 3’. When the transistor is in use, electrons migrate from the source region 111’ along the U-shaped channel region to the drain region 112’. Since the leakage area is very large, electrons are also easily migrated to the leakage region W’ to form a leakage current (as shown by the arrow in FIG1 ), affecting the storage performance of the device.

Based on this, the present invention provides a semiconductor device and a method for forming the same. First, a trench isolation structure is formed in the substrate, and an active area is defined by the trench isolation structure. Since the trench isolation structure has a first isolation portion connected to each other and a second isolation portion located below the first isolation portion, and the lateral width dimension of the second isolation portion in a direction perpendicular to the height is greater than the lateral width dimension of the first isolation portion in a direction perpendicular to the height, the second isolation portion protrudes laterally relative to the first isolation portion, thereby reducing the area of the leakage region, thereby increasing the equivalent resistance on the leakage path, thereby reducing the leakage current and improving the storage performance of the semiconductor device. Furthermore, the source region extends from the top surface of the substrate to between the first depth position and the second depth position, further reducing the area of the leakage region, achieving a better effect of reducing the leakage current, and the source region is further sunken into the drain region to adjust the channel length to ensure that the channel of the semiconductor device does not change, and has little effect on the conduction performance of the device.

The specific implementation of the present invention will be described in more detail below in conjunction with the schematic diagram. The advantages and features of the present invention will become clearer based on the following description. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

Please refer to FIG. 10 or FIG. 11 , the present embodiment provides a semiconductor device, the semiconductor device comprising a substrate 1 and a trench isolation structure 2 formed in the substrate 1, the trench isolation structure 2 defining a plurality of active regions in the substrate 1; wherein the trench isolation structure 2 comprises a first isolation portion 22 and a second isolation portion 23, the first isolation portion 22 extending from the top surface of the substrate 1 to the inside of the substrate 1 to a first depth position (i.e., a position extending from the top surface of the substrate 1 to the inside of the substrate 1 at a first depth value H1), and the second isolation portion 23 extending from below the first isolation portion 22 to a second depth position (i.e., The second isolation portion 23 extends from the top surface of the substrate 1 to the inside of the substrate 1 to a position of a second depth value H2) and is connected to the first isolation portion 22, and the lateral width dimension h' of the second isolation portion 23 in the direction perpendicular to the height is greater than the lateral width dimension h of the first isolation portion 22 in the direction perpendicular to the height, so that the second isolation portion 23 protrudes laterally relative to the first isolation portion 22 in the direction toward the active area; the active area includes a source region 111 and a drain region 112, and the source region 111 extends from the top surface of the substrate 1 to between the first depth position and the second depth position, so that the source region 111 is further sunken into the drain region 112.

Specifically, the trench isolation structure 2 is used to isolate adjacent active areas, and the trench isolation structure 2 includes an isolation material layer formed in an isolation trench 21, the isolation trench 21 extends from the top surface of the substrate 1 to the inside of the substrate 1 to a second depth position, the isolation material layer is filled in the isolation trench 21, and the isolation material layer is not higher than the top opening of the isolation trench 21. Optionally, the isolation material layer includes one or more of silicon oxide, free silicon oxide or silicon carbide oxide.

Furthermore, a gate structure 3 is formed in the substrate 1 between the source region 111 and the drain region 112, and the gate structure 3 extends from the top surface of the substrate 1 to the inside of the substrate 1 to a third depth position (i.e., a position of a third depth value H3 extending from the top surface of the substrate 1 to the inside of the substrate 1), and the second isolation portion 23 is located between the first depth position and the second depth position of the substrate 1, and the third depth position is higher than the second depth position and lower than the first depth position, that is, the bottom of the gate structure 3 is located between the first depth position and the second depth position.

In this embodiment, the bottom of the isolation trench 21 is laterally protruding relative to the top thereof, that is, the lateral width dimension of the bottom of the isolation trench 21 in the direction perpendicular to the height is greater than the lateral width dimension of the top thereof, the isolation material layer filled between the top and the bottom of the isolation trench 21 constitutes the first isolation portion 22, and the isolation material layer filled at the bottom of the isolation trench 21 constitutes the second isolation portion 23, so that the bottom of the formed trench isolation structure 2 is also laterally protruding, so that the spacing dimension between the second isolation portion 23 and the gate structure 3 is smaller than the spacing dimension between the first isolation portion 22 and the gate structure 3, so as to reduce the area of the leakage region W. Furthermore, the second isolation portion 23 of the trench isolation structure 2 is arc-shaped, and the outwardly protruding portion of the isolation trench 21 is also arc-shaped, so that the process of forming the trench isolation structure is simpler. Since the second isolation portion 23 of the trench isolation structure 2 protrudes laterally relative to the first isolation portion 22, the area of the leakage region W between the trench isolation structure 2 and the gate structure 3 in the active area is reduced, thereby reducing the equivalent resistance on the leakage channel, thereby reducing the leakage current and improving the storage performance of the device.

Optionally, the source region 111 and the drain region 112 extend from the top surface of the substrate 1 to the inside of the substrate 1 to a fourth depth position (i.e., a position where a fourth depth value H4 is extended from the top surface of the substrate 1 to the inside of the substrate 1) and a fifth depth position (i.e., a position where a fifth depth value H5 is extended from the top surface of the substrate 1 to the inside of the substrate 1), respectively. The fourth depth position is lower than the first depth position and higher than the third depth position, so that the gate structure 3 is further sunken into the source region 111, so that the U-shaped area along the bottom of the gate structure 3 constitutes a channel of the transistor, and the fifth depth position is higher than the first depth position, so that the source region 111 is further sunken into the drain region 112. Since the source region 111 is lower than the source region 111' in Figure 1, in order to ensure that the length of the channel of the transistor does not change, the position of the drain region 112 can be correspondingly increased to ensure that the length of the channel remains unchanged and will not affect the conduction performance of the semiconductor device.

Furthermore, the semiconductor device can be applied to an integrated circuit memory, and the active region is used to constitute a transistor in the integrated circuit memory.

As shown in FIG. 2 , this embodiment further provides a method for forming a semiconductor device, comprising:

S1: providing a substrate, wherein at least one isolation trench is formed in the substrate, wherein the isolation trench comprises a first trench portion and a second trench portion, wherein the first trench portion extends from the top surface of the substrate to the inside of the substrate to a first depth position, and the second trench portion extends from below the first trench portion to a second depth position and is connected to the first trench portion, and the lateral width dimension of the second trench portion in a direction perpendicular to the height direction is greater than the lateral width dimension of the first trench portion in a direction perpendicular to the height direction; and,

S2: filling an isolation material layer in the isolation trench to form a trench isolation structure, wherein a portion of the trench isolation structure corresponding to the first trench portion constitutes a first isolation portion, and a portion of the trench isolation structure corresponding to the second trench portion constitutes a second isolation portion, and the second isolation portion protrudes laterally relative to the first isolation portion;

S3: forming an active region in the substrate, wherein the source region includes a source region and a drain region, and the source region extends from the top surface of the substrate to between a first depth position and a second depth position, so that the source region is further sunken into the drain region.

Specifically, first refer to FIG3 , a substrate 1 is provided, and a first etching process is performed on the substrate 1 to form a first groove portion 211 in the first substrate 1, wherein the first groove portion 211 extends from the top surface of the substrate 1 to the inside of the substrate 1 to a first depth position. Optionally, the first etching process is anisotropic dry etching to form a vertically downward blind hole in the substrate 1, and the lateral width dimension h' of the first groove portion 211 in the direction perpendicular to the height is substantially the same.

Next, as shown in FIG. 4 , a protective material layer 41 is formed on the substrate 1, the protective material layer 4 covers the substrate 1 and extends to cover the side walls and bottom walls of the first groove portion 211, and then an etching process is used to remove the portion of the protective material layer 41 covering the substrate 1 and the bottom wall of the first groove portion 211, and the portion of the protective material layer 41 covering the side walls of the first groove portion 211 is retained to form the protective layer 4 on the side walls of the first groove portion 211, as specifically shown in FIG. 5 .

Then, the second etching process is performed on the substrate 1 at the bottom of the first groove portion 211 using the protective layer 4 as a mask to form the second groove portion 212. The first groove portion 211 and the second groove portion 212 together constitute the isolation groove 21. The second groove portion 212 is located below the first groove portion 211 and extends to the inside of the substrate 1 to a second depth position. Optionally, the second etching process is isotropic wet etching. The etching liquid flows through the first groove portion 211 and etches the substrate 1 below the first groove portion 211 in the horizontal and vertical directions to form the second groove portion 212. Since the sidewalls of the first groove portion 211 are protected by the protective layer 4, the sidewalls of the first groove portion 211 will not be etched. After the substrate 1 at the bottom of the first groove portion 211 is isotropically etched, the lateral width dimension of the second groove portion 212 formed in the direction perpendicular to the height is greater than the lateral width dimension of the first groove portion 211 in the direction perpendicular to the height, as shown in FIG. 6.

Next, as shown in FIG7 , an isolation material layer is filled in the isolation trench 21 to form the trench isolation structure 2. It can be understood that the portion of the trench isolation structure 2 corresponding to the first trench portion 211 constitutes a first isolation portion 22, and the portion of the trench isolation structure 2 corresponding to the second trench portion 212 constitutes a second isolation portion 23, and the second isolation portion 23 protrudes laterally relative to the first isolation portion 22. At this time, the trench isolation structure 2 has been formed, and the region where the active region is formed is defined by the trench isolation structure 2. Then, a first ion implantation process is performed to form a first conductive type first doping region 11 in the substrate 1, and the bottom boundary of the first doping region 11 is located at the fourth depth position, and the fourth depth position is located between the first depth position and the second depth position, as shown in FIG8 .

Further, as shown in Figures 9 and 10, the substrate 1 is etched to form a gate trench 31 corresponding to the gate area, and the gate trench 31 is used to define a first area for forming a source area and a second area for forming a drain area, and then a gate structure 3 is formed in the gate trench 31. The steps of forming the gate structure 3 may be: as shown in Figure 10, a gate dielectric layer 32 is formed on the bottom wall and side wall of the gate trench 31, and the gate dielectric layer 32 may be a silicon oxide material, and then a gate electrode layer 33 and an insulating layer 34 are filled in the gate trench 31, the gate electrode layer 33 is located in the lower part of the gate trench 31, and the insulating layer 34 is located in the upper part of the gate trench 31, so that the insulating layer 34 covers the gate electrode layer 33 to isolate and protect the gate electrode layer 33. Optionally, the filling depth of the gate electrode layer 33 is greater than the filling depth of the insulating layer 34. It can be understood that the gate trench 31 extends from the top surface of the substrate 1 to the inside of the substrate 1 to a third depth position, and the third depth position is located between the first depth position and the second depth position, so that the gate structure 3 is further sunken into the first doping region 11.

Further, as shown in Figure 10, the first doping region 11 located in the first area constitutes the source region 111, that is, the bottom boundary of the source region 111 is located at the fourth depth position, the fourth depth position is lower than the first depth position and higher than the third depth position, and then the second ion implantation process is performed on the substrate 1 of the second area to implant the second conductive type ions in the first doping region 11, the second conductive type ions extend from the bottom boundary of the first doping region 11 to the top surface of the substrate 1 to the fifth depth position, so that the first doping region 11 forms a second doping region of the second conductive type from the bottom boundary to the fifth depth position (the first conductive type is opposite to the second conductive type, so that the second doping region and the substrate 1 are integrated), and the portion of the first doping region 11 from the fifth depth position to the top surface of the substrate 1 constitutes a drain region 112 of the first conductive type (that is, the drain region 112 extends from the top surface of the substrate 1 to the inside of the substrate 1 to the fifth depth position), and the fifth depth position is higher than the first depth position, so that the source region 111 is further sunken into the drain region 112.

As shown in FIG11 , two gate structures 3 can be formed in each active area to form two transistors, and the drain regions 111 of the two transistors are shared to form a transistor pair, thereby improving the density of the device. It can be understood that, as shown in FIG10 , there may be only one gate structure 3 in each active area, and the present invention does not limit this.

In summary, in the semiconductor device and the formation method thereof provided in the embodiment of the present invention, a trench isolation structure is first formed in the substrate, and an active area is defined by the trench isolation structure. Since the trench isolation structure has a first isolation portion connected to each other and a second isolation portion located below the first isolation portion, and the lateral width dimension of the second isolation portion in the direction perpendicular to the height is greater than the lateral width dimension of the first isolation portion in the direction perpendicular to the height, the second isolation portion protrudes laterally relative to the first isolation portion, thereby reducing the area of the leakage region, thereby increasing the equivalent resistance on the leakage path, thereby reducing the leakage current and improving the storage performance of the semiconductor device. Furthermore, the source region extends from the top surface of the substrate to between the first depth position and the second depth position, further reducing the area of the leakage region, achieving a better effect of reducing the leakage current, and the source region is further sunken in the drain region to adjust the channel length to ensure that the channel of the semiconductor device does not change, and has little effect on the conduction performance of the device.

The above is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the content of the technical solution of the present invention and still falls within the protection scope of the present invention.

Claims (11)

1. A semiconductor device, characterized in that the semiconductor device comprises a substrate and a trench isolation structure formed in the substrate, wherein the trench isolation structure defines a plurality of active regions in the substrate; The trench isolation structure includes a first isolation portion and a second isolation portion, wherein the first isolation portion extends from the top surface of the substrate to the inside of the substrate to a first depth position, and the second isolation portion extends from the bottom of the first isolation portion to a second depth position and is connected to the first isolation portion, and the lateral width dimension of the second isolation portion in a direction perpendicular to the height direction is greater than the lateral width dimension of the first isolation portion in a direction perpendicular to the height direction, so that the second isolation portion protrudes laterally relative to the first isolation portion in a direction toward the active area, and the second isolation portion of the trench isolation structure is arc-shaped; The active region includes a source region and a drain region, and the source region extends from the top surface of the substrate to between a first depth position and a second depth position, so that the source region is further sunken than the drain region, the source region extends from the top surface of the substrate to a fourth depth position toward the inside of the substrate, and the drain region extends from the top surface of the substrate to a fifth depth position toward the inside of the substrate, and the fourth depth position is lower than the fifth depth position; Two gate structures are formed in each of the active regions. The gate structure is located between the source region and the drain region. The source region is located between the trench isolation structure and the gate structure. The drain region is located between the two gate structures. 2. The semiconductor device as described in claim 1 is characterized in that the gate structure extends from the top surface of the substrate to the inside of the substrate to a third depth position, the second isolation portion is located between the first depth position and the second depth position of the substrate, and the third depth position is higher than the second depth position and lower than the first depth position, so that the spacing dimension between the second isolation portion and the gate structure is smaller than the spacing dimension between the first isolation portion and the gate structure. 3. The semiconductor device as described in claim 2 is characterized in that the fourth depth position is lower than the first depth position and higher than the third depth position, so that the gate structure is further sunken into the source region, and the fifth depth position is higher than the first depth position, so that the source region is further sunken into the drain region. 4 . The semiconductor device according to claim 1 , wherein the trench isolation structure comprises an isolation material layer filled in an isolation trench, and the isolation material layer comprises one or more of silicon oxide, free silicon oxide or silicon carbide oxide. 5. The semiconductor device according to any one of claims 1 to 4, characterized in that the semiconductor device is applied to an integrated circuit memory, and the active area is used to constitute a transistor in the integrated circuit memory. 6. A method for forming a semiconductor device, comprising: A substrate is provided, wherein at least one isolation trench is formed in the substrate, wherein the isolation trench includes a first trench portion and a second trench portion, wherein the first trench portion extends from the top surface of the substrate to the inside of the substrate to a first depth position, and the second trench portion extends from below the first trench portion to a second depth position and is connected to the first trench portion, and the lateral width dimension of the second trench portion in a direction perpendicular to the height direction is greater than the lateral width dimension of the first trench portion in a direction perpendicular to the height direction; and, Filling an isolation material layer in the isolation trench to form a trench isolation structure, wherein a portion of the trench isolation structure corresponding to the first trench portion constitutes a first isolation portion, and a portion of the trench isolation structure corresponding to the second trench portion constitutes a second isolation portion, and the second isolation portion protrudes laterally relative to the first isolation portion, and the second isolation portion of the trench isolation structure is arc-shaped; An active region is formed in the substrate, the source region includes a source region and a drain region, and the source region extends from the top surface of the substrate to between a first depth position and a second depth position, so that the source region is further sunken than the drain region, the source region extends from the top surface of the substrate to a fourth depth position toward the inside of the substrate, the drain region extends from the top surface of the substrate to a fifth depth position toward the inside of the substrate, and the fourth depth position is lower than the fifth depth position; Two gate structures are formed in each of the active regions. The gate structure is located between the source region and the drain region. The source region is located between the trench isolation structure and the gate structure. The drain region is located between the two gate structures. 7. The method for forming a semiconductor device according to claim 6, wherein the step of forming the isolation trench comprises: Performing a first etching process to etch the substrate to form the first trench portion of the isolation trench; forming a protection layer on the sidewalls of the first groove portion; and, A second etching process is performed on the substrate below the first trench portion, wherein the second etching process etches the substrate below the first trench portion simultaneously in a lateral direction and a longitudinal direction to form the second trench portion of the isolation trench. 8 . The method for forming a semiconductor device according to claim 7 , wherein the first etching process is anisotropic dry etching, and the second etching process is isotropic wet etching. 9. The method for forming a semiconductor device according to claim 7, wherein the step of forming the protective layer comprises: forming a protective material layer on the substrate, wherein the protective material layer covers the substrate and extends to cover the sidewalls and bottom wall of the first groove portion; and, The portion of the protective material layer covering the substrate and the portion covering the bottom wall of the first groove portion is removed, and the portion of the protective material layer covering the side wall of the first groove portion is retained to form the protective layer. 10. The method for forming a semiconductor device according to claim 6, wherein a first region for forming a source region and a second region for forming a drain region are defined in the substrate, and the step of forming the active region comprises: Performing a first ion implantation process on the substrate to form a first doped region of a first conductivity type in the substrate, wherein the first doped region extends from the top surface of the substrate to the inside of the substrate to a fourth depth position, the fourth depth position is between the first depth position and the second depth position, and the first doped region located in the first region constitutes the source region; and A second ion implantation process is performed on the substrate of the second area to implant second conductive type ions in the first doping region, wherein the second conductive type ions extend from the bottom boundary of the first doping region to the top surface of the substrate to a fifth depth position, so that the portion of the first doping region from the bottom boundary to the fifth depth position forms a second doping region of the second conductive type, and the portion of the first doping region from the fifth depth position to the top surface of the substrate constitutes a drain region of the first conductive type, and the fifth depth position is higher than the first depth position, so that the source region is further sunken into the drain region. 11. The method for forming a semiconductor device according to claim 10, wherein after performing a first ion implantation process on the substrate and before performing a second ion implantation process on the substrate in the second region, forming two gate structures in each of the active regions comprises: Etching the substrate between the first region and the second region to form a gate trench, wherein the gate trench extends from the top surface of the substrate to the inside of the substrate to a third depth position; A gate structure is formed in the gate trench, wherein the third depth position is lower than the fourth depth position and higher than the second depth position, so that the gate structure is further sunken into the source region.