CN111161769B

CN111161769B - Flash chip and reading method thereof

Info

Publication number: CN111161769B
Application number: CN201911388851.7A
Authority: CN
Inventors: 刘梦
Original assignee: XTX Technology Shenzhen Ltd
Current assignee: Xtx Technology Inc
Priority date: 2019-12-30
Filing date: 2019-12-30
Publication date: 2020-10-20
Anticipated expiration: 2039-12-30
Also published as: CN111161769A

Abstract

The invention relates to a Flash chip and a reading method thereof; the Flash chip comprises a timer (30) used for acquiring an internal time signal (32), and a reading circuit (40) which is electrically connected with the timer (30) and used for acquiring the internal time signal (32) acquired by the timer (30) and starting or stopping according to the internal time signal (32); the frequency of the internal time signal (32) is constant. The Flash chip and the reading method thereof have novel design and strong practicability.

Description

Flash chip and reading method thereof

Technical Field

The invention relates to the technical field of memories, in particular to a Flash chip and a reading method thereof.

Background

In Flash chips, the read circuit is one of the important components. When a user applies a Flash chip, the Flash chip is expected to work at a high frequency, which requires that the Flash chip can accurately read data of a storage unit at the high frequency. In general, the lower the reading frequency of the Flash chip is, the longer the working time of the reading circuit is, and the larger the power consumption of the reading circuit is. If the reading circuit has the capability of accurately reading the data of the storage unit at a high frequency, the power consumption of the reading circuit and the Flash chip for reading the data at a low frequency from the high frequency becomes very large, which puts higher requirements on the power supply of the peripheral circuit and possibly causes the abnormal work of the whole system.

Disclosure of Invention

The invention provides a Flash chip and a reading method thereof aiming at the technical problems.

The technical scheme provided by the invention is as follows:

the invention provides a Flash chip, which comprises a timer for acquiring an internal time signal, and a reading circuit, wherein the reading circuit is electrically connected with the timer and is used for acquiring the internal time signal acquired by the timer and starting or stopping the reading circuit according to the internal time signal; the frequency of the internal time signal is constant.

In the Flash chip of the present invention, the read circuit includes a comparator, a storage unit and a voltage source; the memory cell includes a transistor; the inverting input end of the comparator is grounded after passing through a voltage source; the non-inverting input end of the comparator is connected with the drain electrode of the transistor of the storage unit, and the source electrode of the transistor of the storage unit is grounded; the gate of the transistor of the memory cell is used for controlling the working time of the memory cell by an internal time signal with constant frequency.

In the Flash chip of the present invention, a bias voltage generating circuit is respectively connected between the inverting input terminal of the comparator and the voltage source, and between the non-inverting input terminal of the comparator and the drain of the transistor of the memory cell.

The invention also provides a reading method of the Flash chip, which comprises the following steps:

step S1, acquiring an internal time signal by using a timer; the frequency of the internal time signal is constant;

and step S2, starting or stopping the reading circuit according to the internal time signal.

The Flash chip and the reading method thereof control the working time of the storage unit by adopting the internal time signal with constant frequency, so that the working time of the reading circuit is not influenced by the working frequency of the Flash chip. The Flash chip and the reading method thereof have novel design and strong practicability.

Drawings

The invention will be further described with reference to the accompanying drawings and examples, in which:

FIG. 1 shows a circuit diagram of a read circuit;

FIG. 2 is a functional block diagram of a Flash chip;

fig. 3 shows a functional module diagram of a Flash chip according to a preferred embodiment of the present invention.

Detailed Description

In order to make the technical purpose, technical solutions and technical effects of the present invention more clear and facilitate those skilled in the art to understand and implement the present invention, the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments.

As shown in fig. 1, fig. 1 shows a circuit diagram of a read circuit. The working principle of the reading circuit is as follows: the inverting input end of the comparator A is connected with the reference current branch 20, and the non-inverting input end of the comparator A is connected with the storage unit branch 10; if the memory cell is a programmed memory cell (pgm cell), the turn-on Voltage (VTH) is higher, and no current flows in the memory cell at the time, and the voltage of the non-inverting input terminal of the comparator a is higher than the voltage of the inverting input terminal of the comparator a; if the memory cell is an erase cell (erase cell), a large current flows through the memory cell at the time when the turn-on Voltage (VTH) is low, and the voltage at the non-inverting input terminal of the comparator a is lower than the voltage at the inverting input terminal of the comparator a. The comparator A outputs a result, namely Data _ out according to the voltage of the non-inverting input end and the voltage of the inverting input end.

During the operation of the reading circuit, the reference current branch 20 and the comparator a generate power consumption, which is assumed to be 50 nA. Since the Flash chip needs to operate at a high frequency, the data bus width is generally increased and the current of the reference current branch 20 is increased.

In the aspect of expanding the width of the data bus, along with the increase of the capacity of the Flash chip, the width of the data bus is increased; the data bus width of a conventional 128-Mbit Flash chip is 128 bits, and if the 128-Mbit Flash chip adopts a read circuit as shown in fig. 1, the power consumption during the operation of the read circuit is 50nA × 128 — 6.4 uA;

in the aspect of increasing the current of the reference current branch 20, increasing the current of the reference current branch 20 will increase the corresponding time of the read circuit, so that the Flash chip can operate at a higher frequency. When the read circuit shown in fig. 1 is used for the Flash chip, if the current of the reference current branch 20 is doubled, the power consumption of a single read circuit is 50nA × 2 — 100 nA.

When the read circuit shown in fig. 1 is used for a Flash chip with a 128Mbit capacity, if the current of the reference current branch 20 is increased while the data bus width is increased, the power consumption of the read circuit is 100nA × 128 — 12.8 uA.

If the calculation result of the power consumption of the read circuit of 12.8uA is calculated based on the operating time of the read circuit of 50ns, then if the operating time of the read circuit is 5000ns, the power consumption of the read circuit should be 12.8uA × 100 ═ 12.8 mA.

To sum up, the power consumption of the read circuit of the Flash chip ∞ varies from the data bus width of the Flash chip × the current of the reference current branch 20 × the operating time of the read circuit.

As shown in fig. 2, fig. 2 shows a functional module schematic diagram of a Flash chip. The Flash chip comprises a timer 30 used for obtaining an external time signal 31 corresponding to the reading frequency of the Flash chip, and a reading circuit 40 which is electrically connected with the timer 30 and used for obtaining the external clock signal 31 obtained by the timer 30 and starting or stopping according to the external clock signal 31. The external time signal 31 is an external clk signal. Therefore, the operating time of the read circuit 40 is related to the read frequency of the Flash chip, generally, the read frequency of the Flash chip needs to satisfy 100Mhz, and assuming that the operating time of the read circuit 30 at the read frequency of the Flash chip of 100Mhz is 5T, i.e., 50ns, and the power consumption is 12.8uA, when the read frequency of the Flash chip is 1Mhz, the read power consumption is 12.8uA × 100 ═ 12.8 mA.

The results show that: when a user applies the same Flash chip at high frequency and low frequency respectively, the difference between the power consumption of the Flash chip and the power consumption of the Flash chip is huge. The reading circuit has high power consumption at a low reading speed, which directly causes the high power consumption of the Flash chip, puts higher requirements on the power supply of peripheral circuits and possibly causes the abnormal work of the whole system.

As shown in fig. 3, fig. 3 is a functional module diagram of a Flash chip according to a preferred embodiment of the present invention. The Flash chip comprises a timer 30 for acquiring an internal time signal 32, and a reading circuit 40 which is electrically connected with the timer 30 and used for acquiring the internal time signal 32 acquired by the timer 30 and starting or stopping according to the internal time signal 32; the frequency of the internal time signal 32 is constant.

In this embodiment, the operating time of the read circuit 40 is determined by the internal time signal 32 of the Flash chip, and is not affected by the operating frequency of the Flash chip when the frequency of the internal time signal 32 is constant. Assuming that the minimum working time required by the read circuit 40 of the Flash chip to work normally is known to be 50ns, the working time of the read circuit 40 is fixed to 50ns, and the working time of the read circuit 40 is constant to 50ns no matter whether the external frequency of the Flash chip is 100Mhz or 1Mhz, and the power consumption of the read circuit 40 during the read operation is unchanged. The internal time signal 32 is an internal clk signal.

Specifically, as shown in fig. 1, the reading circuit 40 includes a comparator a, a memory cell 11, and a voltage source 21; the memory cell 11 includes a transistor; the inverting input end of the comparator A is grounded after passing through a voltage source 21; the non-inverting input end of the comparator A is connected with the drain electrode of the transistor of the storage unit 11, and the source electrode of the transistor of the storage unit 11 is grounded; the gate of the transistor of the memory cell 11 is used to control the operation time of the memory cell 11 by the internal time signal 32 with constant frequency, so that the operation time of the read circuit 40 is not affected by the operation frequency of the Flash chip.

Further, in the present embodiment, the bias voltage generating circuit 50 is connected between the inverting input terminal of the comparator a and the voltage source 21 and between the non-inverting input terminal of the comparator a and the drain of the transistor of the memory cell 11, respectively.

Further, the present invention also provides a method for reading the Flash chip, which includes the following steps:

step S1, acquiring an internal time signal 32 by using the timer 30; the frequency of the internal time signal 32 is constant;

step S2, the read circuit 40 is turned on or off according to the internal time signal 32.

Specifically, the internal time signal 32 is an internal clk signal.

While the present invention has been described with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, which are illustrative and not restrictive, and it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A Flash chip is characterized by comprising a timer (30) used for acquiring an internal time signal (32), and a reading circuit (40) which is electrically connected with the timer (30) and used for acquiring the internal time signal (32) acquired by the timer (30) and starting or stopping according to the internal time signal (32); the frequency of the internal time signal (32) is constant;

the reading circuit (40) comprises a comparator (A), a memory cell (11) and a voltage source (21); the memory cell (11) comprises a transistor; the inverting input end of the comparator (A) is grounded after passing through a voltage source (21); the non-inverting input end of the comparator (A) is connected with the drain electrode of the transistor of the storage unit (11), and the source electrode of the transistor of the storage unit (11) is grounded; the gate of the transistor of the memory cell (11) is used to control the operating time of the memory cell (11) by means of an internal time signal (32) of constant frequency.

2. The Flash chip according to claim 1, characterized in that a bias voltage generating circuit (50) is connected between the inverting input of the comparator (a) and the voltage source (21) and between the non-inverting input of the comparator (a) and the drain of the transistor of the memory cell (11), respectively.

3. A method for reading a Flash chip according to claim 1 or 2, characterized in that it comprises the following steps:

step S1, acquiring an internal time signal (32) by adopting a timer (30); the frequency of the internal time signal (32) is constant;

step S2, the read circuit (40) is turned on or off according to the internal time signal (32).