CN111176023A - Display panel and display device with increased segment difference - Google Patents
Display panel and display device with increased segment difference Download PDFInfo
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- CN111176023A CN111176023A CN201811338881.2A CN201811338881A CN111176023A CN 111176023 A CN111176023 A CN 111176023A CN 201811338881 A CN201811338881 A CN 201811338881A CN 111176023 A CN111176023 A CN 111176023A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1339—Gaskets; Spacers; Sealing of cells
- G02F1/13394—Gaskets; Spacers; Sealing of cells spacers regularly patterned on the cell subtrate, e.g. walls, pillars
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
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- G—PHYSICS
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
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Abstract
The invention is suitable for the technical field of display, and provides a display panel and a display device for increasing a section difference, which comprise a first substrate and a second substrate which are oppositely arranged; the first substrate comprises a first base layer; the second substrate comprises a second base layer, a dielectric layer, a semiconductor heightening layer and a metal heightening layer, and the second base layer, the dielectric layer, the semiconductor heightening layer and the metal heightening layer are arranged in the dielectric layer and correspond to the main spacer; the avoiding groove is formed in the medium layer and corresponds to the auxiliary spacer. According to the invention, the semiconductor heightening layer, the metal heightening layer and the avoiding groove are arranged, the main spacer is opposite to the semiconductor heightening layer and the metal heightening layer, the auxiliary spacer is opposite to the avoiding groove and can extend into the avoiding groove, so that the section difference of the panel is increased, the increased quantity is the sum of the thickness of the heightening part and the depth of the avoiding groove, the sum of the thicknesses of the semiconductor heightening layer and the metal heightening layer and the thickness of the medium layer can be increased to the maximum, the section difference is effectively increased, the liquid crystal redundancy is increased, and the quality of the panel is improved.
Description
Technical Field
The invention belongs to the technical field of display, and particularly relates to a display panel and a display device for increasing a section difference.
Background
The liquid crystal display panel is mainly formed by pairing a Color Filter (CF) substrate and a Thin Film Transistor (TFT) array substrate at a certain distance and sealing the periphery, and the structure formed by the two substrates in pair is also called a liquid crystal cell, and the liquid crystal material is filled in the liquid crystal cell. The CF substrate is a key material for realizing color display of the liquid crystal display, and affects optical characteristics such as display brightness and contrast. The CF substrate mainly includes a Glass Substrate (GS), a Black Matrix (BM), a Color Resist (CR), ITO (Indium tin oxide), and a column Spacer (PS). The PS is used to maintain a stable gap between the TFT substrate and the CF substrate.
In the liquid crystal cell, there are two types of PS, one is a Main PS (Main-PS, MPS) that normally maintains a cell gap, and the other is a Sub-PS (SPS) that serves as a support when the cell thickness becomes small. Under abnormal conditions, for example, when the temperature is too high, the liquid crystal volume expands, the MPS supporting force decreases, the liquid crystal locally gathers together after expanding, and gravity Mura (uneven brightness, speckles) appears, and the boundary liquid crystal amount where the gravity Mura appears is defined as L1; when the temperature is too low, the volume of the liquid crystal is reduced, the thickness of the liquid crystal box is reduced, the SPS generates a supporting force to prevent the thickness of the liquid crystal box from further reducing, and at the moment, vacuum bubbles possibly appear in a local space due to no liquid crystal, and the boundary liquid crystal amount of the vacuum bubbles is defined as L2. The amount of liquid crystal between L1 and L2, called LC margin (liquid crystal redundancy), within which gravity mura and vacuum bubbles do not occur, is as large as reasonably possible.
MPS and SPS successively contact with the TFT substrate along with the reduction of the liquid crystal cell gap to generate PS section difference, when the section difference is too small, the liquid crystal can not be ensured to be filled with the liquid crystal cell after being shrunk, and then vacuum bubbles are easily generated, so that the LC margin is too small, and the proper section difference is a necessary condition for ensuring the LC margin which is large enough and is also an important factor for improving the quality of the liquid crystal display panel. Therefore, a new scheme for increasing the step difference needs to be provided to increase the LC margin.
Disclosure of Invention
The invention aims to provide a display panel with an increased step, and aims to solve the technical problem that LCmargin of the display panel is small.
The invention is realized in such a way that the display panel with the increased step difference comprises a first substrate and a second substrate which are oppositely arranged;
the first substrate includes:
a first base layer;
a main spacer disposed on the first base layer; and
a sub spacer disposed on the first base layer;
the second substrate includes:
the second base layer is arranged opposite to the first base layer at intervals;
the dielectric layer is arranged on one side, close to the first base layer, of the second base layer;
the semiconductor heightening layer and the metal heightening layer are overlapped in the medium layer and correspond to the main spacer; and
and the avoidance groove is formed in the dielectric layer, corresponds to the auxiliary spacer and can be used for the auxiliary spacer to extend into.
In one embodiment, the dielectric layer comprises a first protective layer and a second protective layer which are laminated and arranged on the second base layer;
the semiconductor heightening layer and the metal heightening layer are arranged between the first protective layer and the second protective layer, and the semiconductor heightening layer and the metal heightening layer push corresponding parts of the second protective layer to abut against the main spacer.
In one embodiment, the second substrate further includes a driving circuit including a first metal layer, a semiconductor active layer, a second metal layer, and a pixel electrode, the first metal layer being disposed between the second base layer and the first protective layer, the semiconductor active layer and the second metal layer being disposed between the first protective layer and the second protective layer, the pixel electrode being disposed on a side of the second protective layer adjacent to the first substrate;
the semiconductor enhancement layer and the semiconductor active layer are formed on the first protective layer at intervals in the same process;
the metal heightening layer and the second metal layer are formed at intervals in the same process, wherein the metal heightening layer is formed on the semiconductor heightening layer, and the second metal layer is formed on the semiconductor active layer.
In one embodiment, the semiconductor enhancement layer and the semiconductor active layer have the same thickness; and/or
The metal heightening layer and the second metal layer have the same thickness.
In one embodiment, the thickness of the semiconductor enhancement layer is greater than the thickness of the semiconductor active layer; and/or
The thickness of the metal enhancement layer is greater than the thickness of the second metal layer.
In one embodiment, the second metal layer includes a data line, a source electrode and a drain electrode, and a distance between the metal boosting layer and the data line is greater than 5 μm.
In one embodiment, the first metal layer comprises a gate and a scan line, the scan line and the data line intersect to form a plurality of sub-pixel regions arranged in an array, and in one of the sub-pixel regions, the semiconductor heightening layer and the metal heightening layer are arranged close to the scan line and on the same side of the scan line as the gate; in another sub-pixel region, the avoiding groove is arranged close to the scanning line and is arranged on the same side of the scanning line with the grid electrode.
In one embodiment, the first substrate further includes a black matrix covering the data lines and the scan lines, the main spacer and the sub spacer are disposed on the black matrix, and the avoidance groove, the semiconductor elevation layer, and the metal elevation layer are covered by the black matrix.
In one embodiment, the area of the bottom of the avoidance slot is greater than or equal to the area of the free end of the secondary spacer;
the depth of the avoidance groove is smaller than the thickness of the second protective layer; or
The depth of the avoidance groove is equal to the thickness of the second protective layer; or
The depth of the avoiding groove is larger than the thickness of the second protective layer and smaller than the thickness of the dielectric layer; or
The depth of the avoiding groove is equal to the thickness of the dielectric layer.
Another object of the present invention is to provide a display device with an increased step, comprising a first substrate and a second substrate oppositely disposed;
the first substrate includes:
a first base layer;
a main spacer disposed on the first base layer; and
a sub spacer disposed on the first base layer;
the second substrate includes:
the second base layer is arranged opposite to the first base layer at intervals;
the first protective layer is arranged on one side, close to the first base layer, of the second base layer;
the second protective layer is arranged on one side, close to the first base layer, of the first protective layer;
the driving circuit comprises a first metal layer, a semiconductor active layer, a second metal layer and a pixel electrode, wherein the first metal layer is arranged between the second base layer and the first protective layer, the semiconductor active layer and the second metal layer are arranged between the first protective layer and the second protective layer, and the pixel electrode is arranged on the second protective layer;
the display device further includes:
the semiconductor enhancement layer is arranged between the first protective layer and the second protective layer and is formed by the same process with the semiconductor active layer;
the metal enhancement layer is arranged between the semiconductor enhancement layer and the second protective layer and is formed by the same process with the second metal layer;
the semiconductor and metal enhancement layers correspond to the main spacer; and
and the avoidance groove is formed from the surface of the second protective layer to the direction of the second base layer, corresponds to the auxiliary spacer and can be used for the auxiliary spacer to extend into.
According to the display panel and the display device with the increased section difference, the semiconductor heightening layer and the metal heightening layer are arranged on the second base layer of the second substrate, the avoidance groove is formed in the medium layer of the second substrate, the main spacer is opposite to the semiconductor heightening layer and the metal heightening layer, the auxiliary spacer is opposite to the avoidance groove and can extend into the avoidance groove, the section difference of the panel is increased due to the arrangement of the semiconductor heightening layer, the metal heightening layer and the avoidance groove, the increased quantity is the sum of the thicknesses of the semiconductor heightening layer and the metal heightening layer and the depth of the avoidance groove, the sum of the thicknesses of the semiconductor heightening layer and the metal heightening layer and the thickness of the medium layer can be increased to the maximum extent, the section difference is effectively increased, liquid crystal redundancy is increased, and the quality of the panel.
Drawings
FIG. 1 is a schematic cross-sectional view of a display panel according to an embodiment of the present invention;
fig. 2 is a schematic plan view illustrating a second substrate of a display panel according to an embodiment of the invention;
FIG. 3 is a schematic view of a half of the structure in section A of FIG. 2;
FIG. 4 is a schematic view of the other half of the structure in section A of FIG. 3;
FIG. 5 is a schematic cross-sectional view of a display panel according to an embodiment of the invention;
fig. 6 is a schematic cross-sectional view of a display panel according to a third embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly or indirectly secured to the other element. When an element is referred to as being "connected to" another element, it can be directly or indirectly connected to the other element. The terms "upper", "lower", "left", "right", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positions based on the orientations or positions shown in the drawings, and are for convenience of description only and not to be construed as limiting the technical solution. The terms "first", "second" and "first" are used merely for descriptive purposes and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features. The meaning of "plurality" is two or more unless specifically limited otherwise.
In order to explain the technical solution of the present invention, the following detailed description is made with reference to the specific drawings and examples.
Referring to fig. 1 and fig. 2, a display panel according to an embodiment of the present invention includes a first substrate 1 and a second substrate 2 disposed opposite to each other; the first substrate 1 and the second substrate 2 form a display panel after the pair sealing edge is formed, and it can be understood that, for the liquid crystal display panel, a liquid crystal material is poured between the first substrate 1 and the second substrate 2. The first substrate 1 mainly includes a first base layer 11, a main spacer 12 and a sub spacer 13 disposed on the first base layer 11, wherein the main spacer 12 and the sub spacer 13 are used for supporting a cell gap. Of course, the first substrate 1 further includes other functional structures to cooperate with the second substrate 2 to realize the display function. The second substrate 2 includes a second base layer 21 and a dielectric layer 22 disposed on one side of the second base layer 21 close to the first base layer 11, the second base layer 21 is used as a main supporting structure of the second substrate 2 for carrying other functional devices, circuits, etc., and the second base layer 21 and the first base layer 11 are disposed at an interval to form a space for accommodating liquid crystal material. The second substrate 2 further includes a semiconductor enhancement layer 231 and a metal enhancement layer 232, which are stacked inside the dielectric layer 22, wherein the semiconductor enhancement layer 231 and the metal enhancement layer 232 correspond to the main spacer 12, and specifically, may be opposite to each other in the vertical direction of the first base layer 11 and the second base layer 21. The second substrate 2 further includes an avoiding groove 24, which is opened in the dielectric layer 22, corresponds to the auxiliary spacer 13, and specifically, may be aligned along a vertical direction of the first base layer 11 and the second base layer 21, and the avoiding groove 24 may allow the auxiliary spacer 13 to extend into. Of course, the second substrate 2 further includes other functional structures disposed on the second base layer 21 to cooperate with the first substrate 1 to realize a display function. In a natural state, the main spacer 12 abuts against the portions corresponding to the semiconductor raising layer 231 and the metal raising layer 232, and in a low temperature state, the liquid crystal contracts, and the sub spacer 13 extends into the avoiding groove 24 and abuts against the bottom of the avoiding groove 24.
In this display panel, based on the arrangement of the raised portions and the avoidance grooves, the step L is D0+ D1+ D2+ H, where D0 is the height difference between the main spacer 12 and the sub spacer 13, and the height difference is the vertical distance between the free end of the main spacer 12 and the free end of the sub spacer 13. D1 is the thickness of the semiconductor raising layer 231, D2 is the thickness of the metal raising layer 232, and H is the depth of the relief groove 24. The avoiding groove 24 is formed in the medium layer 22, the depth H is larger than 0 and smaller than or equal to the thickness D3 of the medium layer 22, and therefore the section difference L is larger than D0+ D1+ D2 and smaller than or equal to D0+ D1+ D2+ D3. When the depth of the evasion groove 24 is equal to the thickness of the dielectric layer 22, the step difference is the largest, i.e., D0+ D1+ D2+ D3.
According to the display panel provided by the embodiment of the invention, the semiconductor heightening layer 231 and the metal heightening layer 232 are arranged on the second base layer 21 of the second substrate 2, the avoiding groove 24 is formed in the dielectric layer 22 of the second substrate 2, the main spacer 12 is opposite to the semiconductor heightening layer 231 and the metal heightening layer 232, the auxiliary spacer 13 is opposite to the avoiding groove 24 and can extend into the avoiding groove, due to the arrangement of the heightening part 23 and the avoiding groove 24, the step difference of the panel is increased, the increase amount is the sum of the thicknesses of the semiconductor heightening layer 231 and the metal heightening layer 232 and the depth of the avoiding groove 24, the sum of the thicknesses of the semiconductor heightening layer 231 and the metal heightening layer 232 and the thickness of the dielectric layer 22 can be increased to the maximum extent, the step difference is effectively increased, the liquid crystal redundancy is increased, and the quality.
Referring to fig. 1, in the present embodiment, the first substrate 1 may be, but is not limited to, a color filter substrate, and the second substrate 2 may be, but is not limited to, a thin film transistor array substrate. When the first substrate 1 is a color filter substrate, the first substrate 1 further includes a black matrix 14, and may further include a color resistance layer 15, where the black matrix 14 is disposed on a side of the first base layer 11 facing the second base layer 21, the color resistance layer 15 is disposed on a side of the first base layer 11 and a side of the black matrix 14 facing the second base layer 21, the color resistance layer 15 includes color resistance blocks of at least three different colors, such as red, green, and blue resistance blocks, or red, green, blue, and white resistance blocks, and the black matrix 14 is in a grid shape, and its horizontal and vertical lines intersect to define a plurality of sub-regions, each sub-region corresponds to one sub-pixel, and each color resistance block corresponds to one sub-region. Alternatively, the main spacer 12 and the sub spacer 13 may be disposed on the black matrix 14, or may be disposed on the color block in a region corresponding to the black matrix 14. Correspondingly, the second substrate 2 is a thin film transistor array substrate, and the second substrate 2 further includes a driving circuit disposed on the basis of the second base layer 21 and protected by the above-described dielectric layer 22.
The semiconductor elevating layer 231 metal elevating layer 232 can be optimized in process when the second substrate 2 is a thin film transistor array substrate. Referring to fig. 2 to 4, a driving circuit is disposed on the second base layer 21, the driving circuit includes a first metal layer 211, a semiconductor active layer 212, a second metal layer 213 and a pixel electrode 214, and the first metal layer 211, the first passivation layer 221, the semiconductor active layer 212, the second metal layer 213, the second passivation layer 222 and the pixel electrode 214 are formed in five processes of the tft array substrate. The first protective layer 221 and the second protective layer 222 constitute the dielectric layer 22. The first metal layer 211 is disposed between the second base layer 21 and the first protective layer 221, the semiconductor active layer 212 and the second metal layer 213 are disposed between the first protective layer 221 and the second protective layer 222, and the pixel electrode 214 is disposed on a side of the second protective layer 222 close to the first substrate 1. The first metal layer 211 generally includes a scan line 2111 and a gate 2112, the first protection layer 221 is used for protecting the first metal layer 211, and the semiconductor active layer 212 is disposed on the first protection layer 221 at a corresponding position corresponding to the gate 2112. The second metal layer 213 is formed on the semiconductor active layer 212 and the first protection layer 221, and includes a source electrode and a drain electrode overlapping the semiconductor active layer 212, and further includes a data line 2131 laid on the first protection layer 221, in a direction perpendicular to the first base layer 11, the data line 2131 crosses the scan line 2111, and the data line 2131 is connected to the source electrode or the drain electrode, for providing a display signal, that is, a voltage signal for implementing liquid crystal deflection. The second passivation layer 222 is formed on the second metal layer 213 for protecting the second metal layer 213 and carrying the pixel electrode 214, and the pixel electrode 214 is connected to the source or the drain of the second metal layer 213 through the conductive via.
The first protective layer 221 and the second protective layer 222 may be sequentially formed of the same or different insulating materials through a film forming process, and the insulating material may be selected from a transparent organic material or an inorganic material (e.g., SiNx) having good thermal conductivity. In addition, the thickness of the first protective layer 221 and the thickness of the second protective layer 222 may be the same or different, and this embodiment is not limited strictly.
Correspondingly, the raised portions 23 may be formed simultaneously in the five processes, referring to fig. 2 and 3, wherein, in the process of the semiconductor active layer 212, the semiconductor raised layer 231 is formed at the corresponding position on the first protection layer 221 at the same time; in the process of the second metal layer 213, a metal raising layer 232 is simultaneously formed on the semiconductor raising layer 231. After the semiconductor raising layer 231 and the metal raising layer 232 are formed, the second protective layer 222 naturally rises to form a convex portion corresponding to the positions of the semiconductor raising layer 231 and the metal raising layer 232. That is, the semiconductor raising layer 231 and the metal raising layer 232 push the corresponding portions of the second protection layer 222 against the main spacer 12.
In the five processes, in order to simplify the process, the thicknesses of the semiconductor raising layer 231 and the semiconductor active layer 212 may be the same; the metal boosting layer 232 and the second metal layer 213 have the same thickness. At the moment, the same material does not need to be etched in different degrees, which is beneficial to improving the efficiency.
In another embodiment, in order to further increase the step difference, the thickness of the semiconductor raising layer 231 may be made larger than that of the semiconductor active layer 212; the thickness of the metal raising layer 232 is greater than that of the second metal layer 213, so that the step difference can be increased as much as possible, the liquid crystal redundancy can be improved, and the quality of the display panel and the liquid crystal display can be improved.
In another embodiment, one of the semiconductor enhancement layer 231 and the metal enhancement layer 232 may also be made the same thickness as the corresponding layer structure. The method can be specifically set according to the operational difficulty of the actual process.
In one embodiment, the data line 2131, the source/drain and the metal enhancement layer 232 are formed in the process of forming the second metal layer 213, the metal enhancement layer 232 and the data line 2131 need to have an insulation space therebetween, the space therebetween is greater than 5 μm, and the space therebetween is greater than 5 μm in the process of forming the semiconductor active layer 212. So as to meet the requirement of insulation under the condition of controllable process machining error. Similarly, in the process of manufacturing the pixel electrode 214, the distance between the transparent conductive sheet layer 233 and the pixel electrode 214 is greater than 5 μm.
In one embodiment, each of the metal and semiconductor enhancement layers 232, 231 is a block structure, and may be a polygon, a circle, an ellipse, etc., with an area equal to or slightly larger than the cross-sectional area of the main spacer 12 or the free end area of the main spacer 12. The size of the metal enhancement layer 232 is larger than the size of the semiconductor enhancement layer 231, i.e. the projection of the metal enhancement layer 232 on the second base layer 21 overlaps the projection of the semiconductor enhancement layer 231 on the second base layer 21. Or the metal raising layer 232 and the semiconductor raising layer 231 have the same size, and the present embodiment is not limited thereto.
Referring to fig. 2 and 4, in five processes of the array substrate, the avoiding groove 24 is formed in the process of the second protection layer 222. In this process, a via hole is formed on the second passivation layer 222 to connect the pixel electrode 214 and the source or drain, and at the same time, a groove is formed on the portion of the second passivation layer 222 corresponding to the sub spacer 13 to form the avoiding groove 24. Optionally, the depth of the avoiding groove 24 may be the same as the via hole, or may be smaller than the depth of the via hole or larger than the depth of the via hole, and the area of the bottom of the avoiding groove 24 is larger than or equal to the area of the free end of the secondary spacer 13, so that the secondary spacer 13 can touch the bottom of the avoiding groove 24.
As a first structure of the avoiding groove 24, the avoiding groove 24 extends from the surface of the second passivation layer 222 close to the first substrate 1 to the inside of the second passivation layer 222, and the depth H is smaller than the thickness of the second passivation layer 222.
As a second structure of the avoiding groove 24, referring to fig. 5, the avoiding groove 24 extends from the surface of the second passivation layer 222 close to the first substrate 1 to the surface of the first passivation layer 221, and the depth H is equal to the thickness of the second passivation layer 222.
As a third structure of the avoiding groove 24, referring to fig. 6, the avoiding groove 24 extends from the surface of the second passivation layer 222 close to the first substrate 1 to the inside of the first passivation layer 221; the depth H is greater than the thickness of the second passivation layer 222 and less than the total thickness of the dielectric layer 22.
As a fourth structure of the avoiding groove 24, referring to fig. 1, the avoiding groove 24 extends from the surface of the second passivation layer 222 close to the first substrate 1 to the second base layer 21, and the depth H is equal to the total thickness of the dielectric layer 22.
In the above-described structure of the avoiding groove 24, the fourth structure may be selected so that the step is made larger.
In one embodiment, the height of the primary spacer 12 is equal to the height of the secondary spacer 13. Because the above-mentioned segment difference L is D0+ D1+ D2+ H, when the height of main spacer 12 is equal to the height of auxiliary spacer 13, D0 is zero, L is D1+ D2+ H, still have great segment difference, this complexity and the technology degree that can reduce the spacer process, can adopt mask that the luminousness is the same everywhere to make highly uniform main spacer 12 and auxiliary spacer 13, realize more easily on the technology, guarantee easily that main, auxiliary spacer 13 highly uniform, and avoid adopting the mask that the structure is complicated, avoid the poor problem of the difference in height uniformity of different height spacers.
In another embodiment, the height of the primary spacer 12 is greater than the height of the secondary spacer 13. When the height of the raised portion 23 is constant, the height of the sub spacer 13 is smaller than the height of the main spacer 12, so that the distance between the free end of the sub spacer 13 and the bottom of the escape groove 24 can be increased, and the step can be increased. The spacers with different heights can be formed at one time through a special mask, for example, structures with different ultraviolet transmittances are arranged on the mask corresponding to the positions of the main spacer 12 and the auxiliary spacer 13, so that the etching depths of the spacer material are different, and the spacers with different heights are formed. Specifically, a gray scale mask (GTM), a slit mask (SSM), or a semi-permeable film mask (HTM) may be used to form the main spacers 12 and the sub-spacers 13 of a predetermined height by reducing the local ultraviolet transmittance and etching away spacer materials of a predetermined thickness according to the predetermined heights of the main spacers 12 and the sub-spacers 13.
In this embodiment, it can be understood that, the larger the step difference is in a certain range, the better the step difference is, but it is not necessarily suitable for increasing without limitation, there is a certain critical value for the deformation amount of the second base layer 21 and the first base layer 11, that is, the variation space of the liquid crystal cell thickness has a certain limit, when the liquid crystal molecules shrink to a certain extent, the second base layer 21 and the first base layer 11 reach the maximum deformation amount, and cannot be compressed, and at this time, as the liquid crystal molecules shrink further, vacuum bubbles may occur. In this case, if the subsidiary spacer 13 still does not contact the bottom of the escape groove 24, it cannot function to support the thickness of the box, and the function of the subsidiary spacer 13 is lost. Generally, the step may range from 0.4 to 0.8 mm.
In the present embodiment, the black matrix 14 grid on the second base layer 21 defines a plurality of sub-pixel regions, and the main spacer 12 and the auxiliary spacer 13 may be disposed in different sub-pixel regions. For example, the main spacer 12 is disposed in the red photonic pixel region, and the sub-spacer 13 is disposed in the green photonic pixel region or the blue photonic pixel region; or, the main spacer 12 is disposed in the green photonic pixel region, and the sub spacer 13 is disposed in the red photonic pixel region or the blue photonic pixel region; alternatively, the main spacer 12 is disposed in the blue photon pixel region, and the sub spacer 13 is disposed in the red photon pixel region.
In this embodiment, the black matrix 14 is disposed at a position corresponding to the scan line 2111, the data line 2131, and the thin film transistor device, a gate 2112 and a source drain of the thin film transistor device are disposed near the scan line 2111, and the gate 2112 is connected to the scan line 2111.
Referring to fig. 2, on the second base layer 21, the semiconductor elevating layer 231 and the metal elevating layer 232 are located in the area covered by the black matrix 14 and on the same side of the gate 2112 as the scan line 2111, and their positions relative to the scan line 2111 are the same as or similar to the positions of the gate 2112 relative to the scan line 2111, and at the same time, they are kept at a certain relative distance from the data line 2131 to prevent conduction. The semiconductor raising layer 231 and the metal raising layer 232 are arranged at the position, so that the process is easy to realize, and the pixel aperture ratio is not influenced. Similarly, the avoiding groove 24 is located in the area covered by the black matrix 14 and on the same side of the scanning line 2111 as the gate 2112, and the position of the avoiding groove relative to the scanning line 2111 is the same as or similar to the position of the gate 2112 relative to the scanning line 2111. The raised portion 23 and the bypass groove 24 are provided in different sub-pixel regions.
In one embodiment, in order to achieve the deflection and regular orientation of the liquid crystal molecules, a first common electrode 16 and a first alignment film are further sequentially disposed on the color resistance layer 15 of the first substrate 1, a second alignment film is further disposed on the pixel electrode 214 of the second substrate 2, and the first common electrode 16 and the pixel electrode 214 form an inter-electrode capacitance. The first alignment film and the second alignment film are used to control the alignment of the liquid crystal molecules in a natural state.
In one embodiment, referring to fig. 2, the second substrate 2 further includes a second common electrode 2113 formed during the fabrication of the first metal layer 211 for forming a storage capacitor with the pixel electrode 214.
In one embodiment, the primary spacer 12 and the secondary spacer 13 may be selected to have a truncated cone-shaped structure, which has a larger diameter at one end connected to the first base layer 11 and a smaller diameter at the free end; the primary spacer 12 and the secondary spacer 13 may also be cylindrical with a uniform diameter. In other embodiments, the primary and secondary spacers 12, 13 may also be prismoid or prismatic, etc.
The display panel provided by the embodiment of the invention is mainly used for the liquid crystal display, and the liquid crystal display comprising the display panel is also within the protection scope of the invention. The LCD also comprises a backlight module for providing illumination, wherein the backlight module can be a side-in type backlight module or a direct type backlight module.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (10)
1. A display panel for increasing the step difference is characterized by comprising a first substrate and a second substrate which are oppositely arranged;
the first substrate includes:
a first base layer;
a main spacer disposed on the first base layer; and
a sub spacer disposed on the first base layer;
the second substrate includes:
the second base layer is arranged opposite to the first base layer at intervals;
the dielectric layer is arranged on one side, close to the first base layer, of the second base layer;
the semiconductor heightening layer and the metal heightening layer are overlapped in the medium layer and correspond to the main spacer; and
and the avoidance groove is formed in the dielectric layer, corresponds to the auxiliary spacer and can be used for the auxiliary spacer to extend into.
2. The display panel of claim 1, wherein the dielectric layer comprises a first protective layer and a second protective layer laminated on the second base layer;
the semiconductor heightening layer and the metal heightening layer are arranged between the first protective layer and the second protective layer, and the semiconductor heightening layer and the metal heightening layer push corresponding parts of the second protective layer to abut against the main spacer.
3. The display panel according to claim 2, wherein the second substrate further comprises a driving circuit, the driving circuit comprising a first metal layer, a semiconductor active layer, a second metal layer, and a pixel electrode, the first metal layer being disposed between the second base layer and a first protective layer, the semiconductor active layer and the second metal layer being disposed between the first protective layer and a second protective layer, the pixel electrode being disposed on a side of the second protective layer adjacent to the first substrate;
the semiconductor enhancement layer and the semiconductor active layer are formed on the first protective layer at intervals in the same process;
the metal heightening layer and the second metal layer are formed at intervals in the same process, wherein the metal heightening layer is formed on the semiconductor heightening layer, and the second metal layer is formed on the semiconductor active layer.
4. The display panel according to claim 3, wherein the semiconductor enhancing layer and the semiconductor active layer have the same thickness; and/or
The metal heightening layer and the second metal layer have the same thickness.
5. The display panel of claim 3, wherein a thickness of the semiconductor enhancement layer is greater than a thickness of the semiconductor active layer; and/or
The thickness of the metal enhancement layer is greater than the thickness of the second metal layer.
6. The display panel of claim 3, wherein the second metal layer comprises a data line, a source electrode and a drain electrode, and a spacing between the metal boosting layer and the data line is greater than 5 μm.
7. The display panel according to claim 6, wherein the first metal layer comprises a gate electrode and a scan line, the scan line and the data line intersect to form a plurality of sub-pixel regions arranged in an array, and in one of the sub-pixel regions, the semiconductor heightening layer and the metal heightening layer are disposed close to the scan line and at the same side of the scan line as the gate electrode; in another sub-pixel region, the avoiding groove is arranged close to the scanning line and is arranged on the same side of the scanning line with the grid electrode.
8. The display panel of claim 7, wherein the first substrate further includes a black matrix covering the data lines and the scan lines, the main spacer and the sub spacer are disposed on the black matrix, and the avoiding groove, the semiconductor elevating layer, and the metal elevating layer are covered by the black matrix.
9. The display panel of claim 2, wherein a bottom area of the escape groove is greater than or equal to an area of a free end of the subsidiary spacer;
the depth of the avoidance groove is smaller than the thickness of the second protective layer; or
The depth of the avoidance groove is equal to the thickness of the second protective layer; or
The depth of the avoiding groove is larger than the thickness of the second protective layer and smaller than the thickness of the dielectric layer; or
The depth of the avoiding groove is equal to the thickness of the dielectric layer.
10. A display device for increasing the step difference is characterized by comprising a first substrate and a second substrate which are oppositely arranged;
the first substrate includes:
a first base layer;
a main spacer disposed on the first base layer; and
a sub spacer disposed on the first base layer;
the second substrate includes:
the second base layer is arranged opposite to the first base layer at intervals;
the first protective layer is arranged on one side, close to the first base layer, of the second base layer;
the second protective layer is arranged on one side, close to the first base layer, of the first protective layer;
the driving circuit comprises a first metal layer, a semiconductor active layer, a second metal layer and a pixel electrode, wherein the first metal layer is arranged between the second base layer and the first protective layer, the semiconductor active layer and the second metal layer are arranged between the first protective layer and the second protective layer, and the pixel electrode is arranged on the second protective layer;
the display device further includes:
the semiconductor enhancement layer is arranged between the first protective layer and the second protective layer and is formed by the same process with the semiconductor active layer;
the metal enhancement layer is arranged between the semiconductor enhancement layer and the second protective layer and is formed by the same process with the second metal layer;
the semiconductor and metal enhancement layers correspond to the main spacer; and
and the avoidance groove is formed from the surface of the second protective layer to the direction of the second base layer, corresponds to the auxiliary spacer and can be used for the auxiliary spacer to extend into.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
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| CN201811338881.2A CN111176023A (en) | 2018-11-12 | 2018-11-12 | Display panel and display device with increased segment difference |
| PCT/CN2018/121211 WO2020098042A1 (en) | 2018-11-12 | 2018-12-14 | Display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811338881.2A CN111176023A (en) | 2018-11-12 | 2018-11-12 | Display panel and display device with increased segment difference |
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| CN111176023A true CN111176023A (en) | 2020-05-19 |
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