CN111180384B

CN111180384B - Interconnect structure and method of forming the same

Info

Publication number: CN111180384B
Application number: CN201911093292.7A
Authority: CN
Inventors: 王菘豊; 梁顺鑫; 张容浩; 朱家宏; 林耕竹
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2018-11-09
Filing date: 2019-11-11
Publication date: 2024-02-23
Anticipated expiration: 2039-11-11
Also published as: TW202018808A; TWI801631B; CN111180384A

Abstract

Embodiments described herein relate generally to one or more methods for forming interconnect structures, such as dual damascene interconnect structures including conductive lines and conductive vias, and structures formed thereby. In some embodiments, the interconnect openings are formed through one or more dielectric layers over the semiconductor substrate. The interconnect opening has a via opening and a trench located above the via opening. Conductive vias are formed in the via openings. A nucleation enhancement treatment is performed on one or more exposed dielectric surfaces of the trench. Conductive lines are formed in the trenches on one or more exposed dielectric surfaces of the trenches and on the conductive vias. Embodiments of the present invention also relate to interconnect structures.

Description

Interconnect structure and method of forming the same

Technical Field

Embodiments of the present invention relate to interconnect structures and methods of forming the same.

Background

The semiconductor Integrated Circuit (IC) industry has experienced an exponential growth. Technological advances in IC materials and design have resulted in multi-generation ICs, where each generation has smaller and more complex circuitry than the previous generation. In IC evolution processes, functional density (e.g., the number of interconnected devices per chip area) has generally increased, while geometry (e.g., the smallest component or line that can be created using a fabrication process) has decreased. Such a downscaling process generally provides benefits by improving production efficiency and reducing associated costs. However, scaling down also results in challenges that previous generations may not present with larger geometries.

Disclosure of Invention

Embodiments of the present invention provide a method for forming an interconnect structure, comprising: etching an interconnect opening through one or more dielectric layers over a semiconductor substrate, the interconnect opening having a via opening and a trench over the via opening, the via opening exposing a conductive feature over the semiconductor substrate, the conductive feature comprising a first layer of a first conductive material; treating the via opening with plasma to physically remove etching residues from sidewalls and bottom of the via opening; soaking the conductive member with a halide of the first conductive material, the residual halide of the first conductive material remaining in the via opening after soaking; reducing the residual halide of the first conductive material to form a second layer of the first conductive material on the first layer; depositing a conductive via in a via opening on a second layer of the first conductive material; and forming a conductive line on one or more exposed dielectric surfaces of the trench and in the trench over the conductive via.

Another embodiment of the present invention provides a method for forming an interconnect structure, comprising: etching an interconnect opening through one or more dielectric layers over a semiconductor substrate, the interconnect opening having a via opening and a trench over the via opening, the via opening exposing a conductive feature over the semiconductor substrate, the conductive feature comprising a conductive material; cleaning the through hole opening; depositing a conductive via in the cleaned via; performing a nucleation enhancement treatment on one or more exposed dielectric surfaces of the trench; and forming a conductive line on one or more exposed dielectric surfaces of the trench and in the trench over the conductive via.

Yet another embodiment of the present invention provides a method for forming an interconnect structure, comprising: depositing a conductive feature over a substrate, the depositing comprising providing a plurality of precursors for a first conductive material; depositing one or more dielectric layers over the conductive features; etching an interconnect opening through the one or more dielectric layers, the interconnect opening having a via portion and a line portion located above the via portion; cleaning the sidewalls and bottom surfaces of the interconnect opening with a halide of the first conductive material, which is a precursor for the first conductive material; depositing a conductive via in the via portion of the cleaned interconnect opening, the conductive via contacting the conductive feature; and depositing a conductive line in the line portion of the cleaned interconnect opening.

Yet another embodiment of the present invention provides an interconnect structure comprising: a semiconductor substrate; one or more dielectric layers over the semiconductor substrate; and an interconnect structure disposed in the one or more dielectric layers, the interconnect structure comprising: a conductive via; and a wire over the conductive via, the wire being disposed over horizontal surfaces of the one or more dielectric layers, the same substance being disposed at the horizontal surfaces of the one or more dielectric layers and at an upper surface of the conductive via at an interface between the conductive via and a conductive filler of the wire.

Yet another embodiment of the present invention provides an interconnect structure comprising: a semiconductor substrate; a first dielectric layer over the semiconductor substrate; a conductive via extending through the first dielectric layer, the conductive via comprising a first conductive material; a second dielectric layer over the first dielectric layer; and a wire extending through the second dielectric layer, the wire including a second conductive material, the wire sharing a first interface with the conductive via, the wire sharing a second interface with a horizontal surface of the first dielectric layer, the wire sharing a third interface with a vertical surface of the second dielectric layer, the same substance being disposed at the first, second, and third interfaces, the first and second interfaces having more substance than the third interface, the substance being different from the first and second conductive materials.

Yet another embodiment of the present invention provides an interconnect structure comprising: a semiconductor substrate; a first conductive member located over the semiconductor substrate; one or more dielectric layers over the first conductive feature; a first interconnect structure disposed in the one or more dielectric layers, the first interconnect structure including a conductive via and a wire, the conductive via and the wire contacting a horizontal surface of the one or more dielectric layers and a vertical surface of the one or more dielectric layers, the same substance being disposed at the horizontal surface of the one or more dielectric layers and the vertical surface of the one or more dielectric layers; and a second conductive feature over the first interconnect structure, wherein the conductive via includes a first conductive material that extends continuously between the first conductive feature and the wire, and wherein the wire includes a second conductive material that extends continuously between the conductive via and the second conductive feature.

Drawings

The various aspects of the invention are best understood from the following detailed description when read in connection with the accompanying drawings. It should be noted that the various components are not drawn to scale according to standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1-10 are cross-sectional views of respective intermediate structures during an exemplary method for forming an interconnect structure, according to some embodiments.

Fig. 11 is a flowchart of an exemplary method for forming an interconnect structure, according to some embodiments.

Fig. 12 is a flow chart of an exemplary Atomic Layer Etching (ALE) process, according to some embodiments.

Fig. 13-18 are cross-sectional views of various details and/or modifications to portions of the intermediate structure of fig. 6, according to some embodiments.

Fig. 19-20 are cross-sectional views of respective intermediate structures during an exemplary method for forming an interconnect structure, in accordance with some other embodiments.

FIG. 21 is a flow chart of an exemplary cleaning process according to some embodiments.

Fig. 22 is a cross-sectional view of a resulting interconnect structure, in accordance with some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Furthermore, the present invention may repeat reference numerals and/or characters in various embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Moreover, spatially relative terms such as "under …," "under …," "lower," "above …," "upper," and the like may be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Embodiments described herein relate generally to one or more methods for forming interconnect structures, such as dual damascene interconnect structures including conductive lines and conductive vias, in semiconductor processes. In general, a conductive via may be selectively deposited in a via opening for an interconnect structure, followed by a nucleation enhancement process, and then a conductive fill material may be deposited in a trench for the interconnect structure. The nucleation enhancement process may cause the deposition of the conductive fill material to be bottom-up and/or conformal, such as by nucleation and deposition on the dielectric surface. Some embodiments may avoid the use of a seed layer to deposit the conductive fill material and may further avoid the use of a high resistance metal-containing barrier layer in the interconnect structure. Thus, some process windows for forming the interconnect structure may be increased, and the resistance of the interconnect structure may be reduced. In some embodiments, a cleaning process is performed prior to the nucleation enhancement process to clean the exposed surfaces of the via openings for the interconnect structures. The cleaning process may include a number of processes, such as physical and chemical removal processes. Some embodiments may also help remove native oxide that may form in the via openings and may reduce the chance of void formation during deposition of the conductive vias. Therefore, the resistance of the interconnect structure can be further reduced. Other advantages or benefits may also be realized.

Some embodiments described herein are in the context of back end of line (BEOL) processes. Other processes and structures within the scope of other embodiments may be implemented in other contexts, such as in a middle of line (MEOL) process and other contexts. Various modifications are discussed with reference to the disclosed embodiments; however, other modifications may be made to the disclosed embodiments while remaining within the scope of the subject matter. Those of ordinary skill in the art will readily appreciate other modifications that may be contemplated within the scope of other embodiments. Although method embodiments may be described in a particular order, various other method embodiments may be implemented in any logical order, and may include fewer or more steps than those described herein.

Fig. 1-10 illustrate cross-sectional views of respective intermediate structures during an exemplary method for forming an interconnect structure, in accordance with some embodiments. Fig. 11 is a flowchart of an exemplary method 200 for forming an interconnect structure, according to some embodiments.

Operation 202 of fig. 1 and method 200 illustrates forming a dielectric layer over semiconductor substrate 20. Fig. 1 shows a first dielectric layer 22 over a semiconductor substrate 20. The semiconductor substrate 20 may be or include a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or n-type dopant) or undoped. In some embodiments, the semiconductor material of semiconductor substrate 20 may include elemental semiconductors such as silicon (Si) and germanium (Ge); a compound semiconductor; an alloy semiconductor; or a combination thereof.

A variety of devices may be located on semiconductor substrate 20. For example, the semiconductor substrate 20 may include a Field Effect Transistor (FET), such as Fin FET (FinFET), planar FET, vertical gate all around FET (VGAA FET), or the like; a diode; a capacitor; an inductor; and other devices. For example, the device may be formed entirely within semiconductor substrate 20, entirely within portions of semiconductor substrate 20 and portions of one or more overlying layers, and/or entirely within one or more overlying layers. The processes described herein may be used to form and/or interconnect devices to form integrated circuits. The integrated circuit may be any circuit, such as for an Application Specific Integrated Circuit (ASIC), a processor, a memory, or other circuit.

A first dielectric layer 22 is located over the semiconductor substrate 20. The first dielectric layer 22 may be located directly on the semiconductor substrate 20, or any number of other layers may be disposed between the first dielectric layer 22 and the semiconductor substrate 20. For example, the first dielectric layer 22 may be or include an inter-metal dielectric (IMD) or an inter-layer dielectric (ILD). The first dielectric layer 22 may be or include, for example, a low-k dielectric having a k value of less than about 4.0, such as about 2.0 or even lower. In some examples, the first dielectric layer 22 includes silicon oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), siO _x C _y A silicon carbon material, a compound thereof, a composite thereof, or a combination thereof.

Conductive features 24 are located in the first dielectric layer 22 and/or through the first dielectric layer 22. The conductive feature 24 may be or include a conductive line and/or conductive via, a gate structure of a transistor, or a contact plug to a gate structure of a transistor and/or a source/drain region of a transistor. In some examples, the first dielectric layer 22 is an IMD, and the conductive features 24 may include conductive lines and/or conductive vias (collectively or individually referred to as "interconnect structures"). The interconnect structure may be formed by, for example, using a damascene process through the IMD and/or forming openings and/or recesses in the IMD. Some examples of forming the interconnect structure are described further below, but other processes and interconnect structures may be implemented. In other examples, the first dielectric layer 22 may include an ILD, and the conductive feature 24 may include a gate electrode (e.g., tungsten, cobalt, etc.) in the ILD formed, for example, using a replacement gate process. In another example, the first dielectric layer 22 may be an ILD and the conductive feature 24 may include a contact plug. The contact plugs may be formed by forming openings through the ILD to, for example, gate electrodes and/or source/drain regions of transistors formed on the semiconductor substrate 20. The contact plug may include an adhesion layer (e.g., ti, etc.), a barrier layer (e.g., tiN, etc.) on the adhesion layer, and a conductive filler material (e.g., tungsten, cobalt, etc.) on the barrier layer. The contact plug may also be made of less diffuse metal, such as tungsten, mo or Ru, without a barrier layer.

A first Etch Stop Layer (ESL) 26 is located over the first dielectric layer 22 and the conductive feature 24. Generally, ESL may provide a mechanism to stop the etching process when forming, for example, contacts or conductive vias. The ESL may be formed of a dielectric material having a different etch selectivity than an adjacent layer or component. A first ESL 26 is deposited on top of the first dielectric layer 22 and the conductive features 24. The first ESL 26 may comprise or be silicon nitride, silicon carbonitride, silicon oxycarbide, carbon nitride, the like, or combinations thereof, and may be deposited by Chemical Vapor Deposition (CVD), plasma Enhanced CVD (PECVD), atomic Layer Deposition (ALD), or other deposition techniques. In some examples, the thickness of the first ESL 26 is in the range of about 3nm to about 10 nm.

A second dielectric layer 28 is located over the first ESL 26. For example, the second dielectric layer 28 may be or include an IMD. A second dielectric layer 28 is deposited on top of the first ESL 26. The second dielectric layer 28 may be or include, for example, a k value less than about 4.0 (such as about 2.0 or evenTo smaller) low-k dielectrics. In some examples, the second dielectric layer 28 includes silicon oxide, PSG, BPSG, FSG, siO _x C _y Silicon carbon materials, their compounds, their composites, or combinations thereof. The second dielectric layer 28 may be deposited using CVD, such as PECVD or Flowable CVD (FCVD); spin coating; or other deposition techniques. In some examples, a Chemical Mechanical Planarization (CMP) or other planarization process may be performed to planarize the top surface of the second dielectric layer 28. In some examples, the thickness of the second dielectric layer 28 is in the range from about 4nm to about 30 nm.

A second ESL 30 is located over the second dielectric layer 28. A second ESL 30 is deposited on the top surface of the second dielectric layer 28. The second ESL 30 may comprise or be silicon nitride, silicon carbonitride, silicon oxycarbide, carbon nitride, the like, or combinations thereof, and may be deposited by CVD, PECVD, ALD or other deposition techniques. In some examples, the thickness of the second ESL 30 is in the range from about 3nm to about 10 nm.

A third dielectric layer 32 is located over the second ESL 30. For example, the third dielectric layer 32 may be or include an IMD. A third dielectric layer 32 is deposited on top of the second ESL 30. The third dielectric layer 32 may be or include, for example, a low-k dielectric having a k value of less than about 4.0 (such as about 2.0 or even less). In some examples, the third dielectric layer 32 includes silicon oxide, PSG, BPSG, FSG, siO _x Cy, silicon carbon materials, their compounds, their composites, or combinations thereof. The third dielectric layer 32 may be deposited using CVD, such as PECVD or FCVD; spin coating; or other deposition techniques. In some examples, a CMP or other planarization process may be performed to planarize the top surface of third dielectric layer 32. In some examples, the thickness of the third dielectric layer 32 is in a range from about 20nm to about 50nm, such as about 45nm.

The configuration of the second dielectric layer 28, the second ESL30, and the third dielectric layer 32 of fig. 1 is an example. In other examples, the second ESL30 may be omitted between the second dielectric layer 28 and the third dielectric layer 32. Further, in some examples, a single dielectric layer may be formed in place of the second dielectric layer 28, the second ESL30, and the third dielectric layer 32. These and other modifications will be readily apparent to those of ordinary skill in the art.

Operation 204 of fig. 2 and method 200 illustrates forming via openings 42 and trenches 40 in and/or through first ESL 26, second dielectric layer 28, second ESL30, and third dielectric layer 32. The via openings 42 and trenches 40 may be formed using photolithography and etching processes, such as in a dual damascene process. For example, a photoresist may be formed on the third dielectric layer 32, such as by using spin coating, and patterned to have a pattern corresponding to the trenches 40 by exposing the photoresist to light using an appropriate photomask. The exposed or unexposed portions of the photoresist may then be removed depending on whether a positive or negative photoresist is used. The pattern of photoresist may then be transferred to the third dielectric layer 32, such as by using a suitable etching process, which forms the trenches 40 in the third dielectric layer 32. The etching process may include Reactive Ion Etching (RIE), neutral Beam Etching (NBE), inductively Coupled Plasma (ICP) etching, or the like, or a combination thereof. The etching process may be anisotropic. The second ESL30 may be used as an etch stop layer for an etching process. The photoresist is then removed, for example, in an ashing or wet strip process. Thereafter, another photoresist may be formed in the third dielectric layer 32 and the trench 40, such as by using spin coating, and the other photoresist is patterned to have a pattern corresponding to the via opening 42 by exposing the photoresist to light using an appropriate photomask. The pattern of photoresist may then be transferred through the second ESL30, the second dielectric layer 28, and the first ESL 26, such as by using one or more suitable etching processes, which form via openings 42 through the second ESL30, the second dielectric layer 28, and the first ESL 26. The etching process may include RIE, NBE, ICP etching, or the like, or a combination thereof. The etching process may be anisotropic. The photoresist is then removed, for example, in an ashing or wet strip process.

The sidewalls of trench 40 and via opening 42 are shown as being substantially vertical and having rounded corners. For example, the linear portion of the sidewall forms an angle measured inside the respective second dielectric layer 28 or third dielectric layer 32 that ranges from about 85 to about 90, such as about 85 to about 89, and more specifically about 87. In other examples, the sidewalls of one or both of the trench 40 and the via opening 42 may be vertical, or may taper together in a direction toward or away from the bottom of the via opening 42. For example, the via opening 42 may have a positively tapered profile or a concave profile. Various examples of configurations for the via openings 42 and details thereof are shown and described in fig. 13-18.

In the exemplary configuration of fig. 2, trench 40 has a first width W1 in the plane of the top surface of third dielectric layer 32 and a second width W2 along the bottom surface of trench 40. In some examples, the first width W1 is in a range from about 20nm to about 40nm, and in some examples, the second width W2 is in a range from about 18nm to about 36 nm. In this example, the depth of the trench is equal to the first thickness T1 of the third dielectric layer 32. As previously described, in some examples, the first thickness T1 is in a range from about 20nm to about 50 nm. The first aspect ratio of the first thickness T1 to the first width W1 may be in a range from about 0.5 to about 2.5, and the second aspect ratio of the first thickness T1 to the second width W2 may be in a range from about 0.56 to about 2.78.

In an exemplary configuration in which the sidewalls of the trench are vertical, the widths corresponding to the first width W1 and the second width W2 in fig. 2 are equal, and each width may range from about 20nm to about 40 nm. In this example, the aspect ratio of the first thickness T1 to the width of the trench 40 may be in a range from about 0.5 to about 2.5. In an exemplary configuration (e.g., a positively tapered profile) where the sidewalls of the trench taper, the width corresponding to the first width W1 in fig. 2 may be a width (W _lower ) And the angle (θ) of the sidewall measured inside the third dielectric layer 32 (e.g., W _upper ＝W _lower +[2T ₁ (tanθ) ^-1 ]). Corresponding to the second width W in FIG. 2 ₂ The width of (c) may range from about 18nm to about 36nm, and the angle may range from about 85 to about 89, or may be less than 85. Aspect ratio of the first thickness T1 to a width corresponding to the second width W2 of FIG. 2May range from about 0.56 to about 2.78.

Those of ordinary skill in the art will readily appreciate that the dimensions, ratios, and angles described herein are merely examples. The dimensions, ratios, and angles may vary based on the technology generation node in which the various aspects are implemented and/or based on the various processes used. Such variations are within the scope of the invention.

Operation 206 of fig. 3 and method 200 illustrates conformally forming liner layer 50 along sidewalls of via opening 42 and trench 40, along respective bottom surfaces of via opening 42 and trench 40, and along a top surface of dielectric layer 32. The liner layer 50 may be formed by conformal deposition. Liner layer 50 may be or include silicon nitride (SiN), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon-containing low-k dielectrics, carbon-containing low-k dielectrics, and the like, or combinations thereof, and may be deposited by CVD, ALD, or other deposition techniques. In some examples, the thickness of the spacer layer 50 is in the range from about 1nm to about 4nm, and more particularly, in the range from about 2nm to about 3 nm.

Operation 208 of fig. 4 and method 200 illustrates forming a respective liner 52 from liner layer 50 along the sidewalls of via opening 42 and along the sidewalls of trench 40. The spacer 52 may be formed by anisotropically etching the spacer layer 50. The etching process for anisotropically etching the liner layer 50 may include RIE, NBE, ICP etching or the like, or a combination thereof. The liner 52 and the second ESL 30 (if implemented) may be diffusion barriers that may reduce or prevent out-diffusion of conductive fill material subsequently deposited in the trench 40 and the via opening 42 to, for example, the second dielectric layer 28 and the third dielectric layer 32. The liner 52 and the second ESL 30 may form a dielectric diffusion barrier.

The profile of the liner 52 may vary depending on the profile of the sidewalls of the trench 40 and via opening 42, etc. In the example of FIG. 4, the second thickness T is at a rounded corner at the sidewall where the slope of the corner is about 45 degrees ₂ May be substantially equal to the thickness T of the liner layer 50 minus the thickness (T _Etching ) Multiplied by the square root of 2 divided by 2 (e.g., T- [ T ] _Etching x 2 ^-(1/2) ]). Further, the third thickness T3 along the substantially vertical portion of the respective sidewall at the bottom of the trench 40 or via opening 42 may be equal to the thickness T of the liner layer 50. In some examples, the second thickness T2 is in a range from about 0.3nm to about 1.2nm, and the third thickness T3 is in a range from about 1nm to about 4 nm. Those of ordinary skill in the art will readily appreciate the relationship between the thickness of the liner 52 and the angle of inclination of the underlying sidewall.

In an exemplary configuration in which the sidewalls of the trenches are vertical, a second thickness T in FIG. 4 corresponds to ₂ And a third thickness T ₃ Which may further be substantially equal to the thickness T of the spacer layer 50, each may be in the range from about 1nm to about 4 nm. In an exemplary configuration in which the sidewalls of the trench taper at a constant oblique angle (e.g., a positively tapered profile), corresponds to a second thickness T in fig. 4 ₂ And a third thickness T ₃ Is equal in thickness. As will be appreciated by those of ordinary skill in the art, this thickness may be a function of the thickness T of the liner layer 50 and the angle of the sidewalls, similar to that described above. The width corresponding to the second width W2 in fig. 2 may be in a range from about 1nm to about 4 nm.

The profile of the liner 52 may further vary depending on the step coverage of the deposition process used to deposit the liner layer 50. For example, the thickness of the sidewall of the liner 52 along the via opening 42 may be different from the thickness of the sidewall of the liner 52 along the trench 40 due to the step coverage variation.

In operation 210 of method 200, after forming liner 52, optionally, a cleaning process may be performed to clean exposed surfaces, such as trench 40 and via opening 42. The cleaning process may include a plasma treatment, an etching process, another cleaning process, or a combination thereof. In an example, the cleaning process includes a plasma treatment (operation 212), followed by an Atomic Layer Etch (ALE) (operation 214). The plasma treatment in operation 212 may include using hydrogen (H ₂ ) With a carrier gas such as argon (Ar). In some cases, the plasma treatment may reduce oxides that may form on the surface of the conductive member 24 exposed through the via opening 42, and may remove oxides that may form on the respective conductive members Organic material on the respective surfaces. The flow rate of hydrogen in the plasma treatment may be in the range of about 5sccm to about 1,000sccm, and the flow rate of carrier gas in the plasma treatment may be in the range of about 0sccm to about 1,000 sccm. The pressure of the plasma treatment may be in the range of about 10mTorr to about 200 mTorr. The temperature of the plasma treatment may be in the range of about-20 ℃ to about 100 ℃. The power of the plasma generator of the plasma treatment may be in the range of about 20W to about 400W, and the frequency of the plasma generator may be about 13.56MHz or more. The substrate during plasma processing may be biased in the range of about 20V to about 100V. The duration of the plasma treatment may be in the range of about 5 seconds to about 120 seconds.

ALE in operation 214 is illustrated in further detail in FIG. 12. The ALE in operation 214 may include implementing a plurality of cycles, such as in the range of 2 cycles to 25 cycles. The recycling of ALE may include sequentially reacting gases (operation 250), such as boron trichloride (BCl) ₃ ) The gas is flowed with a carrier gas (e.g., argon (Ar)), the reactant gas is purged (operation 252), and the etchant gas (operation 254) (such as hydrogen (H) ₂ ) Flowing with a carrier gas, such as argon (Ar), and possibly plasma enhanced; and purging (operation 256) the etchant gas. In some examples, the reactant gas (e.g., boron trichloride (BCl) ₃ ) Gas is adsorbed on the dielectric surface to form a monolayer and does not significantly adsorb on the metal surface, and the monolayer is formed by, for example, hydrogen (H) ₂ ) Is etched by the flow of the etchant gas. Examples provided herein are boron trichloride (BCl) as a reactant gas ₃ ) Gas and hydrogen gas (H) as etchant gas ₂ ) A gas; other gases may be used. In boron trichloride (BCl) ₃ ) During the flow of the gas, boron trichloride (BCl) ₃ ) The flow rate of the gas may be in the range of about 20sccm to about 180sccm, and the flow rate of the carrier gas may be in the range of about 200sccm to about 800 sccm. In addition, in boron trichloride (BCl) ₃ ) During the flow of the gas, the pressure of the ALE may be in the range of about 15mTorr to about 100mTorr, and the temperature of the ALE may be in the range of about-20℃to about 60 ℃. After purging the boron trichloride, hydrogen (H ₂ ) The flow starts and the plasma ignites. In hydrogen (H) ₂ ) During the flow, hydrogen (H ₂ ) May be in the range of about 5sccm to about 1,000sccm, and the carrier gas may be in the range of about 50sccm to about 400 sccm. In addition, in the presence of hydrogen (H ₂ ) During flow, the pressure of the ALE may be in the range of about 10mTorr to about 200mTorr, and the temperature of the ALE may be in the range of about-20℃to about 20 ℃. The power of the plasma generator of the ALE may be in the range of about 10W to about 800W, and the frequency of the plasma generator may be about 13.56MHz or greater. The substrate during the plasma of ALE may be biased in the range of about 50V to about 300V.

The above process is one example of a cleaning process (operation 210). In some embodiments (described further below with reference to fig. 19-22), the cleaning process includes a plasma treatment, followed by a halide soak, followed by a reduction treatment.

In operation 216 of method 200, after optionally performing the cleaning process in operation 210, a selective enhancement treatment may optionally be performed on the exposed dielectric surfaces, such as trenches 40 and via openings 42. The selectivity enhancing treatment may, for example, treat and/or passivate the dielectric surface such that subsequent metal deposition has a higher selectivity than without such treatment, such that the metal is deposited on the metal surface at a greater rate than on the dielectric surface. For example, the selectivity enhancing treatment may render the dielectric surface hydrophobic, which may improve selectivity during subsequent metal deposition. The selective enhancement process can include flowing a silicon-containing hydrocarbon gas over the dielectric surface. The selectivity enhancing treatment may be a Trimethylsiloxy (TMS) treatment, a Dimethylsiloxy (DMS) treatment, or the like, or a combination thereof. Examples of silicon-containing hydrocarbon gases include 1, 3-Hexamethyldisilazane (HDMS), chlorotrimethylsilane (TMCS), N, O-bis (trimethylsilyl) acetamide (BSA), N- (trimethylsilyl) dimethylamine (TMS-DMA), TMS-imidazole (SIM, N-trimethylsilylimidazole), 1, 3-Tetramethyldisilazane (TMDS), chlorodimethylsilane (DMCS), and the like, or combinations thereof. The selective enhancement treatment may cause a silylation process in which atoms or groups of atoms terminating at the dielectric surface may be replaced with a silicon-containing hydrocarbon species, which may render the dielectric surface hydrophobic. The flow rate of the silicon-containing hydrocarbon may be in the range of about 5sccm to about 100sccm, and the flow rate of the carrier gas flowing with the silicon-containing hydrocarbon may be in the range of about 0sccm to about 400 sccm. The pressure during the flow of the siliceous hydrocarbon can be in the range of from about 1mTorr to about 100mTorr and the temperature can be in the range of from about 20 ℃ to about 300 ℃. The selectivity enhancing process may treat or passivate the exposed dielectric surfaces of the liner 52, the second ESL 30, and the third dielectric layer 32 to enhance the selectivity of subsequent selective deposition on the conductive feature 24.

Operation 218 of fig. 5 and method 200 illustrates forming a conductive via 60 in via opening 42. The formation of the conductive vias 60 may include selective deposition. For example, selective deposition may use conductive feature 24 exposed through via opening 42 as a seed. Selective deposition may include electroless deposition or plating, selective CVD, or other techniques. The conductive via 60 may be or include a metal such as cobalt (Co), ruthenium (Ru), or the like, or a combination thereof. In an example, the conductive via 60 is cobalt deposited using electroless plating or plating. Electroless deposition or plating of cobalt (Co) may be in a temperature range equal to or less than about 200 ℃, such as in a range of room temperature (e.g., about 23 ℃) to about 200 ℃. Selective CVD can include the use of a material comprising Ru ₃ (CO) ₁₂ 、C ₁₀ H ₁₀ Ru、C ₇ H ₉ RuC ₇ H ₉ 、Ru( _C5 (CH ₃ ) ₅ ) ₂ Etc., or combinations thereof, and a carrier gas, such as argon (Ar). The flow rate of the precursor gas may be in the range of about 5sccm to about 100sccm and the flow rate of the carrier gas may be in the range of about 10sccm to about 400 sccm. The pressure of the selective CVD may be in the range of about 0.2mTorr to about 20 mTorr. The temperature of the selective CVD may be less than or equal to about 200 ℃, such as in the range of room temperature (e.g., about 23 ℃) to about 200 ℃.

As shown in fig. 5, the upper surface of the conductive via 60 is convex. In other examples, the upper surface of the conductive via 60 may be concave or flat. Various examples of the configuration of the conductive vias 60 formed in the via openings 42 and their details are shown and described in fig. 13-18.

As shown in fig. 5, some residual deposition sites 62 may be formed during the selective deposition for forming the conductive vias 60. Residual deposition sites 62 may be formed on various surfaces, such as the surfaces of the second ESL 30 and liner 52 in trench 40.

Operation 220 of fig. 6 and method 200 illustrates the implementation of a selective etch back to remove the residual deposition sites 62. The etch back may be a dry (e.g., plasma) etch process, a wet etch process, or a combination thereof. The plasma etching process may include the use of carbon fluoride (C _x F _y ) Gas, chlorofluorocarbon (C) _x Cl _y F _z ) Gas, carbon chloride (C) _x Cl _y ) Gases, and the like, or combinations thereof. The wet etch process may include the use of one or more of standard cleaning-1 (SC 1), standard cleaning-2 (SC 2), sulfuric acid-hydrogen peroxide mixture (SPM), dilute hydrofluoric acid (dHF) acid, hydrogen peroxide (H) ₂ O ₂ ) Buffer Oxide Etch (BOE) solution, hydrochloric acid (HCl), etc., or a combination thereof. The temperature of the solution may be in the range of about 20 ℃ to about 90 ℃ and the duration of the soaking of the substrate in the solution may be in the range of about 10 seconds to about 120 seconds.

Operation 222 of fig. 7 and method 200 illustrates the implementation of a nucleation enhancement process along exposed surfaces in trench 40, for example, including upper surfaces of conductive vias 60, to form treated surface 70. Typically, the nucleation enhancement process breaks bonds along exposed surfaces, such as in trenches 40, to enhance the ability to adsorb material during subsequent deposition processes. In some examples, the nucleation enhancement process includes sputtering (operation 224), implantation (operation 226), plasma processing (operation 228), ultraviolet (UV) processing (operation 230), plasma doping (operation 232), and the like, or a combination thereof. The nucleation enhancement process may be directional (e.g., anisotropic) or conformal (e.g., isotropic). In some examples, the nucleation enhancement treatment may treat, for example, vertical surfaces, although to a lesser extent than, for example, horizontal surfaces. The extent to which the nucleation enhancement process is performed (e.g., the extent to which bonds are broken along the surface) can affect the plurality of nucleation sites and thus at least the initial deposition rate for the later deposited conductive filler material 80, as will be described later. In general, the more bonds that are broken and the more dangling bonds that are created, nucleation sites can be used for adsorption and nucleation of the conductive filler material 80 to increase the deposition rate, at least the initial rate of deposition. In some examples, the nucleation enhancement process may be directional to treat substantially only horizontal surfaces (e.g., the top surface of the second ESL 30 and the upper surface of the conductive via 60 exposed by the trench 40), which enables bottom-up deposition of the conductive fill material in the trench 40 and reduces the formation of cracks and voids in the conductive fill material in the trench 40.

In an example, the nucleation enhancement process is sputtering using argon (Ar) gas (operation 224). The flow rate of argon may be in the range of about 10sccm to about 2,000 sccm. The pressure of sputtering may be in the range of about 0.5mTorr to about 50mTorr, and the temperature of sputtering may be in the range of about-20℃to about 120 ℃. The power of the sputtered plasma generator may be in the range of about 100W to about 2,000W, and the frequency of the plasma generator may be about 13.56MHz or higher. The substrate may be biased during sputtering in the range of about 50V to about 300V. Sputtering may be directional (e.g., treating a horizontal surface), but in some examples, sputtering may be conformal. Sputtering may deposit argon on the treatment surface 70 and/or embed into the corresponding material to a depth below the treatment surface 70. For example, a species (e.g., argon) for sputtering may be embedded into the material forming the processing surface 70 (e.g., the conductive via 60, the second ESL 30, the liner 52 in the trench 40, and the third dielectric layer 32) to a depth of equal to or less than about 2nm from the corresponding material of the processing surface 70, and at a concentration of about 1x10 ¹⁸ cm ^-3 Up to about 1x10 ¹⁹ cm ^-3 Within a range of (2). The concentration of the species may decrease from a peak near the corresponding treatment surface 70 to a depth in the material. Sputtering can break bonds by collisions of species with atoms of the exposed material (e.g., the treatment surface 70).

In another example, the nucleation enhancement process is a beam line implantation (operation 226). For beam-line implantationThe species may include silicon (Si), germanium (Ge), carbon (C), nitrogen (N), argon (Ar), and the like, or combinations thereof. The implantation energy may be in the range of about 2keV to about 10 keV. The implant dose may be about 10 ¹³ cm ^-2 Up to about 2x10 ¹⁵ cm ^-2 Within a range of (2). The implantation may be from the corresponding exposed surface to a depth in the range of about 1nm to about 4nm, and the concentration of implanted species is about 5x10 ¹⁸ cm ^-3 Up to about 5x10 ²¹ cm ^-3 Within a range of (2). The concentration of the species may decrease from a peak near the corresponding treatment surface 70 to a depth in the material. The beam line implant may be directional, but in some examples multiple implants may be performed to achieve a more conformal process. The beam line implant may break bonds by collisions of the implanted species with atoms of the implanted material (e.g., the process surface 70).

In other examples, the nucleation enhancement process is a plasma process (operation 228). The plasma treatment may include the use of a plasma containing xenon (Xe), argon (Ar), hydrogen (H) ₂ ) Nitrogen (N) ₂ ) Etc. or a combination thereof. The flow rate of the gas may be in the range of about 10sccm to about 2,000 sccm. The pressure of the plasma treatment may be in the range of about 10mTorr to about 100mTorr and the temperature of the plasma treatment may be in the range of about-20 ℃ to about 60 ℃. The power of the plasma generator of the plasma treatment may be in the range of about 20W to about 200W, and the frequency of the plasma generator may be about 13.56MHz or more. The substrate during plasma processing may be biased in the range of about 50V to about 300V. The species of the plasma may damage the exposed surface and may diffuse into the exposed surface. The plasma treatment may be conformal or directional. The plasma treatment may embed the substances of the plasma in the treatment surface 70 and/or diffuse in the corresponding material to a depth below the treatment surface 70. For example, species for the plasma (e.g., xenon, argon, hydrogen, etc.) may diffuse into the material forming the processing surface 70 (e.g., the conductive via 60, the second ESL30, the liner 52 in the trench 40, and the third dielectric layer 32) to a depth of equal to or less than about 5nm from the corresponding material of the processing surface 70, and at about 1x10 ¹⁸ cm ^-3 Up to about 1x10 ²⁰ cm ^-3 At a concentration within the range of (2). The concentration of the species may decrease from a peak near the corresponding treatment surface 70 to a depth in the material.

In yet another example, the nucleation enhancement process is a UV process (operation 230). The UV treatment may include exposing the substrate to UV light in the environment. The environment may include a gas containing argon (Ar), neon (Ne), xenon (Xe), or the like, or a combination thereof. The energy of the UV light exposure may be in the range of about 3.4eV to about 10 eV. The duration of the UV light exposure may be equal to or less than about 300 seconds, such as in the range of about 15 seconds to about 300 seconds. UV treatment can cause bond failure on the exposed surface, thereby damaging the exposed surface. Environmental species during UV treatment can diffuse into the exposed surface. For example, ambient substances (e.g., xenon, argon, neon, etc.) may diffuse into the material forming the processing surface 70 (e.g., the conductive via 60, the second ESL 30, the liner 52 in the trench 40, and the third dielectric layer 32) to a depth equal to or less than about 5nm from the corresponding material of the processing surface 70. The concentration of the species may decrease from a peak near each treatment surface 70 to a depth in the material. The UV treatment may be directional, but in some examples multiple UV treatments may be performed to achieve a more conformal treatment.

In a further example, the nucleation enhancement process is plasma doping (operation 232). The species for plasma doping may include boron (B), argon (Ar), and the like, or a combination thereof. The doping can be to a depth in the range of about 1nm to about 5nm and at a concentration of about 1x10 to the corresponding exposed surface ¹⁹ cm ^-3 Up to about 1x10 ²⁰ cm ^-3 Within a range of (2). The concentration of the species may decrease from a peak near the corresponding treatment surface 70 to a depth in the material. Plasma doping can break bonds by atomic collisions of the implanted species with the implanted material (e.g., the process surface 70).

Operation 234 of fig. 8 and method 200 illustrates forming a conductive fill material 80, such as filling trenches 40, on processing surface 70. Formation of the conductive fill material 80 may be deposited on the dielectric surface as well as on the metal surface by a deposition process. The nucleation enhancement process described with respect to fig. 7 may create nucleation sites on the dielectric surface (e.g., on the process surface 70) where the conductive filler material 80 may be adsorbed during deposition. Thus, the deposition of the conductive fill material 80 may be a bottom-up deposition and/or a conformal deposition, such as depending on the directionality of the nucleation enhancement process. In bottom-up deposition, cracking may be avoided by allowing a single growth front of conductive fill material 80 to propagate vertically in trench 40.

Due to the conformal deposition, a crack 82 may be formed in the conductive fill material 80 in the trench 40. The cracks 82 may result from the merging or coalescence of the different growth fronts of the conductive fill material 80 during conformal deposition. For example, the growth fronts from the sidewall surfaces of liner 52 along the sidewalls of third dielectric layer 32 may coalesce or merge with the growth fronts from the top surface of second ESL 30 to form at least a portion of crack 82. Each of the cracks 82 includes, for example, one or more voids, grain boundaries of the conductive filler material 80, and/or other signs of coalescence or coalescence of the growth fronts. The slit 82 may have an angle 86 relative to vertical (e.g., perpendicular to the top surface of the second ESL 30). The angle 86 may be in the range of about 25 to about 75, more specifically, in the range of about 30 to about 60. Angle 86 may be affected by the proximity of the sidewall surface of pad 52 to conductive via 60. In some examples, the rate at which the conductive fill material 80 grows from the conductive via 60 is greater than the rate at which it grows from the dielectric surface (e.g., the sidewall of the liner 52), such as about two to about three times. Thus, in such an example, the closer the sidewall of the pad 52 is to the conductive via 60, the smaller the angle 86 may be.

In some examples, the deposition of the conductive fill material 80 includes using CVD, electroless plating or deposition, or other deposition process. The conductive fill material 80 may be or include a metal such as ruthenium (Ru), nickel (Ni), molybdenum (Mo), cobalt (Co), tungsten (W), copper (Cu), or the like, or a combination thereof. In some examples, the conductive fill material 80 is or includes ruthenium (Ru), molybdenum (Mo), cobalt (Co), or tungsten (W) deposited by CVD. Exemplary precursors for ruthenium include triruthenium dodecacarbonyl (Ru ₃ (CO) ₁₂ ) CHORUS, etc., or itA combination thereof. Exemplary precursors for molybdenum include molybdenum (V) chloride (MoCl ₅ )、Mo(CO) ₅ Etc., or a combination thereof. Exemplary precursors for cobalt include dicarbonyl hexacarbonyl tert-butylacetylene (CCTBA), and the like, or combinations thereof. Exemplary precursors for tungsten include tungsten hexafluoride (WF) ₆ ) Tungsten (V) chloride (WCl) ₅ ) Etc., or a combination thereof. The flow rate of the precursor gas during CVD may be in the range of about 10sccm to about 200sccm, and the flow rate of the carrier gas (e.g., argon (Ar)) may be in the range of about 100sccm to about 800 sccm. The pressure of CVD may be in the range of about 0.2mTorr to about 20 mTorr. The temperature of CVD can be less than or equal to about 175 ℃, such as in the range of 120 ℃ to 170 ℃ (e.g., particularly for ruthenium deposition). In other examples, electroless plating or deposition may be used to deposit nickel. An anneal or reflow may be performed after the conductive fill material 80 is deposited.

In some examples, silicide and/or carbide may be formed along the treated surface 70 of the dielectric material including silicon and/or carbon. For example, assuming that the liner 52 and the second ESL 30 comprise silicon, the nucleation enhancing process may cause the silicon to have dangling bonds at the process surface 70, and the metal of the conductive fill material 80 may attach to the dangling bonds and/or react with the silicon of the process surface 70 to form a silicide at the interface between the conductive fill material 80 and the liner 52 or the second ESL 30. The metal of the conductive filler material 80 may attach to dangling bonds and/or react with silicon of the processing surface 70 during deposition of the conductive filler material 80 (e.g., when a precursor flows on the processing surface 70) and/or after deposition of the conductive filler material 80. Similarly, for example, assuming that the liner 52 and the second ESL 30 comprise carbon, the nucleation enhancing treatment may cause the carbon to have dangling bonds at the treatment surface 70, and the metal of the conductive filler material 80 may attach to the dangling bonds and/or react with the carbon of the treatment surface 70 to form carbides (e.g., metal carbides) at the interface between the conductive filler material 80 and the liner 52 or the second ESL 30. The metal of the conductive filler material 80 may attach to dangling bonds and/or react with carbon of the processing surface 70 during deposition of the conductive filler material 80 (e.g., when a precursor flows on the processing surface 70) and/or after deposition of the conductive filler material 80. With dangling and/or broken bonds of silicon and/or carbon of the treated surface 70, silicide and/or carbide may be formed at the treated surface 70 to enhance nucleation of the conductive fill material 80 and promote adhesion of the conductive fill material 80 to dielectric layers, such as the liner 52 and the second ESL 30.

In some examples, the metal of the conductive via 60 may form a metal alloy or compound with the metal of the conductive filler material 80 at the treated surface 70 of the conductive via 60. The nucleation enhancing treatment may break bonds at the treated surface 70 of the conductive via 60 to allow the metal of the conductive via 60 and the conductive filler material 80 to mix and/or react at the treated surface 70 of the conductive via 60. The metal of the conductive filler material 80 may mix and/or react with the metal of the conductive via 60 at the processing surface 70 during deposition of the conductive filler material 80 (e.g., when a precursor flows over the processing surface 70) and/or after deposition of the conductive filler material 80. The conductive via 60 and the conductive filler 80 may be electrically connected without significant resistance caused by the species used in the nucleation enhancement process to form the treated surface 70.

Still further, in some examples, a substance for nucleation enhancement treatment may be embedded in the treatment surface 70 or on the treatment surface 70, such as by adsorption, diffusion, and/or implantation, and the substance may react with the conductive filler material 80. For example, silicon or germanium implanted in the processing surface 70 may react with the metal of the conductive fill material 80 to form a metal-semiconductor compound (e.g., silicide or germanide, respectively). As another example, carbon implanted in the treatment surface 70 may react with the metal of the conductive filler material 80 to form a metal carbide, or nitrogen implanted in the treatment surface 70 may react with the metal of the conductive filler material 80 to form a metal nitride. In other examples, other compounds may be formed.

In some examples, the substances used for the nucleation enhancing treatment may be embedded in or on the treatment surface 70 and may remain unreacted with other materials. For example, an inert species (such as argon) may remain unreacted at or near the treatment surface 70. Unreacted species may diffuse into the corresponding dielectric layer. Depending on the nucleation enhancement process, the highest concentration of unreacted species may decrease at the process surface 70 (e.g., of the dielectric layer or conductive via 60) and in the direction from the process surface 70 to the respective dielectric layer or conductive via 60, or may increase in the direction from the process surface 70 to the respective dielectric layer or conductive via 60 to a peak before decreasing in that direction, such as when species are injected by beam line injection, plasma doping, or similar techniques.

The extent to which the material used for the nucleation enhancement treatment may be embedded in or on the different treatment surfaces 70 may depend on the directionality of the nucleation enhancement treatment. For example, highly directional nucleation enhancement processes, such as beam line implantation, may cause some surfaces to have more material embedded therein or thereon than others. Specifically, in some examples, the horizontal surface (e.g., the top surface of the second ESL 30) may have more material embedded therein or thereon than the vertical surface (e.g., the sidewalls of the liner 52). In some examples, the multi-directional nucleation enhancement treatment may be performed in different directions to obtain a more uniform treatment between different surfaces, such as multi-beam line implantation at different implantation angles.

Fig. 9 illustrates removing excess conductive fill material 80 to form conductive lines 84 in the third dielectric layer 32. A planarization process such as CMP may be used to remove the excess conductive fill material 80 and the treated surface 70 of the third dielectric layer 32. The third dielectric layer 32 may be further thinned by a planarization process, and in some examples, the third dielectric layer 32 may remove rounded corners of the trench 40. In some examples, the third dielectric layer 32 is thinned to a thickness of about 10nm to about 30 nm. The removal of excess conductive fill material 80 and the treated surface 70 of the third dielectric layer 32 may form the top surfaces of the conductive fill material 80 and the third dielectric layer 32 to be coplanar. As described above, the slit 82 may remain in the wire 84. In some examples, the fracture 82 may be cured or removed by annealing or other thermal processes used during processing. As shown in fig. 9, an interconnect structure, such as a dual damascene interconnect structure, may be formed including conductive via 60 and wire 84.

FIG. 10 shows a thirdDielectric layer 32, conductive line 84, and third ESL90 and fourth dielectric layer 92 over liner 52 along the sidewalls of trench 40, and wherein conductive feature 94 contacts conductive line 84 through third ESL90 and fourth dielectric layer 92. A third ESL90 may be deposited over the third dielectric layer 32, the wire 84, and the liner 52. The third ESL90 may comprise or be silicon nitride, silicon carbonitride, silicon oxycarbide, carbon nitride, the like, or combinations thereof, and may be deposited by CVD, PECVD, ALD or deposition techniques thereof. A fourth dielectric layer 92 is deposited over the third ESL 90. For example, fourth dielectric layer 92 may be or include an IMD. The fourth dielectric layer 92 may be or include, for example, a low-k dielectric having a k value of less than about 4.0, such as about 2.0 or even less. In some examples, the fourth dielectric layer 92 includes silicon oxide, PSG, BPSG, FSG, siO _x C _y Silicon carbon materials, their compounds, their composites, or combinations thereof. CVD such as PECVD or FCVD may be used; spin coating; or other deposition technique to deposit the fourth dielectric layer 92. In some examples, CMP or another planarization process may be performed to planarize the top surface of the fourth dielectric layer 92.

The conductive member 94 of the contact wire 84 may be or include, for example, a conductive via or another conductive member. Conductive feature 94 may be formed using a damascene process, such as a dual damascene process. For example, the conductive member 94 may be formed using the process shown above with reference to fig. 2-9 or using a similar process.

As is apparent from the foregoing, no seed layer and no metal-containing barrier layer are deposited in the example described for forming conductive via 60 and conductive line 84. In the illustrated and described example, no seed layer and no metal-containing barrier layer are deposited between (i) the wire 84 and any dielectric layer (e.g., the third dielectric layer 32 or the second ESL 30) on or in which the wire 84 is deposited, (ii) the conductive via 60 and any dielectric layer (e.g., the second ESL 30, the second dielectric layer 28, or the first ESL 26) in which the conductive via 60 is disposed; or (iii) between the conductive via 60 and the wire 84. Some embodiments may implement a seed layer and/or a metal-containing barrier layer. Further, while the nucleation enhancing treatment substance may react with the metal of the conductive line 84 (e.g., conductive fill material 80) and/or the conductive via 60, such as at the treated surface 70 of the conductive via 60 (e.g., the interface between the conductive via 60 and the conductive line 84), the resulting material may be thinner and/or have a lower concentration of substance than the deposited barrier layer, and thus, may not be a diffusion barrier layer in some cases. For example, in some examples where the nucleation enhancement process is performed, the substance may have a concentration of less than or equal to about 5 atomic percent (at.%) at the corresponding treated surface in the conductive line 84 (e.g., conductive filler material 80) and/or conductive via 60, such as in the range of about 0.1at.% to about 5 at.%. The concentration of the substance in the conductive line 84 (e.g., conductive fill material 80) and/or conductive via 60 may be discontinuous because of the low concentration of the substance therein. Further, the substance and conductive material of the conductive line 84 and/or the conductive via 60 may not be in a stable phase of the corresponding material compound (e.g., metal compound).

Fig. 13-18 illustrate various details and/or modifications of portions of the cross-sectional view of the intermediate structure of fig. 6, in accordance with some embodiments. Fig. 13-18 illustrate additional details and/or modifications to the via opening 42 formed in fig. 2 and the corresponding conductive via 60 formed in the via opening 42 in fig. 5 and 6. Fig. 13-18 each show a first ESL 26 over the conductive feature 24, a second dielectric layer 28 over the first ESL 26, and a second ESL 30 over the second dielectric layer 28. Although the via openings 42 are not specifically identified in fig. 13-18, one of ordinary skill in the art will readily understand when viewing the drawings that the sidewalls of the first ESL 26, the second dielectric layer 28, and the second ESL 30 (with the conductive via 60 disposed therebetween) are the sidewalls of the via openings 42 formed in fig. 2. The via opening 42 in fig. 13-18 has a first dimension D1 (e.g., depth) from the top surface of the conductive member 24 exposed through the via opening 42 to the top surface of the second ESL 30. The first dimension D1 may correspond to the combined thickness of the first ESL 26, the second dielectric layer 28, and the second ESL 30. The first dimension D1 may be in the range of about 8nm to about 40nm, more specifically, in the range of about 10nm to about 30nm, such as about 25nm.

In fig. 13 and 14, the via opening 42 has substantially vertical sidewalls with rounded corners at the upper corners (e.g., sidewalls of the first ESL 26, the second dielectric layer 28, and the second ESL30 on which the liner 52 is formed). The via opening 42 has a second dimension D2 (e.g., width) at the bottom of the via opening 42 in fig. 13 and 14 (e.g., at the top surface of the conductive feature 24) and a third dimension D3 (e.g., width) in the plane of the top surface of the second ESL 30. In some examples, the second dimension D2 is in a range of about 8nm to about 14nm, and in some examples, the third dimension D3 is in a range of about 13nm to about 19 nm. The first aspect ratio of the first dimension D1 to the second dimension D2 may be in the range of about 0.7 to about 3.75, and the second aspect ratio of the first dimension D1 to the third dimension D3 may be in the range of about 0.53 to about 2.31.

In fig. 15 and 16, the via opening 42 has vertical sidewalls (e.g., the sidewalls of the first ESL 26, the second dielectric layer 28, and the second ESL30 on which the liner 52 is formed are vertical). Thus, the cross-section of the via opening 42 is rectangular. The via opening 42 has a sixth dimension D6 (e.g., width) at the bottom of the via opening 42 in fig. 15 and 16 (e.g., at the top surface of the conductive member 24). Since the sidewalls are vertical, the dimension (e.g., width) of the via opening 42 in the plane of the top surface of the second ESL30 is equal to the sixth dimension D6. In some examples, the sixth dimension D6 is in a range of about 8nm to about 14 nm. The aspect ratio of the first dimension D1 to the sixth dimension D6 may be in the range of about 0.7 to about 3.75.

In fig. 17 and 18, the via opening 42 has non-vertical or sloped sidewalls (e.g., the sidewalls of the first ESL 26, the second dielectric layer 28, and the second ESL 30 on which the liner 52 is formed are non-vertical or sloped). Thus, the cross-section of the via opening 42 may have a positively tapered profile, as shown, and in other examples, the cross-section of the via opening 42 may be a reentrant profile. The via opening 42 has a ninth dimension D9 (e.g., width) at the bottom of the via opening 42 in fig. 17 and 18 (e.g., at the top surface of the conductive feature 24) and a tenth dimension D10 (e.g., width) in the plane of the top surface of the second ESL 30. In some examples, the ninth dimension D9 is in the range of about 8nm to about 14nm, and in some examples, the tenth dimension D10 is in the range of about 13nm to about 19 nm. The first aspect ratio of the first dimension D1 to the ninth dimension D9 may be in the range of about 0.7 to about 3.75, and the second aspect ratio of the first dimension D1 to the tenth dimension D10 may be in the range of about 0.53 to about 2.31.

In fig. 13, 15, and 17, the conductive via 60 has convex upper surfaces 100, 104, and 108 (e.g., convex curved surfaces) that protrude above the top surface of the second ESL 30. The cross-sections of the convex upper surfaces 100, 104, and 108 may be part-circular (e.g., semi-circular), part-elliptical (e.g., semi-elliptical), or other shapes. For example, the convex upper surfaces 100, 104, and 108 may have an uppermost point at a horizontal surface above the top surface of the second ESL 30, and the bottom of the convex top surface may be at a horizontal surface above the top surface of the second ESL 30, at a horizontal surface below the top surface of the second ESL 30, or at a horizontal surface below the top surface of the second ESL 30. As shown, the uppermost points of the convex upper surfaces 100, 104, and 108 protrude above the top surface of the second ESL 30 by a fourth dimension D4, a seventh dimension D7, and an eleventh dimension D11, respectively. The fourth, seventh and eleventh dimensions D4, D7 and D11 may range from about 0nm to about the respective second, sixth and ninth dimensions D2, D6 and D9. In other examples, the uppermost points of the convex upper surfaces 100, 104, and 108 may be at a horizontal surface below the top surface of the second ESL 30 or at a horizontal surface of the top surface of the second ESL 30.

In fig. 14, 16 and 18, the conductive via 60 has convex upper surfaces 102, 106 and 110 (e.g., concave curved surfaces) that are located below the top surface of the second ESL 30. The cross-section of concave upper surfaces 102, 106, and 110 may be partially circular (e.g., semi-circular), partially elliptical (e.g., semi-elliptical), or other shapes. The concave upper surfaces 102, 106, and 110 may have a lowest point at a horizontal surface below the top surface of the second ESL 30. The upper portions of concave upper surfaces 102, 106, and 110 may be at a horizontal surface above the top surface of second ESL 30 or at a horizontal surface above the top surface of second ESL 30. As shown, the lowest point of concave upper surfaces 102, 106, and 110 is below the top surface of second ESL 30 by fifth dimension D5, eighth dimension D8, and twelfth dimension D12, respectively. The fifth dimension D5, eighth dimension D8, and twelfth dimension D12 may each be in the range of about 0nm to about two-thirds (e.g., (2/3) ×d1) of the first dimension D1. In other examples, the top surface may have other shapes, such as being planar, and may be at any horizontal surface relative to the top surface of the second ESL 30 and/or another dielectric layer.

Fig. 19-21 illustrate cross-sectional views of respective intermediate structures during an exemplary method for forming an interconnect structure, in accordance with some other embodiments. Fig. 19 and 20 illustrate an implementation of a cleaning process (operation 210 of method 200) on the intermediate interconnect structure of fig. 4 (e.g., after operations 202-208 are completed). The cleaning process according to this embodiment is illustrated in more detail in fig. 21. In this embodiment, the cleaning process includes a plasma treatment (operation 260), a subsequent halide soak (operation 262), and a subsequent reduction treatment (operation 264).

In the illustrated embodiment, the conductive member 24 is a multi-layer member that includes a body 24A formed of a first material (e.g., cobalt) and a cap layer 24B formed of a second material (e.g., tungsten). The cleaning process cleans the cap layer 24B of the conductive member 24. In some embodiments, such as those described above, the conductive member 24 is a single continuous metal layer (e.g., tungsten).

Fig. 19 shows the implementation of plasma processing (operation 260) and halide soaking (operation 262). The plasma treatment serves to physically clean residues from trenches 40 and/or through openings 42. The halide soak serves to remove native oxides that may form on the metal components (e.g., conductive components 24) during processing.

The plasma treatment may include the use of hydrogen (H ₂ ) Argon (Ar), helium (He), neon (Ne), O ₂ 、O ₃ 、N ₂ Or NH ₃ The gas and carrier gas, such as argon (Ar). A plasma sheath is created and hydrogen accelerates through the plasma sheath to bombard the via opening 42. In some cases, the plasma treatment may reduce the formation of trenches 40 and/or via openings 42 on sidewalls and/or bottom surfaces during the etching process used to pattern first ESL 26, second dielectric layer 28, second ESL30, third dielectric layer 32, and/or liner layer 50 Residual oxides, nitrides and/or carbides of (a). The flow rate of hydrogen gas in the plasma treatment may be in the range of about 5sccm to about 1,000sccm, and the flow rate of carrier gas in the plasma treatment may be in the range of about 0sccm to about 1,000 sccm. The pressure of the plasma treatment may be in the range of about 10mTorr to about 200 mTorr. The temperature of the plasma treatment may be in the range of about-20 ℃ to about 100 ℃. The power of the plasma generator of the plasma treatment may be in the range of about 20W to about 400W, and the frequency of the plasma generator may be about 13.56MHz or more. The substrate during plasma processing may be biased in the range of about 20V to about 200V. The plasma treatment may be performed for a shorter duration. In particular, the plasma treatment may be performed for a duration sufficient to physically clean residues from trenches 40 and/or through openings 42, but may not be performed long enough to remove native oxide that may have formed on conductive feature 24. For example, in some embodiments, the duration of the plasma treatment may be in the range of about 5 seconds to about 300 seconds. Performing the plasma treatment in a short time reduces the risk of damaging the via opening 42 or the contour of the conductive member 24 during the plasma treatment.

The halide soaking includes exposing the conductive member 24 to one or more soaking agents. The soaking agent is a halide of the material of the conductive member 24. In some embodiments, the soaking agent is a chloride or fluoride of the material of the conductive member 24. For example, in embodiments where the conductive member 24 is formed of tungsten (W), the halide is tungsten hexafluoride (WF) ₆ ). Also, in embodiments where the silicide (e.g., tiSi) is formed on the conductive member 24, the halide may be titanium tetrachloride (TiCl) ₄ ) Titanium Tetrafluoride (TiF) ₄ ) Or a combination thereof. In some embodiments, one or more precursors used to form the conductive member 24 may also be used as a soaking agent. Continuing with the example where conductive member 24 is formed of tungsten, the same precursor (e.g., WF ₆ ) Can be used for the deposition of the conductive features 24 and for the dipping of the conductive features 24. The halide soak occurs in a process chamber, which in some embodiments is the same process chamber used to deposit the material of the conductive member 24. Halide leachingThe pressure of the bubble may be in the range of about 1Torr to about 10 Torr. The temperature of the halide soak may be in the range of about 300 ℃ to about 450 ℃. The duration of the halide soak may range from about 5 seconds to about 120 seconds.

The halide soak removes native oxide that may have formed on the conductive features 24. Specifically, the halide immersion agent converts the solid phase native oxide to a vapor phase oxide, which is then evacuated from the via openings 42 and trenches 40. Continuing with the example where conductive member 24 is formed of tungsten, tungsten oxide may be formed on the exposed surface of conductive member 24 during processing according to the following equation:

W+1.5O ₂ →WO ₃ .(1)

the tungsten oxide was converted to tungsten oxyfluoride by exposure to a halide soak according to the following conditions:

2WO ₃ +WF ₆ →3WO ₂ F ₂ .(2)

the resulting tungsten oxyfluoride gas may then be evacuated from the process chamber. Evacuation may be accomplished, for example, by flowing an inert gas (e.g., ar) through the process chamber to entrain the tungsten oxyfluoride. Removal of native oxide from the exposed surfaces of the conductive features 24 with a halide soak may reduce damage to the conductive features 24 during removal of the native oxide. In addition, the halide immersion agent may etch the conductive feature 24 without substantially etching the first ESL 26, the second dielectric layer 28, the second ESL 30, the third dielectric layer 32, or the liner layer 50. Thus, the halide soak may allow cleaning of the exposed surfaces of the conductive members 24 without substantially damaging the profile of the via openings 42. The process window of the cleaning process may be improved, particularly when the width of the via opening 42 is less than about 10 nm. Furthermore, avoiding damaging the profile of the via opening 42 may reduce the chance of void formation in the via opening 42 during formation of the conductive via 60 (see fig. 5).

Some of the residue 112 may remain in the via opening 42 after the halide soak. The residue 112 may be a residue of the soaking agent itself, or may be a residual byproduct of the soaking. Continuing with the example where conductive member 24 is formed of tungsten, residue 112 may be WF ₆ W, F or WO ₂ F ₂ . Residue 112 may be along the sidewalls and/or bottom of via opening 42.

Fig. 20 shows an implementation of the reduction process (operation 264). The reduction treatment includes exposing the conductive member 24 to one or more reducing agents, such as H ₂ . Exposure to the reducing agent allows additional material of the conductive member 24 (e.g., material of the cap layer 24B) to be selectively redeposited in the via opening 42. The reducing agent reacts with the residue 112, such as with a residual halide immersion agent, to form additional material for the conductive member 24. The amount of residue 112 in the via opening 42 can be reduced. Continuing with the example where the conductive member 24 is formed of tungsten, the halide soaking agent and residue 112 may include WF ₆ And the additional material of the conductive member 24 may be formed according to the following formula:

WF ₆ +3H ₂ →W+6HF.(3)

the reduction treatment may be performed at low pressure and low temperature. The pressure of the reduction process may be in the range of about 100mTorr to about 300 mTorr. The temperature of the reduction treatment may be in the range of about 300 ℃ to about 400 ℃. The duration of the reduction treatment may be in the range of about 5 seconds to about 60 seconds.

The redeposited portion of conductive feature 24 (e.g., cap layer 24B) extends at least partially upward into via opening 42. The redeposited portion of the conductive feature 24 has a thirteenth dimension D13 from the bottom surface of the first ESL 26 to the top surface of the conductive feature 24. In some examples, the thirteenth dimension D13 is in the range of about 2nm to about 15nm, such as less than about 5nm. In some embodiments, the conductive member 24 has an original height, fourteenth dimension, D14, which in some examples is in the range of about 10nm to about 50 nm. The thirteenth dimension D13 may be in the range of about 5% to about 40% of the fourteenth dimension D14.

After the reduction process, a subsequent process as described above may be performed to produce an interconnect structure. Details of further processing will not be repeated herein. Fig. 22 illustrates the resulting interconnect structure after subsequent processing (e.g., after operations 216-234 are completed). The interconnect structure of fig. 22 is similar to the interconnect structure of fig. 10 and includes some of the etchant residue 112 surrounding the conductive via 60. Further, the redeposited portion of the conductive member 24 contacts a portion of the sidewall of the pad 52, and the bottom surface of the pad 52 is located below the bottom surface of the conductive via 60. The interface of the conductive feature 24 and the conductive via 60 may be located below the top surface of the first ESL 26, flush with the top surface of the first ESL 26, or above the top surface of the first ESL 26. While some of the residue 112 is shown at the interface of the conductive feature 24 and the conductive via 60, it should be understood that some or all of the residue 112 at the interface may be consumed by the reduction process (operation 264). The sidewalls of the conductive via 60 may have more residue 112 than the interface of the conductive feature 24 and the conductive via 60. In some embodiments, no residue 112 remains at the interface of conductive feature 24 and conductive via 60.

While the resulting interconnect structure of fig. 22 is similar to the interconnect structure of fig. 10, it should be understood that the cleaning process shown in fig. 21 may be applicable to other embodiments. For example, the resulting interconnect structure may optionally be similar to the embodiments of fig. 13-18.

Some embodiments may achieve a number of advantages. The halide soaking performed as part of the cleaning process of the via opening 42 allows the duration of the plasma treatment to be reduced, which may reduce damage to the profile of the via opening 42 caused by the cleaning process. The chance of void formation in the conductive via 60 can be reduced. Removing native oxide from the conductive feature 24 with a halide soak and redeposition additional material of the conductive feature 24 by a reduction process may create a clean (e.g., oxide free) surface on which the conductive vias 60 may be formed, thereby reducing the resistance of the interconnect structure. As previously described, some embodiments may avoid seed layers and/or barrier layers. Without the seed layer and/or barrier layer, the resistance of the interconnect structure may be reduced, thereby reducing resistance-capacitance (RC) delay and increasing device speed. Further, the deposition of the conductive fill material in forming the interconnect structure may be by bottom-up deposition and/or conformal deposition due to a nucleation enhancement process. Bottom-up deposition and/or conformal deposition may reduce the amount of time to fill the trench, which may increase throughput and reduce cost during processing. The exemplary embodiments may be applied to any technology node and may be particularly applicable to improved technology nodes, such as 20nm and less.

In an embodiment, a method comprises: etching an interconnect opening through one or more dielectric layers over the semiconductor substrate, the interconnect opening having a via opening exposing a conductive feature over the semiconductor substrate, the conductive feature comprising a first layer of a first conductive material, and a trench over the via opening; treating the via opening with a plasma to physically remove etching residues from sidewalls and bottom of the via opening; soaking the conductive member with a halide of the first conductive material, the residual halide of the first conductive material remaining in the via opening after soaking; reducing the residual halide of the first conductive material to form a second layer of the first conductive material on the first layer; depositing a conductive via in a via opening on a second layer of a first conductive material; and forming a conductive line on one or more exposed dielectric surfaces of the trench and in the trench over the conductive via.

In some embodiments of the method, the first conductive material is tungsten and the halide of the first conductive material is tungsten hexafluoride. In some embodiments of the method, reducing the residual halide of the first conductive material includes exposing the residual halide to hydrogen. In some embodiments of the method, forming the conductive line includes conformally depositing a material of the conductive line in the trench over the one or more exposed dielectric surfaces. In some embodiments of the method, depositing the material of the conductive line does not include depositing a seed layer for depositing the material of the conductive line. In some embodiments of the method, a metal-containing barrier layer is not deposited in the interconnect opening prior to depositing the material of the conductive line. In some embodiments, the method further comprises: prior to depositing the material of the conductive line, one or more exposed dielectric surfaces of the trench are subjected to a nucleation enhancement treatment. In some embodiments of the method, the nucleation enhancing treatment increases the number of nucleation sites on the surface of the dielectric layer exposed in the trench by breaking chemical bonds on the surface of the dielectric layer exposed in the trench.

In an embodiment, a method comprises: etching an interconnect opening through the one or more dielectric layers over the semiconductor substrate, the interconnect opening having a via opening exposing a conductive feature over the semiconductor substrate, the conductive feature comprising a conductive material, and a trench over the via opening; cleaning the through hole opening; depositing a conductive via in the clean via opening; performing a nucleation enhancement treatment on one or more exposed dielectric surfaces of the trench; and forming a conductive line on one or more exposed dielectric surfaces of the trench and in the trench over the conductive via.

In some embodiments of the method, cleaning the via opening comprises: the via openings are cleaned with a halide of the conductive material. In some embodiments of the method, etching the interconnect opening forms an etching residue in the via opening and a native oxide on the surface of the conductive feature, and cleaning the via opening comprises: removing etching residues by treating the via openings with plasma; and removing the native oxide by exposing the surface of the conductive member to a halide of the conductive material. In some embodiments of the method, treating the via opening with plasma includes: the via opening is bombarded with hydrogen for a duration of about 5 seconds to about 300 seconds. In some embodiments of the method, exposing the surface of the conductive member comprises: the surface of the conductive member is soaked with a halide of the conductive material, and the halide remains in the via opening after the soaking. In some embodiments, the method further comprises: additional conductive material is redeposited on the conductive member by exposing the surface of the conductive member to a reducing agent. In some embodiments of the method, exposing the surface of the conductive member to the reducing agent comprises: the residual halide is reduced with hydrogen, and the reduced residual halide forms an additional conductive material. In some embodiments, the method further comprises: a conductive feature is deposited over a semiconductor substrate with a plurality of precursors for a conductive material, a halide of which is one precursor for a conductive material. In some embodiments of the method, the nucleation enhancement process increases the number of nucleation sites on the exposed dielectric surfaces of the trench by breaking chemical bonds of the exposed dielectric surfaces of the trench. In some embodiments of the method, forming the conductive line includes conformally depositing a material of the conductive line on the exposed dielectric surfaces of the trench without depositing a seed layer of the material for the conductive line.

In an embodiment, a method comprises: depositing a conductive feature over a substrate, the depositing comprising providing a plurality of precursors for a first conductive material; depositing one or more dielectric layers over the conductive features; etching an interconnect opening through the one or more dielectric layers, the interconnect opening having a via portion and a line portion located above the via portion; cleaning the sidewalls and bottom surfaces of the interconnect opening with a halide of a first conductive material, the halide of the first conductive material being a precursor for the first conductive material; depositing a conductive via in the via portion of the cleaned interconnect opening, the conductive via contacting the conductive feature; and depositing a conductive line in the line portion of the cleaned interconnect opening.

In some embodiments, the method further comprises: after cleaning the interconnect openings, a first layer of conductive material is deposited over the conductive features in the cleaned interconnect openings.

An embodiment is a method. An interconnect opening is formed through one or more dielectric layers over the semiconductor substrate. The interconnect opening has a via opening and a trench located above the via opening. Conductive vias are formed in the via openings. A nucleation enhancement treatment is performed on one or more exposed dielectric surfaces of the trench. Conductive lines are formed on one or more exposed dielectric surfaces of the trench and in the trench over the conductive via.

Another embodiment is a structure. The structure includes a semiconductor substrate, one or more dielectric layers over the semiconductor substrate, and an interconnect structure disposed in the one or more dielectric layers. The interconnect structure includes a conductive via and a wire located over the conductive via. The conductive lines are disposed on horizontal surfaces of the one or more dielectric layers. The same substance is provided at the horizontal surface of the dielectric layer or layers and at the surface of the conductive via at the interface between the conductive via and the conductive filler material of the wire. In some embodiments, an upper surface of the conductive via at an interface between the conductive via and the conductive fill material of the wire is convex. In some embodiments, an upper surface of the conductive via at an interface between the conductive via and the conductive fill material of the wire is concave. In some embodiments, there are cracks in the conductive filler material of the wire. In some embodiments, the structure further comprises a metal semiconductor compound located at an interface between the conductive fill material of the conductive line and a surface of the one or more dielectric layers, wherein a metal of the metal semiconductor compound is the same metal as a metal of the conductive fill material. In some embodiments, the structure further comprises a metal carbide located at an interface between the conductive filler material of the wire and a surface of the one or more dielectric layers, wherein the metal of the metal carbide is the same metal as the metal of the conductive filler material. In some embodiments, the structure further comprises a metal alloy or metal compound located at an interface between the conductive fill material of the conductive line and the conductive via. In some embodiments, the dielectric surface of one or more dielectric layers abuts the wire; and the respective concentrations of the species decrease in respective directions from the dielectric surface to the one or more dielectric layers. In some embodiments, the structure further comprises: a first dielectric diffusion barrier liner along sidewalls of the conductive lines; and a second dielectric diffusion barrier liner along sidewalls of the conductive via. In some embodiments, no seed layer and no barrier layer are disposed between the conductive via and the wire.

Another embodiment is a structure comprising: a semiconductor substrate; a first dielectric layer over the semiconductor substrate; a conductive via extending through the first dielectric layer, the conductive via comprising a first conductive material; a second dielectric layer over the first dielectric layer; and a wire extending through the second dielectric layer, the wire including a second conductive material, the wire sharing a first interface with the conductive via, the wire sharing a second interface with a horizontal surface of the first dielectric layer, the wire sharing a third interface with a vertical surface of the second dielectric layer, the same substance being disposed at the first interface, the second interface, and the third interface, the first interface and the second interface having more substances than the third interface, the substances being different from the first conductive material and the second conductive material. In some embodiments, the substance is argon. In some embodiments, the species is a combination of silicon, germanium, carbon, nitrogen, and argon. In some embodiments, the substance is a combination of xenon, argon, hydrogen, and nitrogen. In some embodiments, the substance is a combination of argon, neon, and xenon. In some embodiments, the species is a combination of boron and argon.

Another embodiment is a structure comprising: a semiconductor substrate; a first conductive member over the semiconductor substrate; one or more dielectric layers over the first conductive feature; a first interconnect structure disposed in the one or more dielectric layers, the first interconnect structure including a conductive via and a conductive line, the conductive via and the conductive line contacting a horizontal surface of the one or more dielectric layers and a vertical surface of the one or more dielectric layers, the same substance being disposed at the horizontal surface of the one or more dielectric layers and the vertical surface of the one or more dielectric layers; and a second conductive feature over the first interconnect structure, wherein the conductive via includes a first conductive material that extends continuously between the first conductive feature and the wire, and wherein the wire includes a second conductive material that extends continuously between the conductive via and the second conductive feature. In some embodiments, more material is disposed at the horizontal surface of the one or more dielectric layers than at the vertical surface of the one or more dielectric layers. In some embodiments, the wire is free of cracks. In some embodiments, the conductive lines include a crack that forms an acute angle with respect to a vertical surface of the one or more dielectric layers, the acute angle being in a range from 30 ° to 60 °.

Another embodiment is a method. A dual damascene opening is formed through one or more dielectric layers over a semiconductor substrate. The dual damascene opening includes a trench and a via opening. Conductive vias are formed in the via openings. By breaking chemical bonds of the dielectric surface exposed in the trench, the number of nucleation sites on the dielectric surface exposed in the trench is increased. The conductive filler material is deposited in the trench by adsorbing the conductive filler material onto the increased number of nucleation sites. Depositing the conductive filler material does not include using a seed layer.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art will appreciate that they may readily use the present invention as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the invention.

Claims

1. A method for forming an interconnect structure, comprising:

Etching an interconnect opening through one or more dielectric layers over a semiconductor substrate, the interconnect opening having a via opening and a trench over the via opening, the via opening exposing a conductive feature over the semiconductor substrate, the conductive feature comprising a first layer of a first conductive material;

treating the via opening with plasma to physically remove etching residues from sidewalls and bottom of the via opening;

soaking the conductive member with a halide of the first conductive material, the residual halide of the first conductive material remaining in the via opening after soaking;

reducing the residual halide of the first conductive material to form a second layer of the first conductive material on the first layer of the first conductive material;

depositing a conductive via in a via opening on a second layer of the first conductive material; and

forming conductive lines on one or more exposed dielectric surfaces of the trench and in the trench over the conductive via,

wherein prior to depositing the material of the conductive line, one or more exposed dielectric surfaces of the trench are subjected to a nucleation enhancing treatment,

Wherein the conductive line contacts a horizontal surface of the one or more dielectric layers and a vertical surface of the one or more dielectric layers, the same substance being provided at the horizontal surface of the one or more dielectric layers, at an interface between the conductive via and the conductive filler material of the conductive line, and at the vertical surface of the one or more dielectric layers, wherein more substance is provided at the horizontal surface of the one or more dielectric layers and at the interface than at the vertical surface of the one or more dielectric layers,

wherein reducing the residual halide of the first conductive material comprises exposing the residual halide to hydrogen,

wherein the sidewall of the conductive via has more residual halide than the interface of the conductive feature and the conductive via.

2. The method of claim 1, wherein the first conductive material is tungsten and the halide of the first conductive material is tungsten hexafluoride.

3. The method of claim 1, wherein no residual halide remains at an interface of the conductive feature and the conductive via.

4. The method of claim 1, wherein forming the conductive line comprises conformally depositing a material of the conductive line in the trenches on the one or more exposed dielectric surfaces.

5. The method of claim 4, wherein depositing the material of the conductive line does not include depositing a seed layer for depositing the material of the conductive line.

6. The method of claim 4, wherein no metal-containing barrier layer is deposited in the interconnect opening prior to depositing the material of the conductive line.

7. The method of claim 1, wherein the nucleation enhancement process comprises a beam line implantation.

8. The method of claim 7, wherein the nucleation enhancement process increases the number of nucleation sites on the surface of the dielectric layer exposed in the trench by breaking chemical bonds of the surface of the dielectric layer exposed in the trench.

9. A method for forming an interconnect structure, comprising:

etching an interconnect opening through one or more dielectric layers over a semiconductor substrate, the interconnect opening having a via opening and a trench over the via opening, the via opening exposing a conductive feature over the semiconductor substrate, the conductive feature comprising a conductive material;

cleaning the through hole opening;

depositing a conductive via in the clean via opening;

performing a nucleation enhancement treatment on one or more exposed dielectric surfaces of the trench; and

wherein cleaning the via opening comprises:

cleaning the via opening with a halide of the conductive material, remaining halide of the conductive material remaining in the via opening after cleaning, and

reducing the residual halide of the conductive material,

10. The method of claim 9, wherein no residual halide remains at an interface of the conductive feature and the conductive via.

11. The method of claim 9, wherein etching the interconnect opening forms an etch residue in the via opening and a native oxide on a surface of the conductive feature, and cleaning the via opening further comprises:

removing the etching residues by treating the via openings with plasma; and

the native oxide is removed by exposing a surface of the conductive member to a halide of the conductive material.

12. The method of claim 11, wherein treating the via opening with the plasma comprises:

the via openings are bombarded with hydrogen for a duration of 5 seconds to 300 seconds.

13. The method of claim 11, wherein exposing the surface of the conductive member comprises:

the surface of the conductive member is immersed with a halide of the conductive material, and after the immersing, residual halide remains in the via opening.

14. The method of claim 11, further comprising:

additional conductive material is redeposited on the conductive member by exposing a surface of the conductive member to a reducing agent.

15. The method of claim 14, wherein exposing the surface of the conductive component to the reducing agent comprises:

The residual halide is reduced with hydrogen, the reduced residual halide forming the additional conductive material.

16. The method of claim 10, further comprising:

a conductive feature is deposited over the semiconductor substrate using multiple precursors for a conductive material, a halide of which is one precursor for the conductive material.

17. The method of claim 9, wherein the nucleation enhancement process increases the number of nucleation sites on the exposed dielectric surface of the trench by breaking chemical bonds of the exposed dielectric surface of the trench.

18. The method of claim 17, wherein forming the conductive line comprises conformally depositing a material of the conductive line on the exposed dielectric surfaces of the trench without depositing a seed layer of the material for the conductive line.

19. A method for forming an interconnect structure, comprising:

depositing a conductive feature over a substrate, the depositing comprising providing a plurality of precursors for a first conductive material;

depositing one or more dielectric layers over the conductive features;

etching an interconnect opening through the one or more dielectric layers, the interconnect opening having a via portion and a line portion located above the via portion;

Cleaning the sidewalls and bottom surfaces of the interconnect opening with a halide of the first conductive material, the halide of the first conductive material being a precursor for the first conductive material, and residual halide of the first conductive material remaining in the interconnect opening;

reducing residual halide of the first conductive material;

depositing a conductive via in the via portion of the cleaned interconnect opening, the conductive via contacting the conductive feature; and

depositing a conductive line in the line portion of the cleaned interconnect opening,

wherein prior to depositing the material of the conductive lines, one or more exposed dielectric surfaces of the cleaned interconnect openings are subjected to a nucleation enhancing treatment,

20. The method of claim 19, further comprising:

after cleaning the interconnect openings, a layer of the first conductive material is deposited over the conductive features in the cleaned interconnect openings.

21. An interconnect structure, comprising:

a semiconductor substrate;

one or more dielectric layers over the semiconductor substrate; and

an interconnect structure disposed in the one or more dielectric layers, the interconnect structure comprising:

a conductive via, wherein a conductive feature is located below the conductive via in the one or more dielectric layers; and

a conductive line over the conductive via, the conductive line being disposed over and in contact with the horizontal surface of the one or more dielectric layers, the same substance being disposed at the horizontal surface of the one or more dielectric layers, at the vertical surface of the one or more dielectric layers in contact with the conductive line, and at the upper surface of the conductive via at the interface between the conductive via and the conductive fill material of the conductive line,

Wherein more material is provided at the horizontal surface of the one or more dielectric layers and at the interface than at the vertical surface of the one or more dielectric layers,

wherein the sidewall of the conductive via has more residual halide than the interface of the conductive member and the conductive via than the substance.

22. The interconnect structure of claim 21, wherein an upper surface of the conductive via at an interface between the conductive via and the conductive filler material of the wire is convex.

23. The interconnect structure of claim 21, wherein an upper surface of the conductive via at an interface between the conductive via and the conductive filler material of the wire is concave.

24. The interconnect structure of claim 21, wherein there is a crack in the conductive filler material of the conductive line.

25. The interconnect structure of claim 21, further comprising a metal-semiconductor compound located at an interface between the conductive fill material of the conductive line and a surface of the one or more dielectric layers, wherein a metal of the metal-semiconductor compound is the same metal as a metal of the conductive fill material.

26. The interconnect structure of claim 21, further comprising a metal carbide located at an interface between the conductive fill material of the conductive line and a surface of the one or more dielectric layers, wherein a metal of the metal carbide is the same metal as a metal of the conductive fill material.

27. The interconnect structure of claim 21, further comprising a metal alloy at an interface between the conductive fill material of the conductive line and the conductive via.

28. The interconnect structure of claim 21, further comprising a metal compound located at an interface between the conductive fill material of the conductive line and the conductive via.

29. The interconnect structure of claim 21, wherein:

a dielectric surface of the one or more dielectric layers abuts the conductive line; and

the respective concentrations of the species decrease in respective directions from the dielectric surface to the one or more dielectric layers.

30. The interconnect structure of claim 21, further comprising:

a first dielectric diffusion barrier liner along sidewalls of the conductive lines; and

a second dielectric diffusion barrier liner along sidewalls of the conductive via.

31. The interconnect structure of claim 21, wherein no seed layer and no barrier layer are disposed between the conductive via and the conductive line.

32. An interconnect structure, comprising:

a semiconductor substrate;

a first dielectric layer over the semiconductor substrate;

a conductive via extending through the first dielectric layer, the conductive via comprising a first conductive material;

a second dielectric layer over the first dielectric layer; and

a wire extending through the second dielectric layer, the wire comprising a second conductive material, the wire sharing a first interface with the conductive via, the wire sharing a second interface with a horizontal surface of the first dielectric layer, the wire sharing a third interface with a vertical surface of the second dielectric layer, the same substance being disposed at the first, second, and third interfaces, the first and second interfaces having more substance than the third interface, the substance being different from the first and second conductive materials; and

a third dielectric layer between the semiconductor substrate and the first dielectric layer, wherein a conductive feature is located in the third dielectric layer,

33. The interconnect structure of claim 32 wherein the species is argon.

34. The interconnect structure of claim 32 wherein the species is a combination of silicon, germanium, carbon, nitrogen, and argon.

35. The interconnect structure of claim 32 wherein the species is a combination of xenon, argon, hydrogen, and nitrogen.

36. The interconnect structure of claim 32 wherein said species is a combination of argon, neon and xenon.

37. The interconnect structure of claim 32 wherein the species is a combination of boron and argon.

38. An interconnect structure, comprising:

a semiconductor substrate;

a first conductive member located over the semiconductor substrate;

one or more dielectric layers over the first conductive feature;

a first interconnect structure disposed in the one or more dielectric layers, the first interconnect structure including a conductive via and a wire, the conductive via and the wire contacting a horizontal surface of the one or more dielectric layers and a vertical surface of the one or more dielectric layers, the same substance being disposed at the horizontal surface of the one or more dielectric layers and the vertical surface of the one or more dielectric layers; and

A second conductive feature over the first interconnect structure,

wherein the conductive via includes a first conductive material continuously extending between the first conductive member and the conductive line, an

Wherein the wire comprises a second conductive material extending continuously between the conductive via and the second conductive member,

wherein more material is provided at the horizontal surface of the one or more dielectric layers than at the vertical surface of the one or more dielectric layers,

wherein the sidewall of the conductive via has more residual halide than the interface of the first conductive member and the conductive via than the substance.

39. The interconnect structure of claim 38 wherein the species is argon.

40. The interconnect structure of claim 38, wherein the conductive lines are free of cracks.

41. The interconnect structure of claim 38, wherein the conductive line comprises a crack that forms an acute angle with respect to a vertical surface of the one or more dielectric layers, the acute angle being in a range from 30 ° to 60 °.

42. A method for forming an interconnect structure, comprising:

forming an interconnect opening through one or more dielectric layers over a semiconductor substrate, the interconnect opening having a via opening and a trench over the via opening, the via opening exposing a conductive feature, the conductive feature comprising a conductive material;

Performing a cleaning process on the via opening, the cleaning process comprising exposing the conductive member to a chloride or fluoride of the conductive material, wherein residual chloride or fluoride of the conductive material remains in the via opening;

performing a cap recovery process on the via opening, the cap recovery process including exposing the conductive member to a reducing agent;

forming a conductive via in the via opening;

Wherein the sidewall of the conductive via has more residual chloride or fluoride than the interface of the conductive member and the conductive via.

43. The method of claim 42, wherein forming the conductive line comprises conformally depositing a material of the conductive line in the trenches on the one or more exposed dielectric surfaces.

44. The method of claim 42, wherein forming the conductive line does not include depositing a seed layer of material for depositing the conductive line.

45. The method of claim 42 wherein a metal-containing barrier layer is not deposited in the interconnect openings prior to forming the conductive lines.

46. The method of claim 42, further comprising forming a first dielectric liner on a first sidewall of the via opening and a second dielectric liner on a second sidewall of the trench, wherein:

the one or more dielectric layers include an etch stop layer;

the one or more exposed dielectric surfaces include a surface of the etch stop layer;

the via opening passes through the etch stop layer; and

the etch stop layer, the first dielectric liner, and the second dielectric liner form a dielectric diffusion barrier.

47. The method of claim 42, wherein the nucleation enhancement process comprises sputtering.

48. The method of claim 42, wherein the nucleation enhancement process comprises a beam line implantation.

49. The method of claim 42, wherein the nucleation enhancement process comprises a plasma process.

50. The method of claim 42, wherein the nucleation enhancing treatment comprises an ultraviolet treatment.

51. The method of claim 42, wherein the nucleation enhancement process comprises plasma doping.

52. The method of claim 42, wherein the conductive material is tungsten, and wherein the cleaning process comprises a tungsten hexafluoride soak.

53. According toThe method of claim 42, wherein the cap recovery process comprises exposing the conductive member to hydrogen (H ₂ )。

54. An interconnect device, comprising:

a plurality of first wires comprising a first conductive material;

a conductive via on one of the first wires, the conductive via comprising a second conductive material, the conductive via having a convex upper surface; and

a second conductive line on the convex upper surface of the conductive via, the second conductive line including a third conductive material, the third conductive material and the first conductive material each being different from the second conductive material,

Wherein the second conductive line contacts a horizontal surface of one or more dielectric layers above the plurality of first conductive lines and a vertical surface of the one or more dielectric layers, the same substance being disposed at the horizontal surface of the one or more dielectric layers, at an interface between the conductive via and a conductive fill material of the second conductive line, and at the vertical surface of the one or more dielectric layers, wherein more substance is disposed at the horizontal surface of the one or more dielectric layers and at the interface than at the vertical surface of the one or more dielectric layers,

wherein the sidewall of the conductive via has more residual halide than the interface of the first conductive line and the conductive via than the material.

55. The interconnect device of claim 54 wherein the conductive via has vertical sidewalls.

56. The interconnect device of claim 54 wherein the second conductive material is cobalt or ruthenium.

57. The interconnect device of claim 54, wherein the first conductive material and the third conductive material are the same material.

58. The interconnect device of claim 57 wherein the first and third conductive materials are tungsten.

59. The interconnect device of claim 54, further comprising:

a first dielectric layer in which the first conductive line is disposed; and

and a second dielectric layer over the first dielectric layer and the first conductive line, the conductive via and the second conductive line being disposed in the second dielectric layer, the conductive via having sidewalls in the second dielectric layer.

60. The interconnect device of claim 59 wherein the same substance is disposed at an interface between the second conductive line and a horizontal surface of the second dielectric layer and at an interface between the second conductive line and a convex upper surface of the conductive via.

61. The interconnect device of claim 54, further comprising:

a first dielectric diffusion barrier liner along sidewalls of the conductive via; and

a second dielectric diffusion barrier liner along sidewalls of the second conductive line,

wherein no seed layer or barrier layer is disposed between the conductive via and the second wire.

62. The interconnect device of claim 54 wherein the convex upper surface of the conductive via extends into the second wire.

63. An interconnect device, comprising:

A first dielectric layer;

a first interconnect structure in the first dielectric layer, the first interconnect structure comprising a first metal;

a second dielectric layer over the first interconnect structure and the first dielectric layer; and

a second interconnect structure in the second dielectric layer, the second interconnect structure including a conductive line and a conductive via, the conductive via having a vertical sidewall and a convex upper surface, the vertical sidewall of the conductive via extending through the second dielectric layer, the convex upper surface of the conductive via extending into the conductive line, the conductive line including a first metal, the conductive via including a second metal, the second metal being different from the first metal, the second metal of the conductive via extending continuously between the first interconnect structure and the conductive line,

wherein the conductive line contacts a horizontal surface of the second dielectric layer and a vertical surface of the second dielectric layer, the same substance being provided at the horizontal surface of the second dielectric layer, at an interface between the conductive via and a conductive filler of the conductive line, and at the vertical surface of the second dielectric layer, wherein more substance is provided at the horizontal surface of the second dielectric layer and at the interface than at the vertical surface of the second dielectric layer,

Wherein the sidewall of the conductive via has more residual halide than the interface of the first interconnect structure and the conductive via than the material.

64. The interconnect device of claim 63, further comprising:

a third dielectric layer over the second interconnect structure and the second dielectric layer; and

and a third interconnect structure in the third dielectric layer, the third interconnect structure contacting the conductive line.

65. The interconnect device of claim 63 wherein a top surface of the second dielectric layer and a lowest point of a top surface of the conductive line are coplanar.

66. The interconnect device of claim 63 wherein a first substance is disposed at an interface of the conductive line and the conductive via and at an interface of the conductive line and the second dielectric layer.

67. The interconnect device of claim 66, wherein the first species is argon.

68. The interconnect device of claim 66, wherein the first species is disposed in the second dielectric layer, a concentration of the species in the second dielectric layer being greatest at an interface of the conductive line and the second dielectric layer, the concentration of the species in the second dielectric layer decreasing in a direction extending into the second dielectric layer and away from the interface of the conductive line and the second dielectric layer.

69. The interconnect device of claim 63 wherein the first metal is tungsten.

70. The interconnect device of claim 63 wherein the second metal is cobalt or ruthenium.

71. The interconnect device of claim 63 wherein no seed layer is disposed between the first metal of the conductive line and the second metal of the conductive via.

72. An interconnect device, comprising:

a semiconductor substrate including a transistor;

a first dielectric layer over the semiconductor substrate;

a first conductive line in the first dielectric layer, the first conductive line comprising a first conductive material, the first conductive line electrically connected to a transistor of the semiconductor substrate;

a second dielectric layer over the first conductive line and the first dielectric layer;

a conductive via in the second dielectric layer, the conductive via having a convex top surface, the conductive via comprising a second conductive material, the second conductive material being different from the first conductive material; and

a second conductive line in the second dielectric layer, the second conductive line comprising the first conductive material, the second conductive line electrically connected to the first conductive line through the conductive via,

Wherein the second conductive line contacts a horizontal surface of the second dielectric layer and a vertical surface of the second dielectric layer, the same substance being provided at the horizontal surface of the second dielectric layer, at an interface between the conductive via and a conductive filler of the second conductive line, and at the vertical surface of the second dielectric layer, wherein more substance is provided at the horizontal surface of the second dielectric layer and at the interface than at the vertical surface of the second dielectric layer,

73. The interconnect device of claim 72 wherein the second conductive material is cobalt or ruthenium.