CN111180417B - Semiconductor structure, preparation process thereof and semiconductor device - Google Patents
Semiconductor structure, preparation process thereof and semiconductor device Download PDFInfo
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- CN111180417B CN111180417B CN201811345558.8A CN201811345558A CN111180417B CN 111180417 B CN111180417 B CN 111180417B CN 201811345558 A CN201811345558 A CN 201811345558A CN 111180417 B CN111180417 B CN 111180417B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 106
- 238000002360 preparation method Methods 0.000 title abstract description 5
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 117
- 239000010703 silicon Substances 0.000 claims abstract description 117
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 86
- 239000000463 material Substances 0.000 claims abstract description 59
- 230000004888 barrier function Effects 0.000 claims abstract description 57
- 239000004020 conductor Substances 0.000 claims abstract description 43
- 239000010410 layer Substances 0.000 claims description 270
- 229910052751 metal Inorganic materials 0.000 claims description 29
- 239000002184 metal Substances 0.000 claims description 29
- 239000011241 protective layer Substances 0.000 claims description 23
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 18
- 239000010949 copper Substances 0.000 claims description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 10
- 229910052802 copper Inorganic materials 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 10
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 6
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 6
- 238000011049 filling Methods 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical group [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 239000010937 tungsten Substances 0.000 claims description 4
- 238000000034 method Methods 0.000 description 50
- 239000000758 substrate Substances 0.000 description 15
- 238000010586 diagram Methods 0.000 description 12
- 230000000903 blocking effect Effects 0.000 description 8
- DZPJVKXUWVWEAD-UHFFFAOYSA-N [C].[N].[Si] Chemical group [C].[N].[Si] DZPJVKXUWVWEAD-UHFFFAOYSA-N 0.000 description 7
- 238000005498 polishing Methods 0.000 description 7
- 229910004298 SiO 2 Inorganic materials 0.000 description 6
- 230000004048 modification Effects 0.000 description 6
- 238000012986 modification Methods 0.000 description 6
- 238000007792 addition Methods 0.000 description 3
- 238000012217 deletion Methods 0.000 description 3
- 230000037430 deletion Effects 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 3
- 238000007517 polishing process Methods 0.000 description 3
- 238000006467 substitution reaction Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000001125 extrusion Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000008092 positive effect Effects 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
本公开提出一种半导体结构及其制备工艺以及半导体器件。半导体结构包括硅基层、第一氧化物层和第二氧化物层、阻挡层、硅穿孔以及电极。第一氧化物层和第二氧化物层由下至上依序设于硅基层上，第二氧化物层的上表面开设有容纳槽。阻挡层设于第二氧化物层之上，阻挡层的材质硬度大于第二氧化物层的材质硬度。硅穿孔开设于硅基层、第一氧化物层和第二氧化物层并填充有导电材料，硅穿孔的上端显露于容纳槽的槽底。电极设于容纳槽内。
The present disclosure provides a semiconductor structure and a preparation process thereof as well as a semiconductor device. The semiconductor structure includes a silicon-based layer, a first oxide layer, a second oxide layer, a barrier layer, a silicon via and an electrode. The first oxide layer and the second oxide layer are sequentially arranged on the silicon-based layer from bottom to top, and a receiving groove is provided on the upper surface of the second oxide layer. The barrier layer is arranged on the second oxide layer, and the material hardness of the barrier layer is greater than the material hardness of the second oxide layer. The silicon via is opened in the silicon-based layer, the first oxide layer and the second oxide layer and is filled with a conductive material, and the upper end of the silicon via is exposed at the bottom of the receiving groove. The electrode is arranged in the receiving groove.
Description
Technical Field
The disclosure relates to the technical field of through-silicon-via design of semiconductor devices, and in particular relates to a semiconductor structure, a preparation process thereof and a semiconductor device.
Background
The conventional backside via exposure device of through-silicon vias (Through Silicon Via, abbreviated as TSV) is prone to control stability problems of backside mechanochemical polishing process (i.e., process of partially removing metal conductive material used to form electrodes) during its manufacturing process, resulting in metal conductive material disconnection problems during Hybrid bonding (Hybrid bonding) of semiconductor structures.
Disclosure of Invention
It is a primary object of the present disclosure to overcome at least one of the above-mentioned drawbacks of the prior art and to provide a semiconductor structure with improved control stability of the backside polishing process.
Another principal object of the present disclosure is to overcome at least one of the above-described drawbacks of the prior art, and to provide a semiconductor device having the above-described semiconductor structure.
It is yet another principal object of the present disclosure to overcome at least one of the above-mentioned drawbacks of the prior art, and to provide a process for fabricating a semiconductor structure.
In order to achieve the above purpose, the present disclosure adopts the following technical scheme:
According to one aspect of the present disclosure, a semiconductor structure is provided. Wherein the semiconductor structure comprises a silicon base layer, first and second oxide layers, a barrier layer, a through-silicon via, and an electrode. The first oxide layer and the second oxide layer are sequentially arranged on the silicon base layer from bottom to top, and the upper surface of the second oxide layer is provided with a containing groove. The barrier layer is arranged on the second oxide layer, and the material hardness of the barrier layer is greater than that of the second oxide layer. The silicon perforation is arranged on the silicon base layer, the first oxide layer and the second oxide layer and is filled with conductive materials, and the upper end of the silicon perforation is exposed at the bottom of the accommodating groove. The electrode is arranged in the accommodating groove.
According to one embodiment of the disclosure, the material of the second oxide layer is silicon oxide, and the material of the barrier layer is silicon carbon nitrogen.
According to one embodiment of the present disclosure, the conductive material comprises copper or tungsten.
According to one embodiment of the disclosure, the upper end of the through silicon via extends out of the bottom of the accommodating groove and is lower than the notch of the accommodating groove.
According to one embodiment of the present disclosure, the through-silicon via walls are provided with an insulating layer to insulate the through-silicon via from the silicon substrate, the first oxide layer and the second oxide layer.
According to one embodiment of the disclosure, the insulating layer is made of silicon oxide or silicon nitride.
According to one embodiment of the disclosure, the first oxide layer is made of silicon oxide. And/or the material of the second oxide layer is silicon oxide.
According to one embodiment of the present disclosure, the upper surface of the electrode is closer to the silicon-based layer than the upper surface of the barrier layer.
According to one embodiment of the present disclosure, a height difference between an upper surface of the electrode and an upper surface of the barrier layer is 1 to 5 nanometers.
According to one embodiment of the disclosure, the electrode material comprises copper.
According to one embodiment of the disclosure, the semiconductor structure further includes a protective layer disposed between the first oxide layer and the second oxide layer, and the protective layer has a material hardness greater than that of the second oxide layer.
According to one embodiment of the disclosure, the material of the protective layer includes silicon oxynitride and silicon carbide silicon carbon nitrogen.
According to one embodiment of the present disclosure, the protective layer has a bent portion surrounding an outer wall of a portion of the through-silicon via located in the second oxide layer, the bent portion separating the portion of the through-silicon via from the second oxide layer.
According to another aspect of the present disclosure, a semiconductor device is provided. Wherein the semiconductor device comprises the semiconductor structure proposed by the present disclosure and described in the above embodiments.
According to yet another aspect of the present disclosure, a process for fabricating a semiconductor structure is provided. The method comprises the following steps of:
setting a silicon base layer, forming silicon perforations on the lower surface of the silicon base layer and filling conductive materials;
Removing the upper part of the silicon base layer, so that the upper end of the silicon perforation extends out of the upper surface of the silicon base layer;
a first oxide layer is arranged on the upper surface of the silicon base layer, and the upper end of the silicon perforation extends out of the upper surface of the first oxide layer;
Disposing a second oxide layer on an upper surface of the first oxide layer;
a blocking layer is arranged on the upper surface of the second oxide layer, and the material hardness of the blocking layer is greater than that of the second oxide layer;
Patterning the barrier layer and the second oxide layer to form a containing groove together, wherein the upper end of the silicon perforation is exposed at the bottom of the containing groove;
Providing a metal conductive material on the upper surface of the barrier layer and in the receiving groove, and
And removing the metal conductive material arranged on the upper surface of the barrier layer, and filling the metal conductive material in the accommodating groove to form an electrode.
According to the technical scheme, the semiconductor structure, the preparation process thereof and the semiconductor device provided by the disclosure have the advantages and positive effects that:
the semiconductor structure proposed by the present disclosure includes a second oxide layer and a barrier layer. The upper surface of the second oxide layer is provided with a containing groove. The blocking layer is arranged on the second oxide layer, and the material hardness of the blocking layer is greater than that of the second oxide layer. The electrode is arranged in the accommodating groove. Through the design, the barrier layer can be utilized to avoid the problem of control stability in the process of polishing the metal conductive material forming the electrode. In addition, the provision of the barrier layer also enables the bonding capability of the semiconductor structure in a hybrid bonding process to be optimized.
Drawings
Various objects, features and advantages of the present disclosure will become more apparent from the following detailed description of the preferred embodiments of the disclosure, when taken in conjunction with the accompanying drawings. The drawings are merely exemplary illustrations of the present disclosure and are not necessarily drawn to scale. In the drawings, like reference numerals refer to the same or similar parts throughout. Wherein:
Fig. 1 is a schematic diagram of a stacked structure of a semiconductor structure according to an exemplary embodiment;
fig. 2 is a schematic diagram of a stacked structure of a semiconductor structure according to another exemplary embodiment;
Fig. 3 is a schematic diagram of a stacked structure of one of the steps of a process for fabricating a semiconductor structure according to an exemplary embodiment;
fig. 4 is a schematic diagram of a stacked structure of one of the steps of a process for fabricating a semiconductor structure according to an exemplary embodiment;
Fig. 5 is a schematic diagram of a stacked structure of one of the steps of a process for fabricating a semiconductor structure according to an exemplary embodiment;
fig. 6 is a schematic diagram of a stacked structure of one of the steps of a process for fabricating a semiconductor structure according to an exemplary embodiment;
fig. 7 is a schematic view of a stacked structure of one of the steps of a process for fabricating a semiconductor structure according to an exemplary embodiment;
fig. 8 is a schematic diagram of a stacked structure of one of the steps of a process for fabricating a semiconductor structure according to an exemplary embodiment;
fig. 9 is a schematic diagram of a stacked structure of one of the steps of a process for fabricating a semiconductor structure according to an exemplary embodiment;
Fig. 10 is a schematic view of a stacked structure of one of the steps of a process for fabricating a semiconductor structure according to an exemplary embodiment;
Fig. 11 is a schematic diagram of a stacked structure of a semiconductor structure according to still another exemplary embodiment.
The reference numerals are explained as follows:
100. a silicon-based layer;
200. punching silicon;
210. an insulating layer;
310. A first oxide layer;
320. a second oxide layer;
321. a receiving groove;
400. A protective layer;
500. An electrode;
510. a seed layer;
600. A barrier layer;
H. And (3) height difference.
Detailed Description
Exemplary embodiments that embody features and advantages of the present disclosure are described in detail in the following description. It will be understood that the present disclosure is capable of various modifications in the various embodiments, all without departing from the scope of the present disclosure, and that the description and drawings are intended to be illustrative in nature and not to be limiting of the present disclosure.
In the following description of various exemplary embodiments of the present disclosure, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration various exemplary structures, systems, and steps in which aspects of the present disclosure may be practiced. It is to be understood that other specific arrangements of parts, structures, example devices, systems, and steps may be used, and structural and functional modifications may be made without departing from the scope of the present disclosure. Moreover, although the terms "over," "between," "within," and the like may be used in this specification to describe various exemplary features and elements of the disclosure, these terms are used herein for convenience only, e.g., in accordance with the directions of the examples depicted in the drawings. Nothing in this specification should be construed as requiring a particular three-dimensional orientation of structures to fall within the scope of this disclosure.
Embodiment of semiconductor Structure
Referring to fig. 1, a schematic diagram of a stacked structure of a semiconductor structure proposed by the present disclosure is representatively illustrated. In this exemplary embodiment, the semiconductor structure proposed in the present disclosure is described taking a through silicon via structure applied to a semiconductor display as an example. Those skilled in the art will readily appreciate that many modifications, additions, substitutions, deletions, or other changes may be made to the specific embodiments described below for use in other types of semiconductor devices or other processes, which remain within the principles of the semiconductor structures set forth in the present disclosure.
As shown in fig. 1, in the present embodiment, the semiconductor structure proposed in the present disclosure mainly includes a silicon base layer 100, first and second oxide layers 310 and 320, a barrier layer 600, a through-silicon via 200, and an electrode 500. Specifically, the first oxide layer 310 and the second oxide layer 320 are sequentially disposed on the silicon substrate 100 from bottom to top, and the accommodating groove 321 is formed on the upper surface of the second oxide layer 320. The barrier layer 600 is disposed on the upper surface of the second oxide layer 320, and the material hardness of the barrier layer is greater than that of the second oxide layer. The through-silicon-via 200 is formed in the above-mentioned stacked structure and sequentially penetrates through the silicon base layer 100, the first oxide layer 310 and a portion of the second oxide layer 320, and the through-silicon-via 200 is filled with a conductive material. The upper end of the through-silicon via 200 is exposed on the lower surface of the silicon substrate 100, and the lower end of the through-silicon via 200 is exposed on the bottom of the accommodating groove 321. The electrode 500 is disposed at the bottom of the receiving groove 321 of the second oxide layer 320 and fills the receiving groove 321. Through the above design, the present disclosure can avoid the control stability problem in polishing the metal conductive material forming the electrode 500 using the barrier layer 600. In addition, the provision of the barrier layer 600 also enables the bonding capability of the semiconductor structure in a hybrid bonding process to be optimized.
Further, in the present embodiment, the conductive material filled in the through-silicon vias 200 may preferably include copper (Cu) or tungsten (W). In other embodiments, the through-silicon-via 200 may be filled with other related integrated circuit conductive materials, which is not limited to this embodiment.
Further, as shown in fig. 1, in the present embodiment, the upper end of the through-silicon-via 200 may preferably protrude from the bottom of the receiving groove 321 and be lower than the notch of the receiving groove 321. Accordingly, the conductive material of the through-silicon-via 200 can have a larger contact area with the metal conductive material forming the electrode 500, further reducing the resistance. In other embodiments, the upper end of the through silicon via 200 may be flush with the bottom of the accommodating groove 321, which is not limited to this embodiment.
Further, as shown in fig. 1, in the present embodiment, an insulating layer 210 may be preferably provided at the wall of the through-silicon via 200 to insulate the through-silicon via 200 from the silicon substrate 100, the first oxide layer 310, the barrier layer 600, and the second oxide layer 320.
Further, based on the design that the insulating layer 210 is disposed at the hole wall of the through-silicon via 200, in this embodiment, the material of the insulating layer 210 may be silicon oxide (SiO 2) or silicon nitride (Si 3N4). In other embodiments, the material of the insulating layer 210 may be selected from other related insulating materials of the integrated circuit, which is not limited to this embodiment.
Further, in this embodiment, the material of the first oxide layer 310 may preferably include silicon oxide (SiO 2). In other embodiments, the material of the first oxide layer 310 may also be selected from other related oxide materials of the integrated circuit, which is not limited to this embodiment.
Further, in the present embodiment, the material of the second oxide layer 320 may preferably include silicon oxide (SiO 2). In other embodiments, the material of the second oxide layer 320 may be selected from other related oxide materials of the integrated circuit, which is not limited to this embodiment.
Still further, based on the design that the material of the second oxide layer 320 includes silicon oxide, in this embodiment, the material of the barrier layer 600 may preferably include silicon carbon nitrogen (SiCN). In which silicon carbon nitrogen has a hardness greater than that of silicon oxide, and thus can avoid the problem of control stability during polishing of the metal conductive material forming the electrode 500. In addition, in the hybrid bonding process of the two semiconductor structures, the barrier layers 600 made of silicon carbon nitrogen materials are bonded relatively, and the density of silicon carbon nitrogen is greater than that of silicon oxide, so that the bonding capability of the semiconductor structures in the hybrid bonding process can be optimized.
Further, as shown in fig. 1, in the present embodiment, the upper surface of the electrode 500 may preferably be closer to the silicon base layer 100 than the upper surface of the second oxide layer 320, i.e., the upper surface of the electrode 500 is submerged with respect to the upper surface of the second oxide layer 320, there is a height difference H between the upper surface of the electrode 500 and the upper surface of the second oxide layer 320. Accordingly, in the process of bonding the electrode 500 at a high temperature in the hybrid bonding process, a reserved space can be reserved for the metal conductive material of the electrode 500 to expand due to heating, so that the metal conductive material is prevented from overflowing.
Still further, based on the design that the upper surface of the electrode 500 is closer to the silicon base layer 100 than the upper surface of the second oxide layer 320, in this embodiment, the height difference H between the upper surface of the electrode 500 and the upper surface of the second oxide layer 320 may be more preferably 1nm to 5 nm (i.e., 1nm,1 nm=1×10 -9 m). In other embodiments, the height difference H between the upper surface of the electrode 500 and the upper surface of the second oxide layer 320 may be other dimensions, which is not limited in this embodiment.
In addition, as shown in fig. 1, because the upper surface of the electrode 500 is closer to the silicon base layer 100 than the upper surface of the second oxide layer 320, in this embodiment, the upper surface of the electrode 500 is a plane, and thus the upper surface of the electrode 500 is a sinking platform structure after sinking relative to the upper surface of the second oxide layer 320. In other embodiments, the design of the present disclosure regarding "the upper surface of the electrode 500 is closer to the silicon base layer 100 than the upper surface of the second oxide layer 320" may be implemented in other ways.
For example, as shown in fig. 2, a schematic diagram of a stacked structure of another embodiment of the semiconductor structure proposed by the present disclosure is representatively illustrated in fig. 2. In this embodiment, the upper surface of the electrode 500 and the upper surface of the second oxide layer 320 actually form together a smoothly sinking curved structure. Further, the curved surface structure may be a sunken arc curved surface, a sunken elliptical arc curved surface or an irregular curved surface with any whole sunken form, which is not limited by the embodiment.
It should be noted that, in the present embodiment, the material of the electrode 500 is exemplified by copper, so that the semiconductor structure proposed in the present disclosure has the effect of blocking the extrusion of copper generated by the electrode 500 on the second oxide layer 320 into the silicon base layer 100. In other embodiments, the material of the electrode 500 may be selected from other metal conductive materials required for forming electrodes of other related integrated circuits, and the semiconductor structure proposed in the present disclosure may have the effect of blocking any metal generated by the electrode 500 on the second oxide layer 320 from extruding into the silicon base layer 100.
In the description of the present specification, the terms "upper" and "lower" with respect to each laminated structure are merely with respect to the directions shown in the drawings. The spatial location of the semiconductor structure proposed by the present disclosure in a variety of specific application scenarios is not limited. For example, in a process of hybrid bonding two semiconductor structures, so-called "upper surfaces" of the second oxide layers 320 of the two semiconductor structures are disposed opposite to each other.
Semiconductor structure embodiment two
Referring to fig. 11, a schematic diagram of a stacked structure of another embodiment of a semiconductor structure proposed by the present disclosure is representatively illustrated. In this exemplary embodiment, the semiconductor structure proposed in the present disclosure is substantially the same as that in the first embodiment, and the main differences between the two will be described below.
As shown in fig. 11, in the present embodiment, a protective layer 400 is disposed between the first oxide layer 310 and the second oxide layer 320, and the material hardness of the protective layer 400 is greater than the material hardness of the second oxide layer 320. The through-silicon-via 200 is formed in the above-mentioned stacked structure and penetrates the silicon base layer 100, the first oxide layer 310, the protection layer 400 and a portion of the second oxide layer 320 in order. With the above design, since the material hardness of the protection layer 400 is greater than that of the second oxide layer 320, the present disclosure can prevent copper generated by the electrode 500 on the second oxide layer 320 from extruding into the silicon substrate 100 by using the protection layer 400, so as to avoid short-circuiting between the through-silicon vias 200. In addition, since the protective layer 400 is sandwiched between two oxide layers, the stress state of the protective layer 400 is optimized.
Further, in the present embodiment, the material of the protective layer may preferably include silicon oxynitride (SiON), silicon carbide (SiN), or silicon carbon nitride (SiCN). In other embodiments, the material of the protection layer may be other materials with hardness greater than that of the second oxide layer 320, which is not limited in this embodiment.
In addition, in other embodiments, the protective layer may preferably have a bent portion surrounding an outer wall of a portion of the through-silicon via located in the second oxide layer, the bent portion separating the portion of the through-silicon via from the second oxide layer.
Further, as shown in fig. 11, in the present embodiment, an insulating layer 210 may be preferably provided at the wall of the through-silicon via 200 to insulate the through-silicon via 200 from the silicon substrate 100, the first oxide layer 310, the protective layer 400, and the second oxide layer 320.
It should be noted herein that the semiconductor structures shown in the drawings and described in this specification are only a few examples of the wide variety of semiconductor structures that can employ the principles of the present disclosure. It should be clearly understood that the principles of the present disclosure are in no way limited to any of the details of the semiconductor structure or any of the components of the semiconductor structure shown in the drawings or described in the present specification.
Semiconductor device embodiment
Based on the above-described exemplary description of the semiconductor structure proposed by the present disclosure, exemplary embodiments of the semiconductor device proposed by the present disclosure will be described below. In this embodiment mode, a semiconductor device having a through-silicon via structure is described as an example. Those skilled in the art will readily appreciate that many modifications, additions, substitutions, deletions, or other changes may be made to the embodiments described below for use in other types of electronic devices or other processes, which remain within the principles of the semiconductor devices set forth in the present disclosure.
In the present embodiment, the semiconductor device proposed by the present disclosure includes the semiconductor structure proposed by the present disclosure and described in detail in the above embodiment.
It should be noted herein that the semiconductor device shown in the drawings and described in this specification is merely one example of the many kinds of semiconductor devices that can employ the principles of the present disclosure. It should be clearly understood that the principles of the present disclosure are in no way limited to any of the details of the semiconductor device or any of the components of the semiconductor device shown in the drawings or described in the present specification.
Process embodiment for preparing semiconductor structure
Referring to fig. 3 through 10, each of which representatively illustrates a schematic view of a stacked structure in several main processes of the fabrication process of the semiconductor structure proposed in the present disclosure. In this exemplary embodiment, the manufacturing process of the semiconductor structure proposed in the present disclosure is described taking as an example a through-silicon via structure applied to a semiconductor device. Those skilled in the art will readily appreciate that many modifications, additions, substitutions, deletions, or other changes may be made to the specific embodiments described below in order to apply the relevant designs of the present disclosure to other types of semiconductor devices or other processes, which remain within the principles of the fabrication process of the semiconductor structures set forth in the present disclosure.
As shown in fig. 3 to 10, in the present embodiment, the manufacturing process of the semiconductor structure provided in the present disclosure mainly includes the following steps:
A silicon base layer 100 is provided, a through silicon via 200 is provided on the lower surface of the silicon base layer 100, and a conductive material is filled in the through silicon via 200. The lower end of the through silicon via 200 is exposed on the lower surface of the silicon substrate 100, and the upper end is coated in the silicon substrate 100.
Removing the upper portion of the silicon base layer 100 such that the upper ends of the through-silicon vias 200 protrude from the upper surface of the silicon base layer 100;
A first oxide layer 310 is arranged on the upper surface of the silicon substrate 100, the upper end of the through silicon via 200 is coated in the first oxide layer 310, and then the upper surface of the first oxide layer 310 is ground, so that the upper end of the through silicon via 200 extends out of the upper surface of the first oxide layer 310;
A second oxide layer 320 is disposed on the upper surface of the first oxide layer 310, and the upper end of the through silicon via 200 is wrapped in the second oxide layer 320;
Providing a barrier layer 600 on the upper surface of the second oxide layer 320, wherein the material hardness of the barrier layer 600 is greater than that of the second oxide layer 320;
Patterning the barrier layer 600 and the second oxide layer 320 such that the barrier layer 600 and the second oxide layer 320 together form a receiving groove 321 and the upper end of the through-silicon-via 200 is exposed at the bottom of the receiving groove 321, and
The metal conductive material is disposed on the upper surface of the barrier layer 600, the receiving groove 321 is also filled with the metal conductive material, and then the metal conductive material is ground, the metal conductive material disposed on the upper surface of the barrier layer 600 is removed, and the metal conductive material filled in the receiving groove 321 is remained, thereby forming an electrode.
The above main steps of the manufacturing process of the semiconductor structure proposed in the present disclosure will be specifically described below with reference to fig. 3 to 10.
Preferably, as shown in fig. 3, in the step of disposing the through-silicon via 200 and the silicon substrate 100, the through-silicon via 200 is disposed on a surface of the silicon substrate 100, and one end of the through-silicon via 200 is exposed on a surface of the silicon substrate 100, wherein the end of the through-silicon via 200 is a lower end, and the surface of the silicon substrate 100 is a lower surface. In addition, the arrangement of the through-silicon-vias 200 further includes filling the conductive material and disposing the insulating layer 210, which is not described herein. Then, as shown in fig. 4, the upper portion of the silicon base layer 100 is removed, so that the other end of the through-silicon via 200 protrudes from the other surface of the silicon base layer 100, wherein the other end of the through-silicon via 200 is the upper end, and the other surface of the silicon base layer 100 is the upper surface.
Further, in the present embodiment, the conductive material filled in the through-silicon vias 200 may preferably include copper (Cu) or tungsten (W). In other embodiments, the through-silicon-via 200 may be filled with other related integrated circuit conductive materials, which is not limited to this embodiment.
Further, in the present embodiment, the material of the insulating layer 210 may be preferably silicon oxide (SiO 2) or silicon nitride (Si 3N4). In other embodiments, the material of the insulating layer 210 may be selected from other related insulating materials of the integrated circuit, which is not limited to this embodiment.
Further, in the present embodiment, the process of partially removing the silicon-based layer 100 may preferably employ a polishing (polishing) process.
Preferably, as shown in fig. 5, in the present embodiment, for the step of disposing the first oxide layer 310, first, the first oxide layer 310 is disposed on the upper surface of the silicon substrate 100, and then the upper end of the through-silicon-via 200 is wrapped in the first oxide layer 310. Then, as shown in fig. 6, the upper portion of the first oxide layer 310 is removed, so that the upper end of the through-silicon-via 200 protrudes from the upper surface of the first oxide layer 310.
Further, in this embodiment, the material of the first oxide layer 310 may preferably include silicon oxide (SiO 2). In other embodiments, the material of the first oxide layer 310 may also be selected from other related oxide materials of the integrated circuit, which is not limited to this embodiment.
Further, in the present embodiment, the disposing process of the first oxide layer 310 on the upper surface of the silicon substrate 100 may preferably employ a deposition (deposition) process.
Further, in the present embodiment, the process of partially removing the first oxide layer 310 may preferably employ a Chemical Mechanical Polishing (CMP) process.
Preferably, as shown in fig. 7, in the present embodiment, for the step of disposing the second oxide layer 320, the second oxide layer 320 is disposed on the upper surface of the first oxide layer 310.
Further, in the present embodiment, the material of the second oxide layer 320 may preferably include silicon oxide (SiO 2). In other embodiments, the material of the second oxide layer 320 may be selected from other related oxide materials of the integrated circuit, which is not limited to this embodiment.
Further, in this embodiment, a deposition process may be preferably used for the disposing process of the second oxide layer 320 on the upper surface of the first oxide layer 310.
Preferably, as shown in fig. 8, in the present embodiment, for the step of disposing the barrier layer 600, the barrier layer 600 is disposed on the upper surface of the second oxide layer 320.
Further, in the present embodiment, based on the design that the material of the second oxide layer 320 includes silicon oxide, the material of the barrier layer 600 may preferably include silicon carbon nitrogen (SiCN).
Further, in the present embodiment, the disposing process of the barrier layer 600 may preferably employ a deposition process.
Preferably, as shown in fig. 9, in the step of forming the accommodating groove 321, the barrier layer 600 and the second oxide layer 320 are subjected to patterning treatment so that the barrier layer 600 and the second oxide layer 320 together form the accommodating groove 321.
Further, in the present embodiment, the process of patterning the barrier layer 600 and the second oxide layer 320 to form the accommodating groove 321 may preferably employ a photolithography (lithographic) or etching (etch) process.
Further, in the present embodiment, the receiving groove 321 may be formed such that the upper end of the through-silicon-via 200 protrudes from the bottom of the receiving groove 321 and is lower than the notch of the receiving groove 321.
Further, as shown in fig. 9, in the present embodiment, the accommodating groove 321 may be preferably formed such that the upper end of the through-silicon-via 200 protrudes from the bottom of the accommodating groove 321 and is lower than the notch of the accommodating groove 321.
Preferably, as shown in fig. 10, in the present embodiment, for the step of disposing the electrode 500, first, a metal conductive material (e.g., copper) is disposed on the upper surface of the barrier layer 600 while the accommodating groove 321 is filled with the metal conductive material. Then, as shown in fig. 1, the metal conductive material not filled in the receiving groove 321, i.e., a portion of the metal conductive material located on the upper surface of the barrier layer 600 is removed, thereby forming the electrode 500 filled in the receiving groove 321.
Further, in the present embodiment, a process of disposing a metal conductive material on an upper surface of the barrier layer and filling the receiving groove 321 may preferably employ a plating process.
Further, in the present embodiment, the process of partially removing the metal conductive material may preferably employ a chemical mechanical polishing process.
Further, as shown in fig. 10, in the step of disposing the electrode 500, it may be preferable to dispose a seed layer 510 on the upper surface of the barrier layer 600 (including the bottom of the accommodating groove 321 and the groove walls), and then dispose the above-mentioned metal conductive material on the seed layer 510 to form the electrode 500. Among them, the disposing process of the seed layer 510 may preferably employ a sputtering process.
Further, as shown in fig. 1, in the present embodiment, after forming the electrode 500, it may be also preferable to partially remove the upper portion of the electrode 500 (or to simultaneously remove the barrier layer 600 and the second oxide layer 320 adjacently disposed on the upper portion of the electrode 500, refer to fig. 2), so that the upper surface of the electrode 500 is closer to the silicon base layer 100 than the upper surface of the barrier layer 600.
As shown in fig. 11, in another embodiment, the fabrication process of the semiconductor structure according to the present disclosure may further include a step of disposing the protective layer 400 between the first oxide layer 310 and the second oxide layer 320 by using a material having a material hardness greater than that of the second oxide layer 320. Specifically, in the step of disposing the protective layer 400, the protective layer 400 is disposed on the upper surface of the first oxide layer 310 after disposing the first oxide layer 310, and the material hardness of the protective layer 400 is greater than the material hardness of the second oxide layer 320. . On the basis of this, the second oxide layer 320 is disposed on the upper surface of the protective layer 400.
Further, in this alternative embodiment, the material of the protection layer 400 may preferably include silicon oxynitride (SiON), silicon carbide (SiN), or silicon carbon nitride (SiCN). In other embodiments, the material of the protection layer may be other materials with hardness greater than that of the second oxide layer 320, which is not limited in this embodiment.
Further, in this other embodiment, the process of disposing the protective layer 400 on the upper surface of the first oxide layer 310 may preferably employ a deposition process.
In addition, in the other present embodiment, since the protective layer completely covers the upper end of the through-silicon via protruding from the first oxide layer, after the accommodating groove is opened, the protective layer surrounding the outer wall of the portion of the through-silicon via located in the second oxide layer forms a bent portion that separates the portion of the through-silicon via from the second oxide layer.
It should be noted herein that the fabrication processes of the semiconductor structures shown in the drawings and described in the present specification are merely a few examples of the many types of semiconductor structures that can employ the principles of the present disclosure. It should be clearly understood that the principles of the present disclosure are in no way limited to any details or any steps of the fabrication process of the semiconductor structure shown in the drawings or described in the present specification.
In summary, the semiconductor structure provided in the present disclosure includes a second oxide layer and a barrier layer. The upper surface of the second oxide layer is provided with a containing groove. The blocking layer is arranged on the second oxide layer, and the material hardness of the blocking layer is greater than that of the second oxide layer. The electrode is arranged in the accommodating groove. Through the design, the barrier layer can be utilized to avoid the problem of control stability in the process of polishing the metal conductive material forming the electrode. In addition, the provision of the barrier layer also enables the bonding capability of the semiconductor structure in a hybrid bonding process to be optimized.
The foregoing describes and/or illustrates in detail one semiconductor structure and process for making the same, and exemplary embodiments of a semiconductor device, as set forth in the present disclosure. Embodiments of the present disclosure are not limited to the specific embodiments described herein, but rather, components and/or steps of each embodiment may be utilized independently and separately from other components and/or steps described herein. Each component and/or each step of one embodiment may also be used in combination with other components and/or steps of other embodiments. When introducing elements/components/etc. that are described and/or illustrated herein, the terms "a," "an," and "the" are intended to mean that there are one or more of the elements/components/etc. The terms "comprising," "including," and "having" are intended to be inclusive and mean that there may be additional elements/components/etc., in addition to the listed elements/components/etc. Furthermore, the terms "first" and "second" and the like in the claims and in the description are used for descriptive purposes only and not for numerical limitation of their subject matter.
While the disclosure has been described in terms of various specific embodiments, a semiconductor structure and process for making the same, as well as a semiconductor device, those skilled in the art will recognize that the disclosure can be practiced with modification within the spirit and scope of the claims.
Claims (14)
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