CN111210860B - A Tri-state Content Addressable Memory Based on 3D MOS Devices - Google Patents
A Tri-state Content Addressable Memory Based on 3D MOS Devices Download PDFInfo
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- 230000015654 memory Effects 0.000 title claims abstract description 103
- 229910052751 metal Inorganic materials 0.000 claims abstract description 35
- 239000002184 metal Substances 0.000 claims abstract description 35
- 239000004065 semiconductor Substances 0.000 claims abstract description 31
- 230000000295 complement effect Effects 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 34
- 230000008569 process Effects 0.000 claims description 20
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium oxide Inorganic materials O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 claims description 12
- PVADDRMAFCOOPC-UHFFFAOYSA-N oxogermanium Chemical compound [Ge]=O PVADDRMAFCOOPC-UHFFFAOYSA-N 0.000 claims description 12
- 238000003860 storage Methods 0.000 claims description 11
- 230000006870 function Effects 0.000 claims description 6
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 6
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- 230000000694 effects Effects 0.000 claims description 5
- 229910052732 germanium Inorganic materials 0.000 claims description 5
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 5
- 230000006386 memory function Effects 0.000 claims description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 3
- 230000007704 transition Effects 0.000 claims 1
- 238000005516 engineering process Methods 0.000 abstract description 4
- 238000002360 preparation method Methods 0.000 abstract description 3
- 238000013461 design Methods 0.000 abstract description 2
- 238000011161 development Methods 0.000 abstract description 2
- 238000005265 energy consumption Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 14
- 239000001301 oxygen Substances 0.000 description 8
- 229910052760 oxygen Inorganic materials 0.000 description 8
- -1 oxygen ions Chemical class 0.000 description 8
- 239000000463 material Substances 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 238000004088 simulation Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 230000006399 behavior Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
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Abstract
本发明公开了一种基于3D MOS器件的三态内容可寻址存储器，该3D MOS器件由依次接触的金属层、记忆层、整流层和半导体层构成，各层沿不同方向搭建，形成一个三维立体结构；该三态内容可寻址存储器由若干存储单元呈阵列排列构成，同一行的所有存储单元连接同一匹配线，同一列的所有存储单元连接同一对互补的信号搜索线。通过对不同时钟周期内所有信号搜索线和匹配线上电压大小进行设定，可以改变一行或一列3D MOS器件的开关状态，完成数据写入。本发明采用非易失性存储器技术，具有能耗低和体积小等优点；本发明存储器单元结构简单，可以有效降低电路和版图设计成本，简化制备工艺；与传统CMOS工艺兼容，对于存储技术和存储器的发展有重要的意义。
The invention discloses a three-state content addressable memory based on a 3D MOS device. The 3D MOS device is composed of a metal layer, a memory layer, a rectifier layer and a semiconductor layer that are in contact with each other in sequence, and each layer is constructed in different directions to form a three-dimensional Three-dimensional structure; the three-state content addressable memory is composed of a plurality of memory cells arranged in an array, all memory cells in the same row are connected to the same matching line, and all memory cells in the same column are connected to the same pair of complementary signal search lines. By setting the voltages on all signal search lines and matching lines in different clock cycles, the switching states of a row or column of 3D MOS devices can be changed to complete data writing. The present invention adopts non-volatile memory technology, and has the advantages of low energy consumption and small size; the memory cell structure of the present invention is simple, which can effectively reduce the cost of circuit and layout design, and simplify the preparation process; The development of memory is of great significance.
Description
Technical Field
The invention belongs to the field of semiconductors and integrated circuits, and particularly relates to a high-density low-power-consumption tri-state content addressable memory based on a 3D MOS device with memristor and rectifying characteristics.
Background
Ternary Content Addressable Memories (TCAMs) have evolved from Content Addressable Memories (CAMs). The content addressable memory is a high-speed hardware search engine, and has the greatest characteristic that the stored content can be used as a key word to perform a search operation, specifically, data which is expected to be searched is input, the address where the data is stored is returned after the search, and a matching signal is used for indicating whether the search is successful or not.
The general content addressable memory has only two states of each bit, 0 or 1, and the ternary content addressable memory has three states of each bit, except 0 and 1, and one state of don't care, so it is called "ternary". It is the third state of the tri-state CAM that enables both exact and fuzzy match lookup, whereas the CAM has no third state and therefore only exact match lookup.
At the core node of the router, the routing table is the most important concept, in which the routing path that the router should select according to the destination IP in the packet is stored, and this is a lookup operation for finding the content according to the content as described above. The traditional searching methods are many, and mainly include a wired searching method, a binary tree searching method, a hash table searching method and the like. The searching methods are software searching methods based on Static Random Access Memory (SRAM), and have the common characteristics of low searching speed and low efficiency. Although there are many optimization schemes for these search methods, the high-speed search requirement of high-speed real-time communication systems in new situation cannot be satisfied fundamentally.
The TCAM search method based on hardware is provided under the background, when the method is used for searching, all data in the whole table are inquired at the same time, the search speed is not influenced by the size of the table item space data, the search is completed once in each clock period, and the average search speed is far faster than the search based on the SRAM algorithm. If the TCAM mode is used to address the contents of the routing table and the Access Control List (ACL) in the router and the three-layer switch, the effect is obvious for improving the network transmission speed and the network performance, and the possibility is provided for providing a novel network transmission protocol under the high-speed condition.
Although the nonvolatile ternary content memory cell based on a Static Random Access Memory (SRAM), a Magnetic Random Access Memory (MRAM) and a Phase Change Memory (PCM) is realized at present, the structure is complex, the preparation process is not completely compatible with a standard CMOS process, and the nonvolatile ternary content memory cell has many defects such as power consumption, area, adjacent cell interference and the like.
Disclosure of Invention
The invention aims to realize a 3D MOS element with I-V characteristics different from a traditional memristor by utilizing the special rectification characteristics and impedance characteristics of an oxide layer formed by hafnium oxide and germanium oxide. By further utilizing the element, a novel ternary content addressable memory is realized, the performance of the ternary content addressable memory can be improved, the unit structure of the ternary content addressable memory is simplified, and a foundation is provided for wide application of hardware addressing at a router node.
The purpose of the invention is realized by the following technical scheme: A3D MOS device with memristor and rectification characteristics comprises a metal layer, a memory layer, a rectification layer and a semiconductor layer which are sequentially contacted, wherein each layer is built along different directions to form a three-dimensional structure; wherein the memory layer and the rectifying layer are realized by an oxide layer in the MOS structure; the semiconductor layer is made of germanium; the memory function of the memory layer is realized by hafnium oxide, and the rectification function of the rectification layer is realized by the cooperation of germanium oxide and aluminum oxide.
Further, the metal layer is made of titanium nitride or metal nickel, and the metal layers of different devices are isolated by oxide.
Further, the device is built in the form of a spatial cylinder; each concentric ring is sequentially provided with a metal layer, a memory layer, a rectifying layer and a semiconductor layer from outside to inside; when the device works, because the perimeter of the outer layer material is larger than that of the inner layer material, oxygen ions are gathered when moving, and the impedance characteristic and the rectification effect can be improved.
Furthermore, a 3D structure formed by a plurality of the devices is built in a layer stacking mode in different directions; the semiconductor layers of the plurality of devices are parallel to each other and built on an oxide substrate; the oxide layer and the metal layer are vertical to the oxide substrate and wrap the stacked semiconductor layers from the side; all devices share the same oxide layer and metal layer; this 3D structure is effectual has promoted space utilization efficiency.
Further, after the Forming process of the device, a filament path will be formed in the hafnium oxide layer from which oxygen ions drift into the germanium oxide layer that is devoid of oxygen ions; in the absence of the germanium oxide layer, there are no sites for storing oxygen ions and therefore no impedance switching behavior is observed; in addition, the conduction band offset (0.4-0.8eV) between the germanium oxide layer and the semiconductor layer is much smaller than the valence band offset (2.3-4.3eV), so that the forward conduction current is much larger than the reverse conduction current in the germanium oxide layer and the semiconductor layer (N-type highly doped Ge layer), thereby improving the rectification characteristic of the MOS device.
Further, applying corresponding voltage between the device metal layer and the semiconductor layer, thereby realizing the conversion of the device between an off state and an on state;
the device in the off state is in the off state, the resistance is suddenly reduced after negative voltage is applied to the metal layer, the process is called SET, the device is converted from the off state to the on state, the device has the characteristics of a diode which is conducted from the metal layer to the semiconductor layer and is cut off in the reverse direction, and the device can be used as a conventional diode device;
in the on-state device, after a forward voltage is applied to the metal layer, the resistance is suddenly increased, the process is called RESET, the device is turned from the on-state to the off-state, and the device is cut off in two directions and can be regarded as a resistor with high resistance.
A three-state content addressable memory based on a 3D MOS device with memristor and rectification characteristics is further composed of a plurality of memory units with memory, read-write and comparison functions in an array arrangement mode; all the memory cells in the same row are connected with the same matched line, and all the memory cells in the same column are connected with the same pair of complementary signal search lines; each memory cell comprises two 3D MOS devices; the metal layers of the two MOS devices are directly connected and connected with the same matched line; the semiconductor layers of the two MOS devices are respectively connected with a pair of complementary signal search lines.
Furthermore, the material of the match line is a metal material connected with the device metal layer, including but not limited to copper, aluminum, tungsten; the signal search line is made of germanium and is connected with a semiconductor layer of the device.
Further, the first device and the second device in the memory cell cooperate with each other to store three logic states of [0], [1], and [ don't care ]: when the first device is in an off state and the second device is in an on state, the memory cell stores a data bit [0 ]; when the first device is in an on state and the second device is in an off state, the memory cell stores a data bit [1 ]; when both the first device and the second device are in the off state, the memory cell is in a don't care (don't care) state.
Further, before the search operation starts, the match line needs to be precharged to the level corresponding to [1 ]; in the searching process, when the storage data of the storage unit is consistent with the searching signal, the storage unit is in a matching state (match), and when all the storage units on the same matchline are in the matching state (match), the matchline outputs a precharge result [1 ]; the match line outputs [0] when the memory cell stores data that is not consistent with the search signal, which is a mismatch state (mismatch), and when one or more memory cells on the same match line are in a mismatch state (mismatch).
Further, the writing mode of the tri-state content addressable memory is as follows: by setting the voltage of all the signal search lines and the voltage of the match lines in different clock cycles, the switching state of a column of 3D MOS devices directly connected with a single signal search line or the switching state of a row of 3D MOS devices directly connected with a single match line can be changed.
Further, before the row-wise write starts, three match line levels (high, medium, low) and two signal search line levels (high, low) are selected and the following requirements are satisfied: the match line level and the signal search line level have 6 voltage combinations, wherein the combination of the high match line level and the low signal search line level enables the device to be turned off, the combination of the low match line level and the high signal search line level enables the device to be turned on, and the other four combinations enable the device to keep the original state; in the writing process, the match line of an irrelevant row is set to be the level of a middle match line; in a row to be written, the level of a signal search line connected with a device to be turned off is set to be low, the level of a signal search line connected with a device to be turned on is set to be high, and a match line of the row to be written performs voltage scanning from the level of a low match line to the level of a high match line.
Further, before the column-wise write begins, two matchline levels (high, low) and three signal search line levels (high, medium, low) are selected and the following requirements are met: the match line level and the signal search line level have 6 voltage combinations, wherein the combination of the high match line level and the low signal search line level enables the device to be turned off, the combination of the low match line level and the high signal search line level enables the device to be turned on, and the other four combinations enable the device to keep the original state; in the writing process, setting a signal search line of an irrelevant column as a medium signal search line level; in the column to be written, the level of a matched line connected with a device to be turned off is set as a high matched line level, the level of a matched line connected with a device to be turned on is set as a low matched line level, and a signal search line of the column to be written performs voltage scanning from the low signal search line level to the high signal search line level.
The invention has the beneficial effects that: the invention adopts the nonvolatile memory technology, has the advantages of high performance, low energy consumption, small volume and the like, and has important significance for improving the performance of data intensive application; especially, on the premise of integrating the advantages, the application of the technology to the key nodes of the network can greatly improve the router searching efficiency; the tri-state content addressable memory unit has a simple structure, can effectively reduce the design cost of a circuit level and a layout level, and simplifies the preparation process; the invention is different from other modes for realizing the three-state content addressable memory, mainly shows that the invention is compatible with the traditional CMOS process, avoids more complicated production procedures, and has important significance for the development of nonvolatile storage technology and the three-state content addressable memory.
Drawings
FIG. 1 is a schematic structural diagram of a three-state content addressable memory based on a 3D MOS device with both memristive and rectifying characteristics according to the present invention;
FIG. 2 is a current-voltage characteristic diagram of a 3D MOS device with both memristive and rectifying characteristics according to the present invention;
FIG. 3a is a schematic diagram of a 3D MOS device according to one embodiment of the present invention;
FIG. 3b is a schematic structural diagram of another 3D MOS device of the present invention;
FIG. 4 is a circuit diagram of a memory cell of the present invention;
FIG. 5 is a circuit diagram illustrating the data matching result obtained according to the embodiment of the present invention;
FIG. 6 is a schematic diagram of the voltage settings for row-wise writing of the device array;
FIG. 7 is a schematic diagram of the voltage set up for column-wise writing of an array of devices;
fig. 8 is a functional simulation result for the TCAM array described above.
Detailed Description
The following description is of some of the many possible embodiments of the invention and is intended to provide a basic understanding of the invention and is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. It is easily understood that according to the technical solution of the present invention, other implementations that can be substituted with each other can be suggested by those skilled in the art without changing the spirit of the present invention. Therefore, the following detailed description and the accompanying drawings are only exemplary illustrations of the technical solutions of the present invention, and should not be construed as limiting or restricting the technical solutions of the present invention.
FIG. 1 is a schematic structural diagram of a three-state content addressable memory array based on a 3D MOS device with both memristive and rectifying characteristics according to the present invention. The tri-state content addressable memory comprises a plurality of memory units (C) with the functions of storing data, erasing data and comparing data; the memory cells (C) are arranged in an array, all the memory cells in row units are connected with the same Matchline (ML), and all the memory cells in column units are connected with the same pair of complementary searching Signal Lines (SL); m bits are stored on the same Match Line (ML) and each search signal comprises m bits. The n match lines indicate that the tri-state content addressable memory stores n words in total.
Fig. 2 is an example of a current-voltage characteristic diagram of a 3D MOS device having both memristive and rectifying characteristics according to the present invention. In the working state of the device, the electrode of a semiconductor layer is grounded, and corresponding voltage is applied to the electrode of a metal layer of the device, so that the conversion of the device between an off state (I and IV states in the figure) and an on state (II and III states in the figure) is realized, and the method specifically comprises the following steps: the device in the off state is in the off state, the resistance is suddenly reduced after negative voltage is applied to the metal layer, the process is called SET, the device is converted from the off state to the on state, the device has the characteristics of a diode which is conducted from the metal layer to the semiconductor layer and is cut off in the reverse direction, and the device can be used as a conventional diode device; in the on-state device, after a forward voltage is applied to the metal layer, the resistance is suddenly increased, the process is called RESET, the device is turned from the on-state to the off-state, and the device is cut off in two directions and can be regarded as a resistor with high resistance.
Fig. 3 is a schematic structural diagram of a 3D MOS device having both memristive and rectifying characteristics according to the present invention. The 3D MOS device is composed of a metal layer, a memory layer, a rectifying layer and a semiconductor layer which are contacted in sequence, wherein each layer is built along different directions to form a three-dimensional structure; wherein the memory layer and the rectifying layer are realized by an oxide layer in the MOS structure; the semiconductor layer is made of germanium; the memory function of the memory layer is realized by hafnium oxide, and the rectification function of the rectification layer is realized by the matching of germanium oxide and aluminum oxide; the metal layer is composed of titanium nitride or metal nickel, and the metal layers of different devices are isolated by oxides.
In one embodiment of the present application, the device is built in the form of a spatial cylinder (shown in fig. 3 a); each concentric ring is sequentially provided with a metal layer, a memory layer, a rectifying layer and a semiconductor layer from outside to inside; when the device works, because the perimeter of the outer layer material is larger than that of the inner layer material, oxygen ions are gathered when moving, and the impedance characteristic and the rectification effect can be improved.
In another embodiment of the present application, a 3D structure made up of a plurality of such devices is built up in a stack of layers in different directions (shown in fig. 3 b); the semiconductor layers of the plurality of devices are parallel to each other and built on an oxide substrate; the oxide layer and the metal layer are vertical to the oxide substrate and wrap the stacked semiconductor layers from the side; all devices share the same oxide layer and metal layer; this 3D structure is effectual has promoted space utilization efficiency.
After the Forming process of the device, a filament path will form in the hafnium oxide layer from which oxygen ions drift into the germanium oxide layer, which is devoid of oxygen ions. In the absence of the germanium oxide layer, there are no sites for storing oxygen ions and therefore no impedance switching behavior is observed. In addition, the conduction band offset (0.4-0.8eV) between the germanium oxide layer and the semiconductor layer is much smaller than the valence band offset (2.3-4.3eV), so that the forward conduction current is much larger than the reverse conduction current in the germanium oxide layer and the semiconductor layer (N-type highly doped Ge layer), thereby improving the rectification characteristic of the MOS device.
FIG. 4 is a circuit diagram of a memory cell of the present invention. The storage unit comprises two 3D MOS devices; the metal layers of the two MOS devices are directly connected and connected with the same matched line; the semiconductor material germanium layers of the two devices are respectively connected to a pair of complementary signal search lines.
FIG. 5 is a circuit diagram illustrating four data matching results obtained according to an embodiment of the present invention. The first device and the second device in the memory cell cooperate with each other to store three logic states of [0], [1] and [ don't care ]: when the first device is in an off state and the second device is in an on state, the core cell stores a data bit [0 ]; when the first device is in an on state and the second device is in an off state, the core cell stores a data bit [1 ]; when the first device and the second device are both in the off state, the core unit is in a [ don't care ] state.
When the storage data of the memory cell is consistent with the searching signal, the memory cell is in a matching state (match), and when all the memory cells on the same matchline are in the matching state (match), the matchline outputs a precharge result [1 ]; the match line outputs [0] when the memory cell stores data that is not consistent with the search signal, which is a mismatch state (mismatch), and when one or more memory cells on the same match line are in a mismatch state (mismatch).
As shown in fig. 5, the left memory cell in the first row is in a mismatch state (mismatch), the memory cell stores a data bit [0], the search signal is [1], and current flows through the on-state device in the memory cell, so that the voltage of the first row Match Line (ML) after being precharged is discharged and [0] is output; the right memory cell of the first row is in a matching state (match), the memory cell stores a data bit [0], the search signal is [0], and because the open-state device in the memory cell has the rectification characteristic of a conventional diode, the mismatch current caused by the left memory cell of the first row cannot flow through the open-state diode, so that the voltage of the Matched Line (ML) is kept unchanged;
the left memory cell in the second row is in a matching state (match), the memory cell stores a data bit [1], the search signal is [1], and the voltage of a Matchline (ML) is not influenced; the right memory cell of the second row is in a matching state (match), the memory cell stores [ don't care ], the search signal is [0], the voltage of the Matchline (ML) is not influenced, and [1] is output;
the left memory cell of the third row is in a mismatch state (mismatch), the memory cell stores a data bit [0], a search signal is [1], current smoothly flows through an on-state device in the memory cell, so that the voltage of the third row Match Line (ML) after being precharged is discharged, and [0] is output; the third row right memory cell is in match state (match), the memory cell stores [ don't care ], the search signal is [0], the Match Line (ML) voltage is not affected, and [0] is output.
Fig. 6 and 7 are schematic diagrams of a writing method for a tri-state content addressable memory array based on a novel MOS device, in which the switching states of a column of 3D MOS devices directly connected to a single signal search line or a row of 3D MOS devices directly connected to a single match line can be changed by setting the voltages on all signal search lines and match lines in different clock cycles.
If the difference (V) between the match line voltage and the signal search line voltageML-VSL) Greater than the turn-off voltage (V) of a novel MOS deviceOFFGreater than 0), the device directly connected to the matchline and signal search line will be reset to an off state; if the difference (V) between the match line voltage and the signal search line voltageML-VSL) Less than the turn-on voltage (V) of a novel MOS deviceONAnd less than 0), the devices directly connected to the match line and the signal search line are reset to an on state. Thus, any combination of match line voltage and signal search line voltage will have three possible effects on the corresponding device: turning off the device, turning on the device and keeping the device in its original state.
Before the row-wise write begins, as shown in FIG. 6, three matchline levels (high, medium, low) and two signal search line levels (high, low) are selected and the following requirements are met: the match line level and the signal search line level have 6 voltage combinations, wherein the combination of the high match line level and the low signal search line level enables the device to be turned off, the combination of the low match line level and the high signal search line level enables the device to be turned on, and the other four combinations enable the device to keep the original state; in the writing process, the match line of an irrelevant row is set to be the level of a middle match line; in a row to be written, the level of a signal search line connected with a device to be turned off is set to be low, the level of a signal search line connected with a device to be turned on is set to be high, and a match line of the row to be written performs voltage scanning from the level of a low match line to the level of a high match line. During the scanning process, the special combination between the corresponding signal search line level and the match line level changes the switch state of the corresponding device in the row, and the devices in the rest rows are not influenced.
Before the column-wise write begins, as shown in FIG. 7, two matchline levels (high, low) and three signal search line levels (high, medium, low) are selected and the following requirements are met: the match line level and the signal search line level have 6 voltage combinations, wherein the combination of the high match line level and the low signal search line level enables the device to be turned off, the combination of the low match line level and the high signal search line level enables the device to be turned on, and the other four combinations enable the device to keep the original state; in the writing process, setting a signal search line of an irrelevant column as a medium signal search line level; in the column to be written, the level of a matched line connected with a device to be turned off is set as a high matched line level, the level of a matched line connected with a device to be turned on is set as a low matched line level, and a signal search line of the column to be written performs voltage scanning from the low signal search line level to the high signal search line level. During the scanning process, the special combination between the corresponding signal search line level and the match line level changes the switching state of the corresponding device in the row, and the devices in the rest columns are not influenced.
FIG. 8 shows the results of functional simulation of the TCAM array in a simulator. In the simulation, from W7[7:0] to W0[7:0] are XXXX0000, 1111XXXX, XXXX0101, 1010 XXXXX, 01011010,10100101,11111111 and 00000000, respectively, and the search data SD [7:0] is 10100101, which matches with W5, W4 and W2, so the output results of ML5, ML4 and ML2 are high level. The simulation results demonstrate the functionality of the TCAM array proposed in the present application.
The foregoing is only a preferred embodiment of the present invention, and although the present invention has been disclosed in the preferred embodiments, it is not intended to limit the present invention. Those skilled in the art can make numerous possible variations and modifications to the present teachings, or modify equivalent embodiments to equivalent variations, without departing from the scope of the present teachings, using the methods and techniques disclosed above. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.
Claims (6)
1. The three-state content addressable memory is characterized in that the 3D MOS device consists of a metal layer, a memory layer, a rectifying layer and a semiconductor layer which are contacted in sequence;
each layer of the 3D MOS device is built along different directions to form a three-dimensional structure;
the memory layer and the rectifying layer are realized by an oxide layer in an MOS structure;
the memory function of the memory layer is realized by hafnium oxide, and the rectification function of the rectification layer is realized by the matching of germanium oxide and aluminum oxide;
the semiconductor layer is made of germanium;
the memory is formed by arranging a plurality of memory units with the functions of storing, reading, writing and comparing in an array; all the memory cells in the same row are connected with the same matched line, and all the memory cells in the same column are connected with the same pair of complementary signal search lines; each memory cell comprises two 3D MOS devices; the metal layers of the two MOS devices are directly connected and connected with the same matched line; the semiconductor layers of the two MOS devices are respectively connected with a pair of complementary signal search lines;
the writing mode of the ternary content addressable memory is as follows: by setting the voltage of all the signal search lines and the voltage of the match lines in different clock periods, the switching state of a column of 3D MOS devices directly connected with a single signal search line or the switching state of a row of 3D MOS devices directly connected with a single match line can be changed;
before the writing according to rows is started, three matching line levels of high, middle and low and two signal search line levels of high and low are selected and the following requirements are met: the match line level and the signal search line level have 6 voltage combinations, wherein the combination of the high match line level and the low signal search line level enables the device to be turned off, the combination of the low match line level and the high signal search line level enables the device to be turned on, and the other four combinations enable the device to keep the original state; in the writing process, the match line of an irrelevant row is set to be the level of a middle match line; in a row to be written, the level of a signal search line connected with a device to be turned off is set to be low, the level of a signal search line connected with a device to be turned on is set to be high, and a match line of the row to be written performs voltage scanning from the level of a low match line to the level of a high match line;
before the writing in columns starts, two matching line levels of high and low and three signal search line levels of high, medium and low are selected and the following requirements are met: the match line level and the signal search line level have 6 voltage combinations, wherein the combination of the high match line level and the low signal search line level enables the device to be turned off, the combination of the low match line level and the high signal search line level enables the device to be turned on, and the other four combinations enable the device to keep the original state; in the writing process, setting a signal search line of an irrelevant column as a medium signal search line level; in the column to be written, the level of a matched line connected with a device to be turned off is set as a high matched line level, the level of a matched line connected with a device to be turned on is set as a low matched line level, and a signal search line of the column to be written performs voltage scanning from the low signal search line level to the high signal search line level.
2. The ternary content addressable memory according to claim 1, characterized in that the device is built in the form of a spatial cylinder; each concentric ring is sequentially provided with a metal layer, a memory layer, a rectifying layer and a semiconductor layer from outside to inside.
3. The ternary content addressable memory according to claim 1, wherein the 3D structure of a plurality of such devices is built up in a stack of layers in different directions; the semiconductor layers of the plurality of devices are parallel to each other and built on an oxide substrate; the oxide layer and the metal layer are vertical to the oxide substrate and wrap the stacked semiconductor layers from the side; all devices share the same oxide and metal layers.
4. The ternary content addressable memory according to claim 1, wherein a respective voltage is applied between the device metal layer and the semiconductor layer to effect a transition of the device between the off-state and the on-state;
the device in the off state is in the off state, the resistance is suddenly reduced after negative voltage is applied to the metal layer, the process is called SET, the device is converted from the off state to the on state, the device has the characteristics of a diode which is conducted from the metal layer to the semiconductor layer and is cut off in the reverse direction, and the device can be used as a conventional diode device;
in the on-state device, after a forward voltage is applied to the metal layer, the resistance is suddenly increased, the process is called RESET, the device is turned from the on-state to the off-state, and the device is cut off in two directions and can be regarded as a resistor with high resistance.
5. The ternary content addressable memory according to claim 1, wherein the first device and the second device in the memory cell cooperate to store three logic states [0], [1] and [ don't care ]:
when the first device is in an off state and the second device is in an on state, the memory cell stores a data bit [0 ];
when the first device is in an on state and the second device is in an off state, the memory cell stores a data bit [1 ];
when both the first device and the second device are in the off state, the memory cell is in a don't care (don't care) state.
6. The ternary content addressable memory according to claim 1, wherein the match line needs to be precharged to [1] corresponding level before a search operation starts; in the searching process, when the storage data of the storage unit is consistent with the searching signal, the storage unit is in a matching state (match), and when all the storage units on the same matchline are in the matching state (match), the matchline outputs a precharge result [1 ]; the match line outputs [0] when the memory cell stores data that is not consistent with the search signal, which is a mismatch state (mismatch), and when one or more memory cells on the same match line are in a mismatch state (mismatch).
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