CN111276944B - A power tube overcurrent protection circuit - Google Patents
A power tube overcurrent protection circuit Download PDFInfo
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- CN111276944B CN111276944B CN202010229573.7A CN202010229573A CN111276944B CN 111276944 B CN111276944 B CN 111276944B CN 202010229573 A CN202010229573 A CN 202010229573A CN 111276944 B CN111276944 B CN 111276944B
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- 238000001514 detection method Methods 0.000 claims abstract description 60
- 238000006243 chemical reaction Methods 0.000 claims description 55
- 239000003990 capacitor Substances 0.000 claims description 13
- 238000010586 diagram Methods 0.000 description 2
- 238000005265 energy consumption Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 230000001960 triggered effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
- H02H7/20—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment
- H02H7/205—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment for controlled semi-conductors which are not included in a specific circuit arrangement
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
- H02H3/02—Details
- H02H3/06—Details with automatic reconnection
- H02H3/066—Reconnection being a consequence of eliminating the fault which caused disconnection
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
- H02H3/08—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current
- H02H3/093—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current with timing means
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
- H03K17/0814—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Abstract
本发明公开了一种功率管过流保护电路，包括过流检测电路、计时控制电路和使能控制电路，过流检测电路用于检测受控功率管是否过流；计时控制电路和使能控制电路共同控制受控功率管。本发明能在用于控制负载工作与否的受控功率管出现过流时，关断该受控功率管而对受控功率管进行保护。
The present invention discloses a power tube overcurrent protection circuit, comprising an overcurrent detection circuit, a timing control circuit and an enabling control circuit, wherein the overcurrent detection circuit is used to detect whether a controlled power tube has overcurrent; the timing control circuit and the enabling control circuit jointly control the controlled power tube. The present invention can protect the controlled power tube by shutting down the controlled power tube when an overcurrent occurs in the controlled power tube used to control whether a load works or not.
Description
Technical Field
The invention relates to the field of electronic circuits, in particular to a power tube overcurrent protection circuit.
Background
In the field of electronic circuits, a power tube is often used as a switching device to control a rear-end load circuit, and whether the rear-end load circuit works or not is controlled by switching on and off the power tube.
Disclosure of Invention
The invention aims to provide a power tube overcurrent protection circuit which can turn off a controlled power tube to protect the controlled power tube when the controlled power tube is in overcurrent.
In order to achieve the above object, the solution of the present invention is:
The power tube overcurrent protection circuit is applied to a power tube control circuit, and the power tube control circuit comprises a load and a controlled power tube for controlling whether the load works or not, wherein the power tube overcurrent protection circuit comprises:
The overcurrent detection circuit is connected with the controlled power tube; the overcurrent detection circuit is used for detecting whether the controlled power tube is overcurrent or not, and outputting an overcurrent signal from the output end of the overcurrent detection circuit if the controlled power tube is overcurrent, and outputting a normal signal from the output end of the overcurrent detection circuit if the controlled power tube is not overcurrent;
The timing control circuit is connected with the output end of the overcurrent detection circuit; when the timing control circuit is powered on, the output end of the timing control circuit outputs an opening signal; the output end of the timing control circuit continuously outputs a turn-off signal in a set time and re-outputs a turn-on signal after reaching the set time if the output end of the overcurrent detection circuit outputs an overcurrent signal;
the control circuit comprises an enabling control circuit, an enabling control circuit and an enabling control circuit, wherein the enabling control circuit is respectively connected with the output end of the timing control circuit and the grid electrode of the controlled power tube, the enabling control circuit is used for controlling the on-off of the controlled power tube, the enabling control circuit is controlled by a signal output by the output end of the timing control circuit and an enabling signal, the enabling control circuit turns off the controlled power tube as long as the enabling control circuit receives the off signal output by the timing control circuit, and the enabling control circuit turns on the controlled power tube as long as the enabling control circuit receives an effective enabling signal and an on signal output by the timing control circuit.
The timing control circuit is connected with the overcurrent detection circuit through the signal conversion circuit, the overcurrent signal is a low-level signal, the normal signal is a high-level signal, the input end of the signal conversion circuit is connected with the output end of the overcurrent detection circuit, the signal conversion circuit is used for carrying out level conversion on the signal output by the output end of the overcurrent detection circuit, the signal conversion circuit is used for converting the high-level normal signal into a low-level holding signal and outputting the low-level holding signal to the input end of the timing control circuit, the signal conversion circuit is used for converting the low-level overcurrent signal into a high-level triggering signal and outputting the high-level triggering signal to the input end of the timing control circuit, the input end of the timing control circuit is connected with the output end of the signal conversion circuit, after the timing control circuit is powered on, if the input end of the timing control circuit receives the holding signal, the output end of the timing control circuit keeps outputting an opening signal, and if the signal received by the input end of the timing control circuit is changed from the holding signal into the triggering signal, the output end of the timing control circuit continuously outputs a switching-off signal within a set time and outputs the opening signal again after the set time is reached.
The controlled power tube is a PMOS tube, a source electrode of the controlled power tube is connected with a first direct current power supply, a drain electrode of the controlled power tube is connected with the load, the overcurrent detection circuit comprises a second switch tube, a second current source and a comparator, the second switch tube is a PMOS tube, the transconductance of the second switch tube is smaller than that of the controlled power tube, the source electrode of the second switch tube is connected with the first direct current power supply, a grid electrode of the second switch tube is connected with a grid electrode of the controlled power tube and an output end of the enabling control circuit, a drain electrode of the second switch tube is connected with a negative input end of the comparator and is grounded through the second current source, a positive input end of the comparator is connected with the drain electrode of the controlled power tube, an output end of the comparator serves as an output end of the overcurrent detection circuit, a power end of the comparator is connected with the first direct current power supply, and a grounding end of the comparator is connected with a virtual ground circuit.
The virtual circuit comprises a fourth switch tube, a fourth resistor, a third current source and a fourth current source, wherein one end of the fourth resistor is connected with a first direct current power supply, the other end of the fourth resistor is connected with the input end of the third current source and the grid electrode of the fourth switch tube, the source electrode of the fourth switch tube is connected with the grounding end of the comparator, the drain electrode of the fourth switch tube is connected with the input end of the fourth current source, and the output end of the third current source and the output end of the fourth current source are grounded.
The signal conversion circuit comprises a third switching tube, a first resistor, a second resistor, a third resistor, a first capacitor and a Schmitt trigger, wherein the third switching tube is a PMOS tube, a source electrode of the third switching tube is connected with a first direct current power supply, a grid electrode of the third switching tube is used as an input end of the signal conversion circuit, a drain electrode of the third switching tube is connected with one end of the first resistor, the other end of the first resistor is connected with one end of the third resistor and is grounded through the second resistor, the other end of the third resistor is connected with the input end of the Schmitt trigger and is grounded through the first capacitor, and an output end of the Schmitt trigger is used as an output end of the signal conversion circuit.
The enabling control circuit comprises an AND gate, a first current source, a current limiting resistor and a first switching tube, wherein the first switching tube is an NMOS tube, a first input end of the AND gate is used for being connected with an enabling signal, a second input end of the AND gate is used for being connected with an output end of the timing control circuit, an output end of the AND gate is connected with a grid electrode of the first switching tube, one end of the current limiting resistor is connected with a first direct current source, the other end of the current limiting resistor is connected with a drain electrode of the first switching tube, a source electrode of the first switching tube is grounded through the first current source, and a common end of the current limiting resistor and the first switching tube is used as an output end of the enabling control circuit to be connected with a grid electrode of the controlled power tube.
The controlled power tube is an NMOS tube, the input end of the load is connected with a first direct current power supply, the drain electrode of the controlled power tube is connected with the output end of the load, the source electrode of the controlled power tube is grounded, the overcurrent detection circuit comprises a second switch tube, a second current source and a comparator, the second switch tube is an NMOS tube, the transconductance of the second switch tube is smaller than that of the controlled power tube, the input end of the second current source is connected with a first direct current power supply, the output end of the second current source is connected with the drain electrode of the second switch tube and the positive input end of the comparator, the grid electrode of the second switch tube is connected with the grid electrode of the controlled power tube and the output end of the enabling control circuit, the source electrode of the second switch tube is grounded, the negative input end of the comparator is connected with the drain electrode of the controlled power tube, the power end of the comparator is connected with a second direct current power supply, and the ground of the comparator is grounded.
The signal conversion circuit comprises a third switching tube, a first resistor, a second resistor, a third resistor, a first capacitor and a Schmitt trigger, wherein the third switching tube is a PMOS tube, a source electrode of the third switching tube is connected with a second direct current power supply, a grid electrode of the third switching tube is used as an input end of the signal conversion circuit, a drain electrode of the third switching tube is connected with one end of the first resistor, the other end of the first resistor is connected with one end of the third resistor and is grounded through the second resistor, the other end of the third resistor is connected with the input end of the Schmitt trigger and is grounded through the first capacitor, and an output end of the Schmitt trigger is used as an output end of the signal conversion circuit.
The enabling control circuit comprises an AND gate, wherein a first input end of the AND gate is used for accessing an enabling signal, a second input end of the AND gate is used for being connected with an output end of the timing control circuit, and the output end of the AND gate is used as an output end of the enabling control circuit and is connected with a grid electrode of the controlled power tube.
The timing control circuit comprises a D trigger and a counter, wherein the input end of the D trigger is connected with a second direct current power supply, the clock end of the D trigger is connected with the enabling end of the counter and is used as the input end of the timing control circuit, the output end of the counter is connected with the reset end of the D trigger, and the negative output end of the D trigger is used as the output end of the timing control circuit.
After the scheme is adopted, when the controlled power tube is in overcurrent, the timing control circuit can output the turn-off signal to the enabling control circuit, so that the enabling control circuit turns off the controlled power tube, overcurrent protection is realized, and the controlled power tube is prevented from being damaged due to overlarge current. In addition, after the controlled power tube is over-current, the timing control circuit continuously outputs a turn-off signal to the enabling control circuit within a set time, and then outputs a turn-on signal to the enabling control circuit again, so that the enabling control circuit can control the controlled power tube to be turned on again to realize automatic restarting of the controlled power tube, after the controlled power tube is turned on again, if the controlled power tube is not over-current, the controlled power tube normally works to enable the circuit to recover to a normal working state, and if the controlled power tube is still over-current, the timing control circuit and the enabling control circuit turn off the controlled power tube again to protect the controlled power tube.
Drawings
FIG. 1 is a schematic circuit diagram of a first embodiment of the present invention;
FIG. 2 is a schematic circuit diagram of a second embodiment of the present invention;
Description of the reference numerals:
the overcurrent detection circuit 1, the second switching tube Q2, the second current source I2, the comparator U2,
Virtual ground circuit 11, fourth switching tube Q4, fourth resistor R4, third current source I3, fourth current source I4,
The timing control circuit 2, the d flip-flop U4, the counter U5,
An enable control circuit 3, an AND gate U1, a first current source I1, a current limiting resistor RT, a first switching tube Q1,
The signal conversion circuit 4, the third switching tube Q3, the first resistor R1, the second resistor R2, the third resistor R3, the first capacitor C1, the Schmitt trigger U3,
The power tube control circuit 5, the load 51, the controlled power tube M1,
The first DC power supply VDD, the second DC power supply VCC, enable signal EN.
Detailed Description
As shown in fig. 1 and 2, the present invention discloses a power tube overcurrent protection circuit, which is applied to a power tube control circuit 5, wherein the power tube control circuit 5 comprises a load 51 and a controlled power tube M1 for controlling whether the load 51 works or not.
Referring to fig. 1 and 2, the power tube overcurrent protection circuit of the present invention includes an overcurrent detection circuit 1, a timing control circuit 2, and an enable control circuit 3.
The overcurrent detection circuit 1 is connected with the controlled power tube M1, and the overcurrent detection circuit 1 is used for detecting whether the controlled power tube M1 is overcurrent or not, if the controlled power tube is overcurrent, the output end of the overcurrent detection circuit 1 outputs an overcurrent signal, and if the controlled power tube M1 is not overcurrent, the output end of the overcurrent detection circuit 1 outputs a normal signal.
Referring to fig. 1 and 2, the timing control circuit 2 is connected to an output end of the overcurrent detection circuit 1, when the timing control circuit 2 is powered on, an on signal is output from the output end of the timing control circuit 2, the output end of the timing control circuit 2 is controlled according to a signal output from the output end of the overcurrent detection circuit 1 after the timing control circuit 2 is powered on, wherein if the output end of the overcurrent detection circuit 1 outputs an overcurrent signal, the output end of the timing control circuit 2 continuously outputs an off signal within a set time and re-outputs the on signal after the set time is reached, and if the output end of the overcurrent detection circuit 1 outputs a normal signal, the output end of the timing control circuit 2 keeps outputting the on signal. With reference to fig. 1 and 2, the over-current signal is a low-level signal and the normal signal is a high-level signal, the timing control circuit 2 may be connected to the over-current detection circuit 1 through the signal conversion circuit 4, the input end of the signal conversion circuit 4 is connected to the output end of the over-current detection circuit 1, the signal conversion circuit 4 is configured to level convert the signal output by the output end of the over-current detection circuit 1, the signal conversion circuit 4 converts the high-level normal signal into a low-level hold signal and outputs the low-level hold signal to the input end of the timing control circuit 2, the signal conversion circuit 4 converts the low-level over-current signal into a high-level trigger signal and outputs the high-level trigger signal to the input end of the timing control circuit 2, the input end of the timing control circuit 2 is connected to the output end of the signal conversion circuit 4, after the timing control circuit 2 is powered up, the output end of the timing control circuit 2 keeps outputting the on signal if the hold signal is received, and the output on signal is continuously set after the output time of the timing control circuit 2 is reset to the off.
According to the embodiment shown in fig. 1 and fig. 2, the enabling control circuit 3 is respectively connected with the output end of the timing control circuit 2 and the grid electrode of the controlled power tube, the enabling control circuit 3 is used for controlling the on-off state of the controlled power tube M1, the enabling control circuit 3 is controlled by a signal output by the output end of the timing control circuit 2 and an enabling signal EN, the enabling control circuit 3 turns off the controlled power tube M1 as long as the enabling control circuit 3 receives a turn-off signal output by the timing control circuit 2, and the enabling control circuit 3 receives an effective enabling signal EN and an opening signal output by the timing control circuit 2 at the same time when the enabling control circuit 3 receives the controlled power tube M1.
With reference to fig. 1 and 2, the working principle of the invention is as follows:
When the invention starts to work, the timing control circuit 2 outputs an opening signal to the enabling control signal, and meanwhile, the enabling control circuit 3 receives a valid enabling signal EN, so that the enabling control circuit 3 controls the controlled power tube M1 to be opened;
After the controlled power tube M1 is started, if the current of the controlled power tube M1 is normal, the overcurrent detection circuit 1 outputs a normal signal to the signal conversion circuit 4, the signal conversion circuit 4 converts the received normal signal into a holding signal and outputs the holding signal to the timing control circuit 2, and the input end of the timing control circuit 2 receives the holding signal and keeps outputting an opening signal to the enabling control circuit 3, so that the controlled power tube M1 is ensured to be started;
After the controlled power tube M1 is turned on, if the controlled power tube M1 is over-current, the over-current detection circuit 1 outputs an over-current signal to the signal conversion circuit 4, the signal conversion circuit 4 converts the received over-current signal into a trigger signal and outputs the trigger signal to the timing control circuit 2, the signal received by the input end of the timing control circuit 2 is changed from a holding signal to a trigger signal, the timing control circuit 2 outputs a turn-off signal to the enabling control circuit 3 within a set time, so that the controlled power tube M1 is turned off, thereby realizing over-current protection, avoiding damage of the controlled power tube M1 due to over-current, the timing control circuit 2 outputs a turn-off signal to the enabling control circuit 3 again after the timing control circuit 2 outputs a turn-off signal to the enabling control circuit 3 within the set time, so that the enabling control circuit 3 can control the controlled power tube M1 to be turned on again, and after the controlled power tube M1 is turned on again, if the controlled power tube M1 is not over-current, the controlled power tube M1 works normally, and the controlled power tube M1 is controlled to be turned off again, and if the controlled power tube M1 is controlled normally, and the controlled power tube M1 is turned off again, and the timing control circuit 1 is controlled normally.
In order to further explain the technical solution of the invention, the invention is explained in detail below by means of two examples.
Embodiment one:
in cooperation with fig. 1, in the first embodiment of the present invention, the controlled power tube M1 of the power tube control circuit 5 is a PMOS tube, the source of the controlled power tube M1 is connected to a first direct current VDD, and the drain of the controlled power tube M1 is connected to the load 51.
In cooperation with fig. 1, in the first embodiment of the present invention, the overcurrent detection circuit 1 includes a second switching tube Q2, a second current source I2, and a comparator U2, where the second switching tube Q2 is a PMOS tube, and the transconductance of the second switching tube Q2 is smaller than that of the controlled power tube M1, a source electrode of the second switching tube Q2 is connected to the first direct current power supply VDD, a gate electrode of the second switching tube Q2 is connected to the gate electrode of the controlled power tube M1 and an output end of the enable control circuit 3, a drain electrode of the second switching tube Q2 is connected to a negative input end of the comparator U2 and is grounded through the second current source I2, a positive input end of the comparator U2 is connected to an output end of the controlled power tube M1, and an output end of the comparator U2 is connected to the signal conversion circuit 4 as an output end of the overcurrent detection circuit 1, so that when the enable control circuit 3 controls the controlled power tube M1 to be turned on, the second switching tube Q2 is synchronously turned on, and when the enable control circuit 3 controls the controlled power tube M1 to be turned off, the second switching tube Q2 is synchronously turned off, so that energy consumption is reduced. In addition, as the sources of the second switching tube Q2 and the controlled power tube M1 are both connected with the first direct current power supply VDD, the gates of the second switching tube Q2 and the controlled power tube M1 are both connected with the output end of the enabling control circuit 3, and the second switching tube Q2 and the controlled power tube M1 are field effect tubes of the same type, when the controlled power tube M1 and the second switching tube Q2 are opened, if the drain voltages of the controlled power tube M1 and the second switching tube Q2 are equal, namely the voltage of the positive input end of the comparator U2 is equal to the voltage of the negative input end of the comparator U2, the current of the controlled power tube M1 is N times of the current of the second switching tube Q2, and N is equal to the transconductance of the controlled power tube M1 divided by the transconductance of the second switching tube Q2; if the drain voltage of the controlled power tube M1 is smaller than the drain voltage of the second switching tube Q2, i.e. the positive input end voltage of the comparator U2 is smaller than the negative input end voltage of the comparator U2, the current of the controlled power tube M1 is larger than N times of the current of the second switching tube Q2, the comparator U2 outputs a low-level overcurrent signal, if the drain voltage of the controlled power tube M1 is larger than the drain voltage of the second switching tube Q2, i.e. the positive input end voltage of the comparator U2 is larger than the negative input end voltage of the comparator U2, the current of the controlled power tube M1 is smaller than N times of the current of the second switching tube Q2, the comparator U2 outputs a high-level normal signal, thus setting the N times of the current of the second switching tube Q2 to be the overcurrent threshold of the controlled power tube M1, when the controlled power tube M1 does not have overcurrent, the current of the controlled power tube M1 is smaller than the overcurrent threshold, the positive input end voltage of the comparator U2 is larger than the negative input end voltage of the comparator U2, if the controlled power tube M2 outputs a high-level normal signal, when the current of the controlled power tube M1 is larger than the overcurrent threshold, the voltage of the positive input end of the comparator U2 is smaller than the voltage of the negative input end of the comparator U2, and the comparator U2 outputs a low-level overcurrent signal.
In cooperation with fig. 1, in the first embodiment of the present invention, a power end of a comparator U2 of the overcurrent detection circuit 1 is connected to a first direct current power supply VDD, and a ground end of the comparator U2 is connected to a virtual ground circuit 11, wherein the virtual ground circuit 11 includes a fourth switching tube Q4, a fourth resistor R4, a third current source I3, and a fourth current source I4, the fourth switching tube Q4 is a PMOS tube, one end of the fourth resistor R4 is connected to the first direct current power supply VDD, the other end of the fourth resistor R4 is connected to an input end of the third current source I3 and a gate of the fourth switching tube Q4, a source of the fourth switching tube Q4 is connected to a ground end of the comparator U2, and a drain electrode of the fourth switching tube Q4 is connected to an input end of the fourth current source I4, an output end of the third current source I3 and an output end of the fourth current source I4 are grounded, so that a ground end voltage nd=vdd-I3+vgs of the fourth current source I4 of the comparator U2 is the voltage VDD, wherein the VDD is the voltage VDD 3 is the first direct current power supply and the fourth current source I3 is the voltage V4, and the voltage V4 is lower than the fourth current V2, and the voltage V4 is lower than the voltage V2 is lower than the fourth current V4, and the voltage is lower than the voltage of the fourth current source V4 is lower than the voltage of the fourth current source V2, and is lower than the voltage region, and the voltage is lower than the voltage V2, and is lower than the voltage region.
In conjunction with fig. 1, in the first embodiment of the present invention, the signal conversion circuit 4 includes a third switching tube Q3, a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, and a schmitt trigger U3, where the third switching tube Q3 is a PMOS tube, a source electrode of the third switching tube Q3 is connected to the first direct current power VDD, a gate electrode of the third switching tube Q3 is connected to an output end of the overcurrent detection circuit 1 as an input end of the signal conversion circuit 4, a drain electrode of the third switching tube Q3 is connected to one end of the first resistor R1, another end of the first resistor R1 is connected to one end of the third resistor R3 and grounded through the second resistor R2, another end of the third resistor R3 is connected to an input end of the schmitt trigger U3 and grounded through the first capacitor C1, and an output end of the schmitt trigger U3 is used as an output end of the signal conversion circuit 4. Therefore, when a high-level normal signal is input into the signal conversion circuit 4, the third switching tube Q3 is turned off to enable the input end voltage of the Schmitt trigger U3 to be low level, so that the output end of the Schmitt trigger U3 can output a low-level holding signal, and when a low-level overcurrent signal is input into the signal conversion circuit 4, the third switching tube Q3 is turned on to enable the input end voltage of the Schmitt trigger U3 to be high level, so that the output end of the Schmitt trigger U3 can output a high-level triggering signal, wherein voltage division operation can be conducted through the first resistor R1 and the second resistor R2, so that the Schmitt trigger U3 can work in a low-voltage area lower than the first direct-current power supply VDD voltage, and further the timing control circuit 2 at the rear end can work in a low-voltage area lower than the first direct-current power supply VDD voltage, so that the Schmitt trigger U3 and the timing control circuit 2 can adopt low-voltage devices, and in addition, the output holding signals and the stable voltage of the triggering signals can be enabled through the Schmitt trigger U3.
In conjunction with fig. 1, in the first embodiment of the present invention, the timing control circuit 2 includes a D flip-flop U4 and a counter U5, the positive output end of the D flip-flop U4 is in a low level, the input end of the D flip-flop U4 is connected to a second dc power VCC, the voltage of the second dc power VCC may be lower than the voltage of the first dc power VDD, the clock end of the D flip-flop U4 is connected to the enable end of the counter U5 and is used as the input end of the timing control circuit 2, the output end of the counter U5 is connected to the reset end of the D flip-flop U4, the negative output end of the D flip-flop U4 is used as the output end of the timing control circuit 2 and is connected to the enable control circuit 3, so that when the timing control circuit 2 is powered on, the negative output end of the D flip-flop U4 outputs a high level on signal, and when the signal received by the input end of the timing control circuit 2 is changed from the hold signal to the trigger signal, that is generated by the signal received by the input end of the timing control circuit 2, a rising edge, the D flip-flop U4 is triggered, the trigger U4 is enabled to be reset, and the negative output of the D flip-flop U4 is enabled, and the counter the negative output signal is turned off, and the counter U4 is enabled to the negative output the signal.
In cooperation with fig. 1, in the first embodiment of the present invention, the enabling control circuit 3 includes an and gate U1, a first current source I1, a current limiting resistor RT and a first switching tube Q1, where the first switching tube Q1 is an NMOS tube, a first input terminal of the and gate U1 is used for accessing an enabling signal EN, a second input terminal of the and gate U1 is used for connecting an output terminal of the timing control circuit 2 and accessing an output signal of the timing control circuit 2, an output terminal of the and gate U1 is connected to a gate of the first switching tube Q1, one end of the current limiting resistor RT is connected to a first direct current source VDD, another end of the current limiting resistor RT is connected to a drain electrode of the first switching tube Q1, a source electrode of the first switching tube Q1 is grounded through the first current source I1, a common terminal of the current limiting resistor RT and the first switching tube Q1 is used as an output terminal of the enabling control circuit 3, the enabling signal EN is effective in a high level, when the first input terminal and the second input terminal of the and the second input terminal of the and gate U1 are respectively accessed to the enabling signal of the high level, the first input terminal and the high level enabling signal and the second input terminal of the and the high level enabling signal EN are respectively, the first input terminal of the and the high level enabling signal Q1 is turned on, and the first input to the first switching tube Q1 is turned off, and the first switching tube Q1 is turned on and the first switching tube Q1 is turned off, and the first switching tube is turned off.
Embodiment two:
In conjunction with fig. 2, in the second embodiment of the present invention, the controlled power tube M1 of the power tube control circuit 5 is an NMOS tube, the input end of the load 51 is connected to a first direct current power supply VDD, the output end of the load 51 is connected to the drain electrode of the controlled power tube M1, and the source electrode of the controlled power tube M1 is grounded.
In conjunction with fig. 2, in the second embodiment of the present invention, the overcurrent detection circuit 1 includes a second switching tube Q2, a second current source I2 and a comparator U2, where the second switching tube Q2 is an NMOS tube, the transconductance of the second switching tube Q2 is smaller than that of the controlled power tube M1, the input end of the second current source I2 is connected to the first direct current power VDD, the output end of the second current source I2 is connected to the drain of the second switching tube Q2 and the positive input end of the comparator U2, the gate of the second switching tube Q2 is connected to the gate of the controlled power tube M1 and the output end of the enable control circuit 3, the source of the second switching tube Q2 is grounded, the negative input end of the comparator U2 is connected to the drain of the controlled power tube M1, the power end of the comparator U2 is connected to a second direct current power source VCC, and the ground of the comparator U2 is grounded, so that when the enable control circuit 3 controls the controlled power tube M1 to be turned on, the second switching tube Q2 is also synchronously turned on, and when the enable control circuit 3 controls the controlled power tube M1 to be turned off, the second switching tube Q2 is also synchronously turned off, thereby reducing energy consumption. In addition, as the sources of the second switching tube Q2 and the controlled power tube M1 are grounded, the input ends of the load 51 and the second current source I2 are both connected with the first direct current power supply VDD, the gates of the second switching tube Q2 and the controlled power tube M1 are both connected with the output end of the enable control circuit 3, the second switching tube Q2 and the controlled power tube M1 are field effect tubes of the same type, when the controlled power tube M1 and the second switching tube Q2 are turned on, if the drain voltages of the controlled power tube M1 and the second switching tube Q2 are equal, i.e. the voltage of the positive input end of the comparator U2 is equal to the voltage of the negative input end of the comparator U2, at this time, the current of the controlled power tube M1 is N times the current of the second switching tube Q2, and N is equal to the transconductance of the controlled power tube M1 divided by the transconductance of the second switching tube Q2; if the drain voltage of the controlled power tube M1 is larger than the drain voltage of the second switch tube Q2, i.e. the positive input end voltage of the comparator U2 is smaller than the negative input end voltage of the comparator U2, the current of the controlled power tube M1 is larger than N times of the current of the second switch tube Q2, the comparator U2 outputs a low-level overcurrent signal, and if the drain voltage of the controlled power tube M1 is smaller than the drain voltage of the second switch tube Q2, i.e. the positive input end voltage of the comparator U2 is larger than the negative input end voltage of the comparator U2, the current of the controlled power tube M1 is smaller than N times of the current of the second switch tube Q2, the comparator U2 outputs a high-level normal signal, thus setting the N times of the current of the second switch tube Q2 to be the overcurrent threshold of the controlled power tube M1, when the controlled power tube M1 is not overcurrent, the current of the controlled power tube M1 is smaller than the overcurrent threshold, the positive input end voltage of the comparator U2 is larger than the negative input end voltage of the comparator U2, the comparator U2 outputs a high-level normal signal, and if the controlled power tube M1 has an overcurrent, the current of the controlled power tube M1 is greater than the overcurrent threshold, the voltage of the positive input end of the comparator U2 is smaller than the voltage of the negative input end of the comparator U2, and the comparator U2 outputs a low-level overcurrent signal.
In conjunction with fig. 2, in the second embodiment of the present invention, the signal conversion circuit 4 includes a third switching tube Q3, a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, and a schmitt trigger U3, where the third switching tube Q3 is a PMOS tube, a source electrode of the third switching tube Q3 is connected to the second dc power VCC, a gate electrode of the third switching tube Q3 is connected to an output end of the overcurrent detection circuit 1 as an input end of the signal conversion circuit 4, a drain electrode of the third switching tube Q3 is connected to one end of the first resistor R1, another end of the first resistor R1 is connected to one end of the third resistor R3 and grounded through the second resistor R2, another end of the third resistor R3 is connected to an input end of the schmitt trigger U3 and grounded through the first capacitor C1, and an output end of the schmitt trigger U3 is used as an output end of the signal conversion circuit 4. Thus, when a high-level normal signal is input into the signal conversion circuit 4, the third switching tube Q3 is turned off to enable the input end voltage of the Schmitt trigger U3 to be low level, and the output end of the Schmitt trigger U3 outputs a low-level holding signal, and when a low-level overcurrent signal is input into the signal conversion circuit 4, the third switching tube Q3 is turned on to enable the input end voltage of the Schmitt trigger U3 to be high level, and the output end of the Schmitt trigger U3 outputs a high-level triggering signal, wherein voltage division operation can be performed through the first resistor R1 and the second resistor R2 to reduce the voltage, and in addition, the output holding signal and the triggering signal voltage can be stabilized through the Schmitt trigger U3.
In conjunction with fig. 2, in the second embodiment of the present invention, the timing control circuit 2 includes a D flip-flop U4 and a counter U5, the positive output terminal of the D flip-flop U4 is in a low level, the input terminal of the D flip-flop U4 is connected to a second dc power VCC, the voltage of the second dc power VCC may be lower than the voltage of the first dc power VDD, the clock terminal of the D flip-flop U4 is connected to the enable terminal of the counter U5 and is used as the input terminal of the timing control circuit 2, the output terminal of the counter U5 is connected to the reset terminal of the D flip-flop U4, the negative output terminal of the D flip-flop U4 is used as the output terminal of the timing control circuit 2 and is connected to the enable control circuit 3, so that when the timing control circuit 2 is powered on, the negative output terminal of the D flip-flop U4 outputs a high level on signal, and when the signal received by the input terminal of the timing control circuit 2 is changed from the hold signal to the trigger signal, that is generated by the signal received by the input terminal of the timing control circuit 2, a rising edge, the D flip-flop U4 is triggered, the trigger U4 is enabled to be reset, and the negative output signal of the D flip-flop U4 is reset, and the counter is enabled to be turned off, and the negative output signal of the D flip-flop U4 is reset, and the counter is enabled to the output at the negative output signal after the negative level of the output signal U4.
In conjunction with fig. 2, in the second embodiment of the present invention, the enabling control circuit 3 includes an and gate U1, where a first input terminal of the and gate U1 is used for accessing an enabling signal EN, a second input terminal of the and gate U1 is used for connecting an output terminal of the timing control circuit 2 and accessing an output signal of the timing control circuit 2, and an output terminal of the and gate U1 is connected as an output terminal of the enabling control circuit 3, the enabling signal EN is valid at a high level, when the first input terminal and the second input terminal of the and gate U1 access an enabling signal EN at a high level and an opening signal at a high level respectively, the and gate U1 outputs a high level to the gates of the controlled power tube M1 and the second switching tube Q2, so as to control the controlled power tube M1 and the second switching tube Q2 to be opened, and when the second input terminal of the and gate U1 access a closing signal at a low level, the and gate U1 outputs a low level to the controlled power tube M1 and the second switching tube Q2 to be closed.
The above examples and drawings are not intended to limit the form or form of the present invention, and any suitable variations or modifications thereof by those skilled in the art should be construed as not departing from the scope of the present invention.
Claims (11)
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| CN202010229573.7A CN111276944B (en) | 2020-03-27 | 2020-03-27 | A power tube overcurrent protection circuit |
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| CN202010229573.7A CN111276944B (en) | 2020-03-27 | 2020-03-27 | A power tube overcurrent protection circuit |
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| CN111564825B (en) * | 2020-07-09 | 2020-11-17 | 深圳市创芯微微电子有限公司 | Battery protection circuit |
| CN111901923B (en) * | 2020-08-03 | 2023-10-03 | 四川遂宁市利普芯微电子有限公司 | Overcurrent protection circuit of common-cathode LED display line driving chip |
| CN111817264B (en) * | 2020-08-03 | 2025-08-05 | 四川遂宁市利普芯微电子有限公司 | An overcurrent protection circuit for a common anode LED display row driver chip |
| CN112491012B (en) * | 2021-02-03 | 2021-04-16 | 四川蕊源集成电路科技有限公司 | Current-limiting double-protection circuit and current-limiting double-protection method of circuit |
| CN114814530A (en) * | 2022-04-01 | 2022-07-29 | 合肥仙湖半导体科技有限公司 | An open-load detection circuit, method and application for high-side intelligent power IC |
| CN116027097B (en) * | 2022-12-16 | 2024-04-05 | 无锡中微爱芯电子有限公司 | An overcurrent detection circuit for gate drive |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102208802A (en) * | 2010-06-29 | 2011-10-05 | 上海山景集成电路技术有限公司 | Power switching tube overcurrent detection and overcurrent protection circuit |
| CN211830193U (en) * | 2020-03-27 | 2020-10-30 | 矽恩微电子(厦门)有限公司 | Power tube overcurrent protection circuit |
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| TW214020B (en) * | 1990-10-12 | 1993-10-01 | Raychem Ltd | |
| EP0577339B1 (en) * | 1992-06-30 | 1999-10-06 | Eaton Corporation | Overcurrent protection device |
| JP2010279188A (en) * | 2009-05-29 | 2010-12-09 | Sanyo Electric Co Ltd | Overcurrent protection circuit |
| CN102035190B (en) * | 2010-12-23 | 2013-06-12 | 上海贝岭股份有限公司 | Over-current protection circuit |
| DE102013000251B4 (en) * | 2012-01-10 | 2025-05-08 | Fairchild Semiconductor Corporation | Dimmer control with soft start overcurrent protection |
| CN105119240B (en) * | 2015-09-15 | 2018-01-02 | 无锡芯朋微电子股份有限公司 | Primary side feedback voltage sample resistive short protection circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102208802A (en) * | 2010-06-29 | 2011-10-05 | 上海山景集成电路技术有限公司 | Power switching tube overcurrent detection and overcurrent protection circuit |
| CN211830193U (en) * | 2020-03-27 | 2020-10-30 | 矽恩微电子(厦门)有限公司 | Power tube overcurrent protection circuit |
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