CN111277354B - Coding and decoding method and related device of low-density parity check LDPC code - Google Patents
Coding and decoding method and related device of low-density parity check LDPC code Download PDFInfo
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Abstract
本申请提供了一种奇偶校验LDPC码的编译码方法和装置。本申请的方案根据奇偶校验H矩阵,对8064个信息比特进行LDPC编码,编码得到码率分别为R=1/2,5/8,3/4,13/16,7/8的LDPC码,其中奇偶校验H矩阵为(n+s‑k)×(n+s)的奇偶校验矩阵,H矩阵被划分为大小为Z×Z维的子方阵,所述Z取值为64或42,子方阵为单位矩阵的循环移位或空矩阵,s为待缩短比特与所述H矩阵所对应的列数,且为Z的正整数倍。
The present application provides a method and device for encoding and decoding a parity-check LDPC code. According to the parity check H matrix, the scheme of the present application performs LDPC encoding on 8064 information bits, and the encoding obtains LDPC codes with code rates of R=1/2, 5/8, 3/4, 13/16, and 7/8 respectively , wherein the parity check H matrix is a parity check matrix of (n+s-k)×(n+s), and the H matrix is divided into sub-square matrices whose size is Z×Z dimensions, and the value of Z is 64 Or 42, the sub-square matrix is the cyclic shift of the unit matrix or an empty matrix, s is the number of columns corresponding to the bits to be shortened and the H matrix, and is a positive integer multiple of Z.
Description
技术领域technical field
本申请涉及通信技术领域,特别涉及低密度奇偶校验LDPC码的编译码方法、相关装置。The present application relates to the field of communication technology, and in particular to a coding and decoding method and a related device of a low-density parity-check LDPC code.
背景技术Background technique
无线局域网(wireless LAN,WLAN)标准IEEE802.11ad/ay主要研究目的是如何在60吉赫兹(Giga Hz,GHz)大带宽场景下提升用户的体验,包括提升用户平均吞吐量以及电池类供电设备的能量使用效率。60GHz大带宽场景需要支持在有限的频率和功率资源上实现数据、视频等业务的高速可靠传输,因此需要高可靠性和高效率的信道编译码方案。在信道编码领域,Turbo码和低密度奇偶校验(Low-density parity-check code,LDPC)码是应用最成熟和广泛的两种信道编码方法,它们都有接近香农(Shannon)限的性能,均已经被广泛地应用到通信领域。与Turbo码相比,LDPC码具有:不需要深度交织器即可获得很好的误码性能;具有更好的误帧率性能;错误平层大大降低;支持并行译码增加吞吐量,译码延时小等优点。The main research purpose of wireless local area network (wireless LAN, WLAN) standard IEEE802.11ad/ay is how to improve user experience in 60 GHz (Giga Hz, GHz) high-bandwidth scenarios, including improving user average throughput and battery-powered devices. Energy use efficiency. The 60GHz large bandwidth scenario needs to support high-speed and reliable transmission of data, video and other services on limited frequency and power resources, so a highly reliable and efficient channel coding and decoding solution is required. In the field of channel coding, Turbo codes and Low-density parity-check (LDPC) codes are the most mature and widely used two channel coding methods, both of which have performance close to the Shannon limit. Both have been widely used in the field of communication. Compared with Turbo codes, LDPC codes have: good bit error performance without deep interleaver; better frame error rate performance; greatly reduced error floor; support for parallel decoding to increase throughput, decoding The advantages of small delay and so on.
因此,LDPC码已成为IEEE802.11n/ac/ax等低频短距WLAN通信系统的标准信道编码方案,同时也已成为IEEE802.11ad/ay等60GHz高频短距WLAN通信系统的信道编码方案。基于此,也可考虑针对下一代60GHz WLAN系统设计新的LDPC码,以进一步提高下一代WLAN系统的可靠性和系统性能。Therefore, LDPC codes have become the standard channel coding scheme for low-frequency short-range WLAN communication systems such as IEEE802.11n/ac/ax, and have also become the channel coding scheme for 60GHz high-frequency short-range WLAN communication systems such as IEEE802.11ad/ay. Based on this, it may also be considered to design a new LDPC code for the next-generation 60GHz WLAN system, so as to further improve the reliability and system performance of the next-generation WLAN system.
发明内容Contents of the invention
第一方面,本申请提供了一种低密度奇偶校验LDPC码的编码方法,包括:根据奇偶校验H矩阵,对8064个信息比特进行LDPC编码,获得编码后的码字C,所述码字C的码长为n,码率R为k/n,n为大于k的正整数;其中,所述H矩阵为(n+s-k)×(n+s)的奇偶校验矩阵,所述H矩阵被划分为大小为Z×Z维的子方阵,所述Z取值为64或42,所述子方阵为单位矩阵的循环移位或空矩阵,s为待缩短比特与所述H矩阵所对应的列数,且为Z的正整数倍。基于此方案可以得到新的码长更长的LDPC码,可以降低误码率,降低计算复杂度,进一步提高系统的性能和可靠性。In the first aspect, the present application provides an encoding method of a low-density parity-check LDPC code, including: performing LDPC encoding on 8064 information bits according to the parity-check H matrix to obtain an encoded code word C, the code The code length of the word C is n, the code rate R is k/n, and n is a positive integer greater than k; wherein, the H matrix is a parity check matrix of (n+s-k)×(n+s), and the The H matrix is divided into a sub-square matrix with a size of Z×Z dimension, the value of Z is 64 or 42, the sub-square matrix is a cyclic shift of the unit matrix or an empty matrix, and s is the bit to be shortened and the The number of columns corresponding to the H matrix, which is a positive integer multiple of Z. Based on this scheme, a new LDPC code with a longer code length can be obtained, which can reduce the bit error rate, reduce the computational complexity, and further improve the performance and reliability of the system.
在一种可能的实现方法中,在所述8064个信息比特前填充s个待缩短比特,得到(s+k)个待编码比特,所述s个待缩短比特的值为0;对所述(s+k)个待编码比特进行LDPC编码,获得编码后的码字C1,所述码字C1的码长为(s+n);删除所述码字C1中的所述s个待缩短比特,得到所述码字C,其中,所述s个待缩短比特与所述H矩阵的前s列相对应。通过在k个信息比特前填充s个值为0的待缩短比特,可有效提升译码性能,降低误比特率或误码字率。In a possible implementation method, s bits to be shortened are filled before the 8064 information bits to obtain (s+k) bits to be encoded, and the value of the s bits to be shortened is 0; for the (s+k) bits to be encoded are subjected to LDPC encoding to obtain encoded codeword C 1 , the code length of the codeword C 1 is (s+n); delete the s in the codeword C 1 bits to be shortened to obtain the codeword C, wherein the s bits to be shortened correspond to the first s columns of the H matrix. By filling s bits to be shortened with a value of 0 before the k information bits, the decoding performance can be effectively improved and the bit error rate or word error rate can be reduced.
第二方面,本申请提供一种低密度奇偶校验LDPC码的译码方法,包括:获取经过LDPC编码后的码字C,在码字C之前填充s个待缩短比特,构成码长为(s+n)的码字C1,利用奇偶校验H矩阵对码字C1进行解码,获得解码后的k个信息比特;其中,H矩阵为(n+s-k)×(n+s)奇偶校验矩阵,奇偶校验矩阵H被划分为大小为ZxZ的子方阵,子方阵是单位矩阵的循环移位,或是具有全零项的空子矩阵。s为待缩短比特与所述H矩阵所对应的列数,且为Z的正整数倍。In a second aspect, the present application provides a decoding method of a low-density parity-check LDPC code, including: obtaining a code word C after LDPC encoding, filling s bits to be shortened before the code word C, and forming a code length of ( s+n) codeword C 1 , use the parity check H matrix to decode the codeword C 1 to obtain the decoded k information bits; where, the H matrix is (n+sk)×(n+s) parity The check matrix, the parity check matrix H is divided into a sub-square matrix with a size of ZxZ, and the sub-square matrix is a cyclic shift of the identity matrix, or an empty sub-matrix with all zero entries. s is the number of columns corresponding to the bits to be shortened and the H matrix, and is a positive integer multiple of Z.
其中,单位矩阵记为P0,单位矩阵P0的循环置换矩阵Pi表示通过将单位矩阵P0向右循环移动i个元素,称为循环移位矩阵。可选的,Z的取值为64或42。Wherein, the identity matrix is denoted as P0, and the cyclic permutation matrix Pi of the identity matrix P0 means that the identity matrix P0 is cyclically shifted to the right by i elements, which is called a cyclic shift matrix. Optionally, the value of Z is 64 or 42.
在一种可能的实现方法中,利用奇偶校验H矩阵对码字C1进行解码,获得解码后的k个信息比特,包括:利用奇偶校验H矩阵对码字C1进行解码后,得到(s+k)个译码比特,删除所述(s+k)个译码比特中的前s个待缩短比特,获得解码后的k个信息比特,所述s个待缩短比特的值为0。通过在k个信息比特前填充s个值为0的待缩短比特,可有效提升译码性能,降低误比特率或误码字率。In a possible implementation method, the code word C 1 is decoded by using the parity check H matrix to obtain the decoded k information bits, including: after decoding the code word C 1 by using the parity check H matrix, obtaining (s+k) decoding bits, delete the first s bits to be shortened in the (s+k) decoding bits, and obtain k information bits after decoding, and the value of the s to be shortened bits is 0. By filling s bits to be shortened with a value of 0 before the k information bits, the decoding performance can be effectively improved and the bit error rate or word error rate can be reduced.
结合第一方面或第二方面或其可能的实现方法中,该译码方法或编码方法可应用于高频无线通信局域网中,例如,60吉赫兹无线通信系统中。In combination with the first aspect or the second aspect or possible implementation methods thereof, the decoding method or encoding method can be applied to a high-frequency wireless communication local area network, for example, a 60 GHz wireless communication system.
结合第一方面或第二方面,在一种可能的实现方式中,奇偶校验H矩阵可为示例一至示例十中所示的任何一个。奇偶校验H矩阵还可以采用其他形式表示,且任一个H矩阵中的行和行的次序可以相互交换,列和列的次序也可以相互交换。With reference to the first aspect or the second aspect, in a possible implementation manner, the parity check H matrix may be any one shown in Example 1 to Example 10. The parity-check H matrix can also be expressed in other forms, and the order of rows and rows in any H matrix can be exchanged, and the order of columns can also be exchanged.
第三方面,本申请提供了一种低密度奇偶校验LDPC码的编码装置,该装置具有实现上述第一方面中涉及编码侧的功能。该功能可以通过硬件实现,也可以通过硬件执行相应的软件实现。该硬件或软件包括一个或多个与上述功能相对应的单元。In a third aspect, the present application provides a low-density parity-check LDPC code encoding device, which has the function of realizing the encoding side in the above-mentioned first aspect. This function may be implemented by hardware, or may be implemented by executing corresponding software on the hardware. The hardware or software includes one or more units corresponding to the functions described above.
在一种可能的实现方式中,当该装置包括:处理器和存储器,所述处理器被配置为支持编码装置执行上述第一方面方法中相应的功能。所述存储器用于与处理器耦合,其保存编码装置必要的程序指令和数据。In a possible implementation manner, when the device includes: a processor and a memory, the processor is configured to support the encoding device to perform corresponding functions in the method of the first aspect above. The memory is used for coupling with the processor, which stores necessary program instructions and data of the encoding device.
在另一种可能的实现方式中,该装置包括:生成模块,编码模块和输入输出模块;生成模块用于生成k个信息比特;编码模块,用于根据奇偶校验H矩阵,对所述k个信息比特进行LDPC编码,获得编码后的码字C,所述码字C的码长为n,码率R为k/n;输入输出模块1003,用于输出所述码字C。In another possible implementation, the device includes: a generation module, an encoding module, and an input-output module; the generation module is used to generate k information bits; the encoding module is used to perform the k LDPC encoding is performed on information bits to obtain a coded code word C, the code length of the code word C is n, and the code rate R is k/n; the input and output module 1003 is used to output the code word C.
在又一个可能的实现方式中,该装置包括:处理器,存储器,发送模块,接收模块,射频模块,天线,用于支持编码装置执行上述第一方面方法中相应的功能。In yet another possible implementation manner, the device includes: a processor, a memory, a sending module, a receiving module, a radio frequency module, and an antenna, configured to support the encoding device to perform corresponding functions in the method of the first aspect above.
第四方面,本申请提供了一种低密度奇偶校验LDPC码的译码装置,该装置具有实现上述第二方面中涉及译码侧的功能。该功能可以通过硬件实现,也可以通过硬件执行相应的软件实现。该硬件或软件包括一个或多个与上述功能相对应的单元。In a fourth aspect, the present application provides a device for decoding a low-density parity check LDPC code, and the device has the function of realizing the decoding side in the above-mentioned second aspect. This function may be implemented by hardware, or may be implemented by executing corresponding software on the hardware. The hardware or software includes one or more units corresponding to the functions described above.
在一种可能的实现方式中,当该装置包括:处理器和存储器,所述处理器被配置为支持译码装置执行上述第二方面中相应的功能。所述存储器用于与处理器耦合,其保存编码装置必要的程序指令和数据。可选的,该存储器可以位于该处理器内部,为内部存储器,还可以位于该处理器外部,为外部存储器。In a possible implementation manner, when the device includes: a processor and a memory, the processor is configured to support the decoding device to perform the corresponding functions in the second aspect above. The memory is used for coupling with the processor, which stores necessary program instructions and data of the encoding device. Optionally, the memory may be located inside the processor as an internal memory, or located outside the processor as an external memory.
在另一种可能的实现方式中,该装置包括:输入输出模块,填充模块和译码模块;输入输出模块,用于获取待解码的码字C1,包括n个码字比特;填充模块,用于在n个码字比特前填充s个待删除比特,构成(s+n)个待译码比特,这s个待删除比特的值为0;译码模块,用于根据奇偶校验H矩阵,对所述(s+n)个待译码比特进行LDPC译码,获得译码后的k个比特。In another possible implementation, the device includes: an input-output module, a padding module and a decoding module; an input-output module, configured to obtain a codeword C 1 to be decoded, including n codeword bits; a padding module, It is used to fill s bits to be deleted before n codeword bits to form (s+n) bits to be decoded, and the value of these s bits to be deleted is 0; the decoding module is used for parity check H matrix, performing LDPC decoding on the (s+n) bits to be decoded to obtain k bits after decoding.
在又一个可能的实现方式中,该装置包括:处理器,存储器,发送模块,接收模块,射频模块,天线,用于支持编码装置执行上述方法中相应的功能。In yet another possible implementation manner, the device includes: a processor, a memory, a sending module, a receiving module, a radio frequency module, and an antenna, configured to support the encoding device to perform corresponding functions in the foregoing method.
上述任一处提到的处理器,可以是一个通用中央处理器(Central ProcessingUnit,简称CPU),微处理器,特定应用集成电路(application-specific integratedcircuit,简称ASIC),或一个或多个用于控制上述各方面空间复用方法的程序执行的集成电路。The processor mentioned in any of the above can be a general-purpose central processing unit (Central Processing Unit, referred to as CPU), a microprocessor, a specific application integrated circuit (application-specific integrated circuit, referred to as ASIC), or one or more An integrated circuit controlling program execution of the spatial multiplexing method of the above aspects.
第五方面,本申请提供了一种计算机可读存储介质,所述计算机可读存储介质中存储有指令,所述指令可以由处理电路上的一个或多个处理器执行。当其在计算机上运行时,使得计算机执行上述第一方面或第二方面中的方法。In a fifth aspect, the present application provides a computer-readable storage medium, where instructions are stored in the computer-readable storage medium, and the instructions can be executed by one or more processors on a processing circuit. When it runs on a computer, it causes the computer to execute the method in the first aspect or the second aspect above.
第六方面,提供了一种包含指令的计算机程序产品,该计算机程序产品包括用于实现上述第一方面或第二方面中方法的指令,其在计算机上运行时,使得计算机执行上述第一方面或第二方面或其任意可能的实现方式中的方法。该计算机程序产品可全部或部分的存储于封装于处理器当中的存储介质上,还可以全部或部分的存储在封装于处理器之外的存储介质中。A sixth aspect provides a computer program product containing instructions, the computer program product includes instructions for implementing the method in the first aspect or the second aspect above, and when running on a computer, the computer executes the first aspect above Or the method in the second aspect or any possible implementation thereof. The computer program product may be stored in whole or in part on a storage medium packaged in the processor, and may also be stored in whole or in part in a storage medium packaged outside the processor.
第七方面,本申请实施例提供一种无线通信系统,该系统包括上述方面涉及的编码装置和,译码装置。In a seventh aspect, an embodiment of the present application provides a wireless communication system, where the system includes the encoding device and the decoding device involved in the above aspect.
第八方面,提供了一种芯片,包括处理器,用于从存储器中调用并运行所述存储器中存储的指令,使得安装有所述芯片的通信设备执行上述各方面中的方法。第九方面,提供另一种芯片,包括:输入接口、输出接口、处理器,可选的,还包括存储器,所述输入接口、输出接口、所述处理器以及所述存储器之间通过内部连接通路相连,所述处理器用于执行所述存储器中的代码,当所述代码被执行时,所述处理器用于执行上述各方面中的方法。In an eighth aspect, a chip is provided, including a processor, configured to call from a memory and execute instructions stored in the memory, so that a communication device installed with the chip executes the methods in the above aspects. In the ninth aspect, another chip is provided, including: an input interface, an output interface, a processor, and optionally a memory, and the input interface, the output interface, the processor, and the memory are internally connected The processor is used to execute the code in the memory, and when the code is executed, the processor is used to execute the method in the above aspects.
第十方面,提供又一种芯片,包括一个或多个处理电路,以及输入输出接口。当所述芯片应用于编码装置中时,所述一个或多个处理电路可用于根据奇偶校验H矩阵进行编码,输入输出接口可用于输出编码后的码字C;当所述芯片应用于译码装置中时,所述一个或多个处理电路可用于根据奇偶校验H矩阵进行解码,输入输出接口可用于输入待译码的码字C,还用于输出译码后的信息比特。In a tenth aspect, there is provided another chip, including one or more processing circuits, and input and output interfaces. When the chip is used in an encoding device, the one or more processing circuits can be used for encoding according to the parity check H matrix, and the input and output interface can be used for outputting the encoded code word C; when the chip is used for decoding When in the coding device, the one or more processing circuits can be used for decoding according to the parity check H matrix, and the input and output interface can be used for inputting the code word C to be decoded, and also for outputting the decoded information bits.
第十一方面,提供一种装置,用于实现上述各实施例中的方法。In an eleventh aspect, an apparatus is provided for implementing the methods in the foregoing embodiments.
本申请实施例提供了新的LDPC编码方法,相较于5G NR LDPC码,可降低误码字率和计算复杂度,进一步提高系统可靠性和性能。The embodiment of the present application provides a new LDPC encoding method, which can reduce the bit error rate and calculation complexity compared with the 5G NR LDPC code, and further improve system reliability and performance.
附图说明Description of drawings
图1为本申请实施例提供的一种应用场景示意图;FIG. 1 is a schematic diagram of an application scenario provided by an embodiment of the present application;
图2为本申请实施例提供的一种LDPC编码方法流程示意图;Fig. 2 is a schematic flow chart of an LDPC encoding method provided by the embodiment of the present application;
图3为本申请实施例提供的大小为4x4的循环移位矩阵;FIG. 3 is a cyclic shift matrix with a size of 4x4 provided by the embodiment of the present application;
图4为本申请实施例提供的一种LDPC译码方法流程示意图;FIG. 4 is a schematic flow chart of an LDPC decoding method provided in an embodiment of the present application;
图5为本申请实施例提供的一个奇偶校验H矩阵对应的20行146列的母矩阵;Fig. 5 is the parent matrix of 20 rows and 146 columns corresponding to a parity check H matrix provided by the embodiment of the present application;
图6为本申请实施例提供的一种LDPC编码方法的示例;FIG. 6 is an example of an LDPC encoding method provided in an embodiment of the present application;
图7为本申请实施例提供的一种LDPC译码方法的示例;FIG. 7 is an example of an LDPC decoding method provided in an embodiment of the present application;
图8为本申请实施例提供的第一组LDPC码与5G NR LDPC码的误码率仿真性能比较;Fig. 8 is the bit error rate simulation performance comparison of the first group of LDPC codes provided by the embodiment of the present application and the 5G NR LDPC codes;
图9为本申请实施例提供的第二组LDPC码与5G NR LDPC码的误码率仿真性能比较;Fig. 9 is the bit error rate simulation performance comparison of the second group of LDPC codes provided by the embodiment of the present application and the 5G NR LDPC codes;
图10为本申请实施例提供的一种LDPC码编码装置示意图;FIG. 10 is a schematic diagram of an LDPC code encoding device provided in an embodiment of the present application;
图11为本申请实施例提供的另一种LDPC码编码装置示意图;FIG. 11 is a schematic diagram of another LDPC code encoding device provided in the embodiment of the present application;
图12为本申请实施例提供的一种LDPC码译码装置示意图;FIG. 12 is a schematic diagram of an LDPC code decoding device provided in an embodiment of the present application;
图13为本申请实施例提供的另一种LDPC码译码装置示意图;FIG. 13 is a schematic diagram of another LDPC code decoding device provided in the embodiment of the present application;
图14为本申请实施例提供的一种通信装置的示意图。FIG. 14 is a schematic diagram of a communication device provided by an embodiment of the present application.
具体实施方式Detailed ways
本申请的实施方式部分使用的术语仅用于对本申请的具体实施例进行解释,而非旨在限定本申请。The terms used in the embodiments of the present application are only used to explain specific embodiments of the present application, and are not intended to limit the present application.
本申请实施例提供一种低密度奇偶校验LDPC码编译码方法和编译码装置。应理解,本申请实施例的技术方案可以应用于各种移动通信系统,例如:通用移动通信系统(universal mobile telecommunication system,UMTS)、全球互联微波接入(worldwideinteroperability for microwave access,WiMAX)通信系统、以及未来的5G(fifthgeneration,5G)通信系统等。本申请实施例的技术方案还可以应用于无线局域网(wireless local area network,WLAN),并且本申请实施例可以适用于WLAN当前采用的国际电工电子工程学会(institute of electrical and electronics engineers,IEEE)802.11系列协议中的任意一种协议。例如,应用于802.11ay标准,或者,应用于802.11ay下一代的标准等。本申请实施例的编码装置和译码装置可以是上述通信系统中的网络节点,还可以是上述通信系统中网络节点内的芯片。Embodiments of the present application provide a low density parity check LDPC code encoding and decoding method and an encoding and decoding device. It should be understood that the technical solutions of the embodiments of the present application can be applied to various mobile communication systems, for example: universal mobile telecommunications system (universal mobile telecommunications system, UMTS), worldwide interconnection microwave access (worldwide interoperability for microwave access, WiMAX) communication system, And the future 5G (fifthgeneration, 5G) communication system, etc. The technical solution of the embodiment of the present application can also be applied to a wireless local area network (wireless local area network, WLAN), and the embodiment of the present application can be applied to the Institute of Electrical and Electronics Engineers (Institute of Electrical and Electronics Engineers, IEEE) 802.11 currently adopted by the WLAN. Any protocol in a series of protocols. For example, it is applied to the 802.11ay standard, or it is applied to the standard of the next generation of 802.11ay. The encoding device and the decoding device in the embodiment of the present application may be a network node in the above-mentioned communication system, or may be a chip in the network node in the above-mentioned communication system.
本申请实施例以WLAN通信系统为例进行说明。WLAN可以包括一个或多个基本服务集(basic service set,BSS),基本服务集中的网络节点包括接入点(access point,AP)和站点(station,STA),则本申请实施例的编码装置和译码装置可以是WLAN系统中的AP或STA,还可以是位于AP或STA内的芯片。本申请实施例的方案既可以运用于AP与STA之间的通信,还可以运用于AP与AP之间的通信,STA与STA之间的通信,且可以是一对一的通信,还可以是一对多和多对多的通信。例如,可以是一个AP与一个STA之间通信(例如图1左所示),可以是AP与多个STA同时通信(如图1右所示),还可以是多个AP与多个STA之间同时通信,还可以是多个STA与AP之间同时通信。The embodiment of the present application is described by taking a WLAN communication system as an example. The WLAN may include one or more basic service sets (basic service set, BSS), and the network nodes in the basic service set include an access point (access point, AP) and a station (station, STA), then the encoding device of the embodiment of the present application The sum and decoding device may be an AP or STA in the WLAN system, and may also be a chip located in the AP or STA. The solution of the embodiment of the present application can be applied to the communication between AP and STA, the communication between AP and AP, the communication between STA and STA, and it can be one-to-one communication, or it can be One-to-many and many-to-many communication. For example, it can be communication between one AP and one STA (such as shown on the left of Figure 1), it can be simultaneous communication between an AP and multiple STAs (as shown on the right of Figure 1), or it can be between multiple APs and multiple STAs. Simultaneous communication between STAs, or simultaneous communication between multiple STAs and APs.
AP为具有无线收发功能的通信装置,可以为定向多吉比特(directional multi-gigabit,DMG)AP/PCP和增强型定向多吉比特(enhanced directional multi-gigabit,EDMG)AP/PCP,还可以是支持60GHz的AP,但本申请实施例对此不作限定。该AP也可以称为基站。STA可以为具有无线收发功能的通信装置,例如,可以是支持60GHz通信的无线通信装置。该STA也可以称为用户单元、接入终端、移动站、移动台、远方站、远程终端、移动设备、用户终端、终端、无线通信设备、用户代理、用户装置或用户设备(user equipment,UE)。AP is a communication device with wireless transceiver function, which can be directional multi-gigabit (directional multi-gigabit, DMG) AP/PCP and enhanced directional multi-gigabit (enhanced directional multi-gigabit, EDMG) AP/PCP, and can also support 60GHz AP, but this embodiment of the application does not limit it. The AP can also be called a base station. The STA may be a communication device having a wireless transceiver function, for example, may be a wireless communication device supporting 60 GHz communication. The STA may also be called a subscriber unit, an access terminal, a mobile station, a mobile station, a remote station, a remote terminal, a mobile device, a user terminal, a terminal, a wireless communication device, a user agent, a user device, or a user equipment (UE) ).
下面结合更多的附图,对本申请实施例的技术方案进一步详细说明。The technical solutions of the embodiments of the present application will be further described in detail below in conjunction with more drawings.
图2示出了本申请实施例提供的一种低密度奇偶校验LDPC码的编码方法,可选的,该方法可以应用于高频无线局域网通信系统中,例如60GHz无线局域网通信系统中,该方法包括:Figure 2 shows a method for encoding a low-density parity-check LDPC code provided by an embodiment of the present application. Optionally, this method can be applied to a high-frequency wireless local area network communication system, such as a 60GHz wireless local area network communication system. Methods include:
S201,获取k个信息比特,k=8064;S201, acquire k information bits, k=8064;
可选的,编码装置,在所述k个信息比特之前填充s个待缩短比特,所述s个待缩短比特的值为0,从而构成(s+k)个待编码比特。其中s为大于等于0的整数,s为Z的正整数倍。Optionally, the encoding device fills s bits to be shortened before the k information bits, and the s bits to be shortened have a value of 0, thereby forming (s+k) bits to be encoded. Where s is an integer greater than or equal to 0, and s is a positive integer multiple of Z.
一个示例中,k个信息比特可以全部为有效载荷;又一个示例中,k个信息比特中可以有部分比特是有效载荷比特,剩余部分比特可以是填充比特,有效载荷比特和剩余部分比特共同构成待编码的k个信息比特。In one example, all of the k information bits may be payloads; in another example, some of the k information bits may be payload bits, and the remaining bits may be padding bits, and the payload bits and the remaining bits together form k information bits to be encoded.
S202,根据奇偶校验H矩阵,对所述k个信息比特进行LDPC编码,获取进行LDPC编码后的码字C,所述码字C的码长为n,码率R为k/n,n为大于k的正整数;S202. Perform LDPC encoding on the k information bits according to the parity check H matrix, and obtain a code word C after LDPC encoding. The code length of the code word C is n, and the code rate R is k/n, n is a positive integer greater than k;
具体的,H矩阵为(n+s-k)×(n+s)的奇偶校验矩阵。其中,s为待缩短的比特所对应的H矩阵的列数。本申请实施例中,码字还可以称为编码后的比特序列。Specifically, the H matrix is a (n+s-k)×(n+s) parity check matrix. Wherein, s is the column number of the H matrix corresponding to the bits to be shortened. In this embodiment of the present application, a codeword may also be referred to as an encoded bit sequence.
可选的,S203,编码装置输出编码后的码字C。Optionally, in S203, the encoding device outputs the encoded codeword C.
一个示例中,编码装置可以对码字C进行处理后发送出去;又一个示例中,编码装置可以输出码字C到射频电路进行处理后发送出去。In one example, the encoding device may process the codeword C and send it out; in another example, the encoding device may output the codeword C to a radio frequency circuit for processing and then send it out.
可选的,对(k+s)个待编码比特,基于奇偶校验矩阵进行LDPC编码,生成(n-k)个奇偶校验比特。(k+s)个待编码比特与(n-k)个校验比特构成码长为(s+n)的码字C1,删除码字C1中的前s个待缩短比特,得到码长为n的码字C,码字C包括(n-k)个奇偶校验比特和k个信息比特。所述前s个待缩短比特与奇偶校验H矩阵中的前s列相对应,码率R为k/n。需要说明的是,编码时该s个比特取值均为’0’,编码完成后的码字中该s个比特的值仍为0,“缩短”指的是将这s个待缩短的取值为’0’的比特删除,因此删除比特也可以称为缩短比特。Optionally, perform LDPC encoding on the (k+s) bits to be encoded based on the parity check matrix to generate (nk) parity check bits. (k+s) bits to be encoded and (nk) check bits constitute a codeword C 1 with a code length of (s+n), and the first s bits to be shortened in the codeword C 1 are deleted to obtain a code length of A code word C of n, the code word C includes (nk) parity check bits and k information bits. The first s bits to be shortened correspond to the first s columns in the parity check H matrix, and the code rate R is k/n. It should be noted that the values of the s bits are all '0' during encoding, and the values of the s bits in the codeword after encoding are still 0. "Shortening" refers to shortening the s bits to be shortened. Bits with a value of '0' are deleted, so deleted bits may also be referred to as shortened bits.
奇偶校验矩阵H可进一步划分为大小为ZxZ的子方阵。子方阵是单位矩阵的循环移位,或是具有全零项的空子矩阵。单位矩阵记为P0,单位矩阵P0的循环置换矩阵Pi表示通过将单位矩阵P0向右循环移动i个元素,称为循环移位矩阵(cyclic permutation matrices,CPM)。循环移位矩阵CPM的下标i表示单位矩阵向右循环移位的位数。The parity check matrix H can be further divided into sub-square matrices with a size of ZxZ. A subsquare is a cyclic shift of the identity matrix, or an empty submatrix with all zero entries. The identity matrix is denoted as P0, and the cyclic permutation matrix Pi of the identity matrix P0 means that by moving the identity matrix P0 to the right by i elements, it is called a cyclic shift matrix (cyclic permutation matrices, CPM). The subscript i of the cyclic shift matrix CPM represents the number of bits that the identity matrix is cyclically shifted to the right.
Z是循环移位矩阵CPM或子方阵的大小。可选的,本申请实施例中,子方阵的大小为64或42。为方便描述,以4x4的CPM为例,P0,P1,P2,P3可如图3所示,相类似地,64x64的CPM和42x42的CPM可参考图3的方式获得,此处不再赘述。Z is the size of the cyclic shift matrix CPM or sub-square. Optionally, in this embodiment of the present application, the size of the sub-square matrix is 64 or 42. For the convenience of description, taking 4x4 CPM as an example, P0, P1, P2, and P3 can be shown in Figure 3. Similarly, 64x64 CPM and 42x42 CPM can be obtained by referring to Figure 3, and will not be repeated here.
以ZxZ阶子方阵表示奇偶校验H矩阵的矩阵形式,可以称为母矩阵,母矩阵包括(n+s-k)/Z行,(n+s)/Z列,母矩阵的每一个元素为一个ZxZ阶的子方阵。The matrix form of the parity check H matrix is represented by a ZxZ order sub-square matrix, which can be called a mother matrix. The mother matrix includes (n+s-k)/Z rows and (n+s)/Z columns. Each element of the mother matrix is A sub-square matrix of order ZxZ.
本申请实施例提供了一种LDPC编码方法,其码长更长,且具有更低的误码率和更好的性能,因此可有效提升系统可靠性和传输性能。The embodiment of the present application provides an LDPC encoding method, which has a longer code length, lower bit error rate, and better performance, and thus can effectively improve system reliability and transmission performance.
图4示出了本申请实施例提供的一种低密度奇偶校验LDPC码的译码方法,包括:Fig. 4 shows the decoding method of a kind of low density parity check LDPC code provided by the embodiment of the present application, including:
S401,获取经过LDPC编码后的码字C;S401. Obtain the codeword C encoded by LDPC;
译码装置接收该码字C,其中,码字C的长度为n,包括k个信息比特和(n-k)个奇偶校验比特。The decoding device receives the codeword C, wherein the codeword C has a length of n and includes k information bits and (n-k) parity check bits.
承载码字C的信号可以是经由射频电路部分处理后,再输入译码装置进行译码处理;还可以是承载码字C的信号由译码装置接收,并经由射频处理后再进行译码处理。The signal carrying the code word C may be partially processed by the radio frequency circuit, and then input to the decoding device for decoding processing; it may also be that the signal carrying the code word C is received by the decoding device, and then decoded after being processed by the radio frequency .
S402,在码字C前面填充值为0的s个待缩短比特,得到码字C1;S402, filling s bits to be shortened with a value of 0 in front of the codeword C to obtain the codeword C 1 ;
具体的,在码字C前面填充值为0的s个待缩短比特,构成码长为(s+n)的码字C1;Specifically, s bits to be shortened with a value of 0 are filled in front of the codeword C to form a codeword C 1 with a code length of (s+n);
S403,利用奇偶校验H矩阵对码字C1进行解码,获得解码后的k个信息比特;S403, using the parity check H matrix to decode the code word C 1 , and obtain k information bits after decoding;
具体的,利用奇偶校验H矩阵对码字C1进行解码后得到(s+k)个译码比特,删除(s+k)个译码比特中的前s个比特,获得解码后的k个信息比特;具体的,H矩阵为(n+s-k)×(n+s)奇偶校验矩阵,奇偶校验矩阵H可进一步划分为大小为ZxZ的子方阵。子方阵是单位矩阵的循环移位,或是具有全零项的空子矩阵。单位矩阵记为P0,单位矩阵P0的循环置换矩阵Pi表示通过将单位矩阵P0向右循环移动i个元素,称为循环移位矩阵。循环移位矩阵CPM的下标i表示单位矩阵向右循环移位的位数。Z为子方阵或循环移位矩阵的大小。可选的,本申请实施例中,Z的取值为64或42。以ZxZ阶子方阵表示奇偶校验矩阵的矩阵形式,可以称为母矩阵,母矩阵包括(n+s-k)/Z行,(n+s)/Z列,母矩阵的每一个元素为一个ZxZ阶的子方阵。Specifically, use the parity check H matrix to decode the codeword C 1 to obtain (s+k) decoding bits, delete the first s bits in the (s+k) decoding bits, and obtain the decoded k information bits; specifically, the H matrix is a (n+sk)×(n+s) parity check matrix, and the parity check matrix H can be further divided into sub-square matrices with a size of ZxZ. A subsquare is a cyclic shift of the identity matrix, or an empty submatrix with all zero entries. The identity matrix is denoted as P0, and the cyclic permutation matrix Pi of the identity matrix P0 means that by moving the identity matrix P0 to the right by i elements, it is called a cyclic shift matrix. The subscript i of the cyclic shift matrix CPM represents the number of bits that the identity matrix is cyclically shifted to the right. Z is the size of the subsquare or cyclic shift matrix. Optionally, in the embodiment of the present application, the value of Z is 64 or 42. The matrix form of the parity check matrix is represented by a ZxZ order sub-square matrix, which can be called a mother matrix. The mother matrix includes (n+sk)/Z rows and (n+s)/Z columns. Each element of the mother matrix is a A sub-square matrix of order ZxZ.
本申请实施例相较于802.11ay标准和802.11ad标准,设计了码长更长的LDPC码编码方法,因此误码字率更低,通信系统的可靠性和系统性能进一步得到提升。且在k个信息比特前填充s个待缩短比特,有助于提高译码装置的译码性能,降低误比特率或误码字率。Compared with the 802.11ay standard and the 802.11ad standard, the embodiment of the present application designs an LDPC code encoding method with a longer code length, so the bit error rate is lower, and the reliability and system performance of the communication system are further improved. And filling s bits to be shortened before the k information bits helps to improve the decoding performance of the decoding device and reduce the bit error rate or word error rate.
下面进一步说明本申请实施例提供的两组LDPC码编码方案,具体包括奇偶校验矩阵的设计。The following further describes the two sets of LDPC code coding schemes provided by the embodiment of the present application, specifically including the design of the parity check matrix.
第一组LDPC码编码方案:码率R分别为R=7/8,13/16,3/4,5/8,1/2,且CPM为64x64;The first group of LDPC code encoding schemes: the code rates R are respectively R=7/8, 13/16, 3/4, 5/8, 1/2, and the CPM is 64x64;
第二组LDPC码编码方案:码率R分别为R=7/8,13/16,3/4,5/8,1/2,且CPM为42x42;其中,两组LDPC码的信息比特长度均为k=8064比特。The second group of LDPC code encoding schemes: the code rate R is respectively R=7/8, 13/16, 3/4, 5/8, 1/2, and the CPM is 42x42; wherein, the information bit length of the two groups of LDPC codes Both are k=8064 bits.
首先介绍第一组LDPC码编码方案,码率R分别为R=7/8,13/16,3/4,5/8,1/2,且CPM为64x64,信息比特长度k=8064。Firstly, the first group of LDPC code coding schemes are introduced, the code rates R are R=7/8, 13/16, 3/4, 5/8, 1/2, and the CPM is 64x64, and the information bit length k=8064.
示例一:码率为7/8,循环移位矩阵(CPM)的大小为64,信息比特长度为k=8064比特。Example 1: the code rate is 7/8, the size of the cyclic shift matrix (CPM) is 64, and the information bit length is k=8064 bits.
码率R=7/8的LDPC码,其奇偶校验H矩阵总的列的数目N1=(n+s),N1为9344,对应母矩阵总的列数为N0=N1/64=146,其奇偶校验H矩阵总的行的数目M1=(n+s-k),M1为1280,对应母矩阵总的行数为M0=M1/64=20,k=8064个信息比特对应H矩阵中的8064列,对应母矩阵中的k/Z=20列。该奇偶校验H矩阵的最大行重为23,即H矩阵的每行中最多23个1。The LDPC code of code rate R=7/8, the total column number N1=(n+s) of its parity-check H matrix, N1 is 9344, and the total column number corresponding mother matrix is N0=N1/64=146, The total row number M1=(n+s-k) of its parity check H matrix, M1 is 1280, and the total row number corresponding to the mother matrix is M0=M1/64=20, and k=8064 information bits correspond to in the H matrix 8064 columns, corresponding to k/Z=20 columns in the mother matrix. The maximum row weight of the parity check H matrix is 23, that is, there are at most 23 1s in each row of the H matrix.
根据奇偶校验H矩阵,生成1152个奇偶校验比特,获得码长为n1=9344的LDPC码码字C1,码字C1包括s个待缩短比特、8064个信息比特和1152个奇偶校验比特;对C1进行缩短,即删除C1的前s个待缩短比特,得到其缩短后的码字C,码字C包括8064个信息比特和1152个奇偶校验比特,码字C的真实码长为n=9216比特,所需缩短比特为C1的前s=128比特,即为母矩阵的前2列对应的C1的前128个比特,这前128个比特的值为0。According to the parity check H matrix, 1152 parity check bits are generated, and the code length is n1=9344 LDPC code word C 1 , code word C 1 includes s bits to be shortened, 8064 information bits and 1152 parity check bits check bits; shorten C 1 , that is, delete the first s bits to be shortened of C 1 , and obtain its shortened codeword C. Codeword C includes 8064 information bits and 1152 parity check bits. The real code length is n=9216 bits, and the required shortening bit is the first s=128 bits of C 1 , which is the first 128 bits of C 1 corresponding to the first 2 columns of the mother matrix, and the value of the first 128 bits is 0 .
下面给出码率为7/8的奇偶校验H矩阵,奇偶校验H矩阵的矩阵形式可以表示为如下第0行至第19行的形式,其中,行的编号和列的编号都从0开始。如下第i行中的各个数字表示奇偶校验H矩阵第64i行中值为‘1’的列位置,且0≤i≤19。H矩阵中第(64i+1)行至第(64i+63)行中‘1’的位置为H矩阵中的第64i行按照循环移位矩阵(CPM)经过循环移位得到。例如,第0行中的数字43表示奇偶校验H矩阵第0行第43列的位置取值为‘1’,第0行中的数字103表示奇偶校验H矩阵第0行中第103列的位置取值为‘1’。H矩阵第0行第43列的位置取值为‘1’,按照循环移位矩阵(CPM)经过循环移位,则可以得到H矩阵中第1行中取值为1的列位置为44,依次类推,而H矩阵中第21行中1的列位置为0。The parity check H matrix with a code rate of 7/8 is given below. The matrix form of the parity check H matrix can be expressed as the following form from the 0th row to the 19th row, where the number of the row and the number of the column start from 0 start. Each number in the i-th row as follows represents the column position with the value '1' in the 64ith row of the parity check H matrix, and 0≤i≤19. The position of '1' in the (64i+1)th row to (64i+63)th row in the H matrix is obtained by cyclic shifting in the 64ith row in the H matrix according to the cyclic shift matrix (CPM). For example, the
按照如上规则,奇偶校验矩阵H表示如下:According to the above rules, the parity check matrix H is expressed as follows:
如前所述,奇偶校验H矩阵前128列所对应的128个比特需要缩短处理,即编码前该128列对应的比特均为’0’,编码完成后再将这些’0’比特删除。上述H矩阵还可以母矩阵的形式来表示。如图5所示。母矩阵包括20行146列,母矩阵的行和列的编号从0开始,分别为第0行至第19行,第0列至第145列。母矩阵中的每一个元素为一个64x64阶的子方阵,子方阵是单位矩阵的循环置换,或是具有全零项的空子矩阵。图5中,空白部分表示64x64的全零矩阵,而非零数值表示64x64循环移位矩阵的循环移位系数。例如,母矩阵中第1行第1列的非零数值43表示循环移位矩阵的循环移位系数为43,即为单位矩阵向右循环移位的位数为43,得到循环移位矩阵P43。128个待缩短比特对应母矩阵中的前2列(第0列和第1列),k个信息比特对应母矩阵的第2列至第127列,奇偶校验比特对应母矩阵的第128列至145列。需要说明的是,H矩阵还可以有其他的变形,例如,H矩阵中的第0行至第19行中行的次序是可以相互交换,也就是说,H矩阵中的所有行的顺序不仅限于示例一给出的情形,例如,H矩阵的20行可以依次为:第19行,第18行,第17行,…第0行;或,第1行,第2行,…,第19行,第0行等。H矩阵中的列和列的次序也是可以交换的,本申请实施例并不具体限定。As mentioned above, the 128 bits corresponding to the first 128 columns of the parity check H matrix need to be shortened, that is, the bits corresponding to the 128 columns are all '0' before encoding, and these '0' bits are deleted after encoding is completed. The above H matrix can also be expressed in the form of a parent matrix. As shown in Figure 5. The mother matrix includes 20 rows and 146 columns, and the numbers of the rows and columns of the mother matrix start from 0, and are respectively the 0th row to the 19th row, and the 0th column to the 145th column. Each element in the mother matrix is a sub-square matrix of order 64x64, and the sub-square matrix is a cyclic permutation of the identity matrix, or an empty sub-matrix with all zero entries. In FIG. 5 , the blank part represents the 64x64 all-zero matrix, and the non-zero value represents the cyclic shift coefficient of the 64x64 cyclic shift matrix. For example, the
示例二:码率为13/16,循环移位矩阵(CPM)的大小为64,信息比特长度为k=8064比特。Example 2: the code rate is 13/16, the size of the cyclic shift matrix (CPM) is 64, and the information bit length is k=8064 bits.
码率R=13/16的LDPC码,其奇偶校验H矩阵总的列的数目N1=(n+s),N1为10176,对应母矩阵总的列数为N0=N1/64=159,其奇偶校验H矩阵总的行的数目M1=(n+s-k),M1为2112,对应母矩阵总的行数为M0=M1/64=33,k个信息比特对应H矩阵中的k列,对应母矩阵中的k/Z列。该奇偶校验H矩阵的最大行重为16,即H矩阵的每行中最多16个1。The LDPC code of code rate R=13/16, the number N1=(n+s) of the total column of its parity check H matrix, N1 is 10176, and the total column number of corresponding mother matrix is N0=N1/64=159, The total row number M1=(n+s-k) of its parity-check H matrix, M1 is 2112, and the total row number corresponding to the mother matrix is M0=M1/64=33, and k information bits correspond to k columns in the H matrix , corresponding to the k/Z columns in the parent matrix. The maximum row weight of the parity check H matrix is 16, that is, there are at most 16 1s in each row of the H matrix.
根据奇偶校验H矩阵,生成1920个奇偶校验比特,获得码长为n0=10176的LDPC码码字C1,对C1前s个比特进行缩短,得到其缩短后的码字C,码字C的真实码长为n=9984比特,所需缩短的比特为C1的前s=192比特,即为母矩阵的前3列对应的C1中的前192个比特,这前192个比特的取值为0。According to the parity check H matrix, generate 1920 parity check bits, obtain the LDPC code word C 1 with code length n0=10176, shorten the first s bits of C 1 , and obtain the shortened code word C, the code The real code length of word C is n=9984 bits, and the bits that need to be shortened are the first s=192 bits of C 1 , which is the first 192 bits in C 1 corresponding to the first 3 columns of the mother matrix, these first 192 bits The value of the bit is 0.
下面给出码率为13/16的奇偶校验H矩阵,奇偶校验H矩阵的矩阵形式可以表示为如下第0行至第32行的形式,其中,行的编号和列的编号都从0开始。如下第i行中的各个数字表示奇偶校验H矩阵第64i行中值为‘1’的列位置,0≤i≤32。H矩阵中第(64i+1)行至第(64i+63)行中‘1’的位置为H矩阵中的第64i行按照循环移位矩阵(CPM)经过循环移位得到。例如,第0行中的数字17表示奇偶校验H矩阵第0行第17列的位置取值为‘1’,第0行中的数字156表示奇偶校验H矩阵第0行中第156列的位置取值为‘1’。H矩阵第0行第17列的位置取值为‘1’,按照循环移位矩阵(CPM)经过循环移位,则可以得到H矩阵中第1行中取值为1的列位置为18,依次类推,而H矩阵中第47行中取值为1的列位置为0。另外,行末尾的’-1’不表示任何含义,可以删除,即,第0行为:17 156 413 1371 2211 2561 3397 3910 4614 6070 62446662 7213 7430 8128。The parity check H matrix with a code rate of 13/16 is given below. The matrix form of the parity check H matrix can be expressed as the following form from the 0th row to the 32nd row, where the number of the row and the number of the column are all from 0 start. Each number in the i-th row as follows represents the column position of the value '1' in the 64th row of the parity check H matrix, 0≤i≤32. The position of '1' in the (64i+1)th row to (64i+63)th row in the H matrix is obtained by cyclic shifting in the 64ith row in the H matrix according to the cyclic shift matrix (CPM). For example, the
按照如上规则,其校验矩阵表示如下:According to the above rules, the parity check matrix is expressed as follows:
如前所述,奇偶校验H矩阵前192列所对应的192个比特需要缩短处理,编码时该192列对应的192个比特取值均为’0’,编码完成后再将这些’0’比特删掉。即编码后输出的码字C不包括这192个待缩短比特。As mentioned earlier, the 192 bits corresponding to the first 192 columns of the parity check H matrix need to be shortened. During encoding, the 192 bits corresponding to the 192 columns are all '0', and these '0' Bit deleted. That is, the codeword C output after encoding does not include the 192 bits to be shortened.
可以理解的,上述H矩阵也可以以母矩阵的形式表示。需要说明的是,H矩阵还可以有其他的变形,H矩阵中的行和行的次序可以相互交换,H矩阵中的列和列的次序也可以相互交换,本申请实施例并不具体限定。It can be understood that the above H matrix can also be expressed in the form of a parent matrix. It should be noted that the H matrix can also have other deformations, the order of rows and rows in the H matrix can be exchanged, and the order of columns and columns in the H matrix can also be exchanged, which is not specifically limited in the embodiment of the present application.
示例三:码率为3/4,循环移位矩阵(CPM)的大小为64,信息比特长度为k=8064比特。Example 3: the code rate is 3/4, the size of the cyclic shift matrix (CPM) is 64, and the information bit length is k=8064 bits.
码率R=3/4的LDPC码,其奇偶校验H矩阵总的列的数目N1=(n+s),N1为11008,对应母矩阵总的列数为N0=N1/64=172,其奇偶校验H矩阵总的行的数目M1=(n+s-k),M1为2944,对应母矩阵总的行数为M0=M1/64=46,k个信息比特对应H矩阵中的k列,对应母矩阵中的k/Z列。该奇偶校验H矩阵的最大行重为13,即H矩阵中每行中最多13个1。The LDPC code of code rate R=3/4, the number N1=(n+s) of the total column of its parity check H matrix, N1 is 11008, and the total column number of corresponding mother matrix is N0=N1/64=172, The total row number M1=(n+s-k) of its parity check H matrix, M1 is 2944, and the total row number corresponding to the mother matrix is M0=M1/64=46, and k information bits correspond to k columns in the H matrix , corresponding to the k/Z columns in the mother matrix. The maximum row weight of the parity check H matrix is 13, that is, there are at most 13 1s in each row of the H matrix.
根据奇偶校验H矩阵,生成2688个奇偶校验比特,获得码长为n0=11008的LDPC码码字C1,码字C1包括:s个待缩短比特、8064个信息比特、2688个奇偶校验比特;对C1前s个比特进行缩短,得到其缩短后的码字C,码字C的真实码长为n=10752比特,包括8064个信息比特和2688个奇偶校验比特,所需缩短比特为C1的前s=256比特,即为母矩阵的前4列对应C1的前256个比特,这前256个比特的取值为0。According to the parity check H matrix, 2688 parity check bits are generated, and the LDPC code word C 1 with a code length of n0=11008 is obtained, and the code word C 1 includes: s bits to be shortened, 8064 information bits, and 2688 parity bits check bits; the first s bits of C1 are shortened to obtain its shortened codeword C, the real code length of codeword C is n=10752 bits, including 8064 information bits and 2688 parity check bits, so The bits to be shortened are the first s=256 bits of C 1 , that is, the first 4 columns of the mother matrix correspond to the first 256 bits of C 1 , and the value of the first 256 bits is 0.
下面给出码率为3/4的奇偶校验H矩阵,奇偶校验H矩阵的矩阵形式可以表示为如下第0行至第45行的形式,其中,行的编号和列的编号都从0开始。如下第i行中的各个数字表示奇偶校验H矩阵第64i行中值为‘1’的列位置,0≤i≤45。H矩阵中第(64i+1)行至第(64i+63)行中‘1’的位置为H矩阵中的第64i行按照循环移位矩阵(CPM)经过循环移位得到。例如,第0行中的数字53表示奇偶校验H矩阵第0行第53列的位置取值为‘1’,第0行中的数字199表示奇偶校验H矩阵第0行中第199列的位置取值为‘1’。H矩阵第0行第53列的位置取值为‘1’,按照循环移位矩阵(CPM)经过循环移位,则可以得到H矩阵中第1行中取值为1的列位置为54,依次类推,而H矩阵中第11行中取值为1的列位置为0。另外,行末尾的’-1’不表示任何含义,也可以删除。The parity check H matrix with a code rate of 3/4 is given below, and the matrix form of the parity check H matrix can be expressed as the following form from the 0th row to the 45th row, where the number of the row and the number of the column start from 0 start. Each number in the i-th row as follows represents the column position of the value '1' in the 64th row of the parity check H matrix, 0≤i≤45. The position of '1' in the (64i+1)th row to (64i+63)th row in the H matrix is obtained by cyclic shifting in the 64ith row in the H matrix according to the cyclic shift matrix (CPM). For example, the
按照如上规则,奇偶校验H矩阵表示如下:According to the above rules, the parity check H matrix is expressed as follows:
如前所述,奇偶校验H矩阵前256列所对应的256个比特需要缩短处理,编码时该256列对应的比特取值均为’0’,编码完成后再将这些’0’比特删掉。As mentioned above, the 256 bits corresponding to the first 256 columns of the parity check H matrix need to be shortened. During encoding, the values of the bits corresponding to the 256 columns are all '0', and these '0' bits are deleted after the encoding is completed. Lose.
可以理解的,上述H矩阵也可以以母矩阵的形式表示。需要说明的是,H矩阵还可以有其他的变形,H矩阵中的行和行的次序可以相互交换,H矩阵中的列和列的次序也可以相互交换,本申请实施例并不具体限定。It can be understood that the above H matrix can also be expressed in the form of a parent matrix. It should be noted that the H matrix can also have other deformations, the order of rows and rows in the H matrix can be exchanged, and the order of columns and columns in the H matrix can also be exchanged, which is not specifically limited in the embodiment of the present application.
示例四:码率为5/8,循环移位矩阵(CPM)的大小为64,信息比特长度为k=8064比特。Example 4: the code rate is 5/8, the size of the cyclic shift matrix (CPM) is 64, and the information bit length is k=8064 bits.
码率R=5/8的LDPC码,其奇偶校验H矩阵总的列的数目N1=(n+s),N1为13504,对应母矩阵总的列数为N0=N1/64=211,其奇偶校验H矩阵总的行的数目M1=(n+s-k),M1为5440,对应母矩阵总的行数为M0=M1/64=85,k个信息比特对应H矩阵中的k列,对应母矩阵中的k/Z列。该奇偶校验H矩阵的最大行重为8,即每行中最多8个1。The LDPC code of code rate R=5/8, the total column number N1=(n+s) of its parity-check H matrix, N1 is 13504, and the total column number corresponding mother matrix is N0=N1/64=211, The total row number M1=(n+s-k) of its parity check H matrix, M1 is 5440, and the total row number corresponding to the mother matrix is M0=M1/64=85, and k information bits correspond to k columns in the H matrix , corresponding to the k/Z columns in the parent matrix. The maximum row weight of the parity check H matrix is 8, that is, there are at most 8 1s in each row.
根据奇偶校验H矩阵,生成4864个奇偶校验比特,获得码长为n0=13504的LDPC码码字C1,码字C1包括:s个待删除比特、8064个信息比特和4864个奇偶校验比特;对C1前s个比特进行缩短,得到其缩短后的码字C,码字C的真实码长为n=12928比特,包括8064个信息比特和4864个奇偶校验比特,所需缩短比特为C1的前s=576比特,即为母矩阵的前8列对应的C1的前576个比特,这前576个比特的取值为0。According to the parity check H matrix, 4864 parity check bits are generated, and the LDPC code word C 1 with a code length of n0=13504 is obtained, and the code word C 1 includes: s bits to be deleted, 8064 information bits and 4864 parity check bits; the first s bits of C1 are shortened to obtain its shortened codeword C, the real code length of codeword C is n=12928 bits, including 8064 information bits and 4864 parity check bits, so The bits to be shortened are the first s=576 bits of C 1 , that is, the first 576 bits of C 1 corresponding to the first 8 columns of the mother matrix, and the value of the first 576 bits is 0.
下面给出码率为5/8的奇偶校验H矩阵,奇偶校验H矩阵的矩阵形式可以表示为如下第0行至第84行的形式,其中,行的编号和列的编号都从0开始。如下第i行中的各个数字表示奇偶校验H矩阵第64i行中值为‘1’的列位置,0≤i≤84。H矩阵中第(64i+1)行至第(64i+63)行中‘1’的位置为H矩阵中的第64i行按照循环移位矩阵(CPM)经过循环移位得到。例如,第0行中的数字430表示奇偶校验H矩阵第0行第430列的位置取值为‘1’,第0行中的数字1216表示奇偶校验H矩阵第0行中第1216列的位置取值为‘1’。H矩阵第0行第430列的位置取值为‘1’,按照循环移位矩阵(CPM)经过循环移位,则可以得到H矩阵中第1行中取值为1的列位置为431,依次类推,而H矩阵中第18行中取值为1的列位置为384。另外,行末尾的’-1’不表示任何含义,也可以删除。A parity check H matrix with a code rate of 5/8 is given below. The matrix form of the parity check H matrix can be expressed as the following form from the 0th row to the 84th row, where the number of the row and the number of the column start from 0 start. Each number in the i-th row as follows represents the column position of the value '1' in the 64th row of the parity check H matrix, 0≤i≤84. The position of '1' in the (64i+1)th row to (64i+63)th row in the H matrix is obtained by cyclic shifting in the 64ith row in the H matrix according to the cyclic shift matrix (CPM). For example, the number 430 in the 0th row indicates that the position of the 430th column in the 0th row of the parity check H matrix is '1', and the number 1216 in the 0th row indicates the 1216th column in the 0th row of the parity check H matrix The value of the position is '1'. The position of the 430th column in
按照如上规则,奇偶校验H矩阵表示如下:According to the above rules, the parity check H matrix is expressed as follows:
如前所述,奇偶校验H矩阵前576列所对应的576个比特需要缩短处理,编码时该576列对应的比特取值均为’0’,编码完成后再将这些’0’比特删掉。As mentioned above, the 576 bits corresponding to the first 576 columns of the parity check H matrix need to be shortened, and the values of the bits corresponding to the 576 columns are all '0' during encoding, and these '0' bits are deleted after the encoding is completed. Lose.
可以理解的,上述H矩阵也可以以母矩阵的形式表示。需要说明的是,H矩阵还可以有其他的变形,H矩阵中的行和行的次序可以相互交换,H矩阵中的列和列的次序也可以相互交换,本申请实施例并不具体限定。It can be understood that the above H matrix can also be expressed in the form of a parent matrix. It should be noted that the H matrix can also have other deformations, the order of rows and rows in the H matrix can be exchanged, and the order of columns and columns in the H matrix can also be exchanged, which is not specifically limited in the embodiment of the present application.
示例五:码率为1/2,循环移位矩阵(CPM)的大小为64,信息比特长度为k=8064比特。Example 5: the code rate is 1/2, the size of the cyclic shift matrix (CPM) is 64, and the information bit length is k=8064 bits.
码率R=1/2的LDPC码,其奇偶校验H矩阵总的列的数目N1=(n+s),N1为17088,对应母矩阵总的列数为N0=N1/64=267,其奇偶校验H矩阵总的行的数目M1=(n+s-k),M1为9024,对应母矩阵总的行数为M0=M1/64=141,k个信息比特对应H矩阵中的k列,对应母矩阵中的k/Z列。该奇偶校验H矩阵的最大行重为7,即每行中最多7个1。The LDPC code of code rate R=1/2, the total column number N1=(n+s) of its parity-check H matrix, N1 is 17088, and the total column number corresponding to mother matrix is N0=N1/64=267, The total row number M1=(n+s-k) of its parity check H matrix, M1 is 9024, and the total row number corresponding to the mother matrix is M0=M1/64=141, and k information bits correspond to k columns in the H matrix , corresponding to the k/Z columns in the mother matrix. The maximum row weight of the parity-check H matrix is 7, that is, there are at most 7 1s in each row.
根据奇偶校验H矩阵,生成8064个奇偶校验比特,获得码长为n0=17088的LDPC码码字C1,码字C1包括:s个待缩短比特、8064个信息比特和8064个奇偶校验比特;对C1前s个比特进行缩短,得到其缩短后的码字C,码字C的真实码长为n=16128比特,包括8064个信息比特和8064个奇偶校验比特。所需缩短比特为C1的前s=960比特,即为母矩阵的前15列对应的C1的前960个比特,这前960个比特的取值为0。According to the parity check H matrix, 8064 parity check bits are generated to obtain an LDPC code word C 1 with a code length of n0=17088. The code word C 1 includes: s bits to be shortened, 8064 information bits and 8064 parity Parity bits; the first s bits of C 1 are shortened to obtain its shortened code word C, the real code length of the code word C is n=16128 bits, including 8064 information bits and 8064 parity bits. The required shortening bits are the first s=960 bits of C 1 , that is, the first 960 bits of C 1 corresponding to the first 15 columns of the mother matrix, and the value of the first 960 bits is 0.
下面给出码率为1/2的奇偶校验H矩阵,奇偶校验H矩阵的矩阵形式可以表示为如下第0行至第140行的形式,其中,行的编号和列的编号都从0开始。如下第i行中的各个数字表示奇偶校验H矩阵第64i行中值为‘1’的列位置,0≤i≤84。H矩阵中第(64i+1)行至第(64i+63)行中‘1’的位置为H矩阵中的第64i行按照循环移位矩阵(CPM)经过循环移位得到。例如,第0行中的数字384表示奇偶校验H矩阵第0行第384列的位置取值为‘1’,第0行中的数字2304表示奇偶校验H矩阵第0行中第2304列的位置取值为‘1’。H矩阵第0行第384列的位置取值为‘1’,按照循环移位矩阵(CPM)经过循环移位,则可以得到H矩阵中第1行中取值为1的列位置为385,依次类推,而H矩阵中第63行中取值为1的列位置为447。另外,行末尾的’-1’不表示任何含义,也可以删除。The parity check H matrix with a code rate of 1/2 is given below. The matrix form of the parity check H matrix can be expressed as the following form from the 0th row to the 140th row, where the number of the row and the number of the column start from 0 start. Each number in the i-th row as follows represents the column position of the value '1' in the 64th row of the parity check H matrix, 0≤i≤84. The position of '1' in the (64i+1)th row to (64i+63)th row in the H matrix is obtained by cyclic shifting in the 64ith row in the H matrix according to the cyclic shift matrix (CPM). For example, the number 384 in the 0th row indicates that the position of the 384th column in the 0th row of the parity check H matrix is '1', and the number 2304 in the 0th row indicates the 2304th column in the 0th row of the parity check H matrix The value of the position is '1'. The position of the 384th column in
按照如上规则,奇偶校验H矩阵表示如下:According to the above rules, the parity check H matrix is expressed as follows:
如前所述,奇偶校验H矩阵前960列所对应的960个比特需要缩短处理,编码时该960列对应的比特取值均为’0’,编码完成后再将这些’0’比特删掉。As mentioned above, the 960 bits corresponding to the first 960 columns of the parity check H matrix need to be shortened. During encoding, the values of the bits corresponding to the 960 columns are all '0', and these '0' bits are deleted after the encoding is completed. Lose.
可以理解的,上述H矩阵也可以以母矩阵的形式表示。需要说明的是,H矩阵还可以有其他的变形,H矩阵中的行和行的次序可以相互交换,H矩阵中的列和列的次序也可以相互交换,本申请实施例并不具体限定。It can be understood that the above H matrix can also be expressed in the form of a parent matrix. It should be noted that the H matrix can also have other deformations, the order of rows and rows in the H matrix can be exchanged, and the order of columns and columns in the H matrix can also be exchanged, which is not specifically limited in the embodiment of the present application.
接下来介绍第二组LDPC码编码方案,码率R分别为R=7/8,13/16,3/4,5/8,1/2,且CPM为42x42,信息比特长度k=8064。Next, the second group of LDPC code coding schemes will be introduced. The code rates R are R=7/8, 13/16, 3/4, 5/8, and 1/2 respectively, and the CPM is 42x42, and the information bit length k=8064.
示例六:码率为7/8,循环移位矩阵(CPM)的大小为Z=42,信息比特长度为k=8064比特。Example 6: the code rate is 7/8, the size of the cyclic shift matrix (CPM) is Z=42, and the information bit length is k=8064 bits.
码率R=7/8的LDPC码,其奇偶校验H矩阵总的列的数目N1=(n+s),N1为9366,对应母矩阵总的列数为N0=N1/42=223,其奇偶校验H矩阵总的行的数目M1=(n+s-k),M1为1302,对应母矩阵总的行数为M0=M1/42=31,k个信息比特对应H矩阵中的k列,对应母矩阵中的k/Z列。该奇偶校验H矩阵的最大行重为23,即每行中最多23个1。The LDPC code of code rate R=7/8, the number N1=(n+s) of the total column of its parity check H matrix, N1 is 9366, and the total column number of corresponding mother matrix is N0=N1/42=223, The total row number M1=(n+s-k) of its parity check H matrix, M1 is 1302, and the total row number corresponding to the mother matrix is M0=M1/42=31, and k information bits correspond to k columns in the H matrix , corresponding to the k/Z columns in the mother matrix. The maximum row weight of the parity-check H matrix is 23, that is, there are at most 23 1s in each row.
根据奇偶校验H矩阵,生成1176个奇偶校验比特,获得码长为n0=9366的LDPC码码字C1,码字C1包括:s个待缩短比特、8064个信息比特和1176个奇偶校验比特;对C1进行缩短,得到其缩短后的码字C,码字C的真实码长为n=9240比特,包括8064个信息比特和1176个奇偶校验比特。所需缩短比特为C1的前s=126比特,即为母矩阵的前3列对应的前126个比特,前126个比特的取值为0。According to the parity check H matrix, 1176 parity check bits are generated, and the LDPC code word C 1 with a code length of n0=9366 is obtained, and the code word C 1 includes: s bits to be shortened, 8064 information bits and 1176 parity Parity bits; C 1 is shortened to obtain its shortened codeword C. The real code length of the codeword C is n=9240 bits, including 8064 information bits and 1176 parity bits. The required shortening bits are the first s=126 bits of C 1 , that is, the first 126 bits corresponding to the first 3 columns of the mother matrix, and the value of the first 126 bits is 0.
下面给出码率为7/8的奇偶校验H矩阵,奇偶校验H矩阵的矩阵形式可以表示为如下第0行至第30行的形式,其中,行的编号和列的编号都从0开始。如下第i行中的各个数字表示奇偶校验H矩阵第42i行中值为‘1’的列位置,0≤i≤30。H矩阵中第(42i+1)行至第(42i+41)行中‘1’的位置为H矩阵中的第42i行按照循环移位矩阵(CPM)经过循环移位得到。例如,第0行中的数字27表示奇偶校验H矩阵第0行第27列的位置取值为‘1’,第0行中的数字42表示奇偶校验H矩阵第0行中第42列的位置取值为‘1’。H矩阵第0行第27列的位置取值为‘1’,按照循环移位矩阵(CPM)经过循环移位,则可以得到H矩阵中第1行中取值为1的列位置为28,依次类推,而H矩阵中第15行中1的列位置为0。需要说明的是,行末尾的“-1”不表示任何含义,可以删除。A parity check H matrix with a code rate of 7/8 is given below. The matrix form of the parity check H matrix can be expressed as the following form from the 0th row to the 30th row, where the number of the row and the number of the column start from 0 start. Each number in the i-th row below represents the column position of the value '1' in the 42i row of the parity check H matrix, 0≤i≤30. The position of '1' in row (42i+1) to row (42i+41) in the H matrix is obtained by cyclic shifting in row 42i in the H matrix according to the cyclic shift matrix (CPM). For example, the
按照如上规则,奇偶校验H矩阵表示如下:According to the above rules, the parity check H matrix is expressed as follows:
如前所述,奇偶校验H矩阵前126列所对应的126个比特需要缩短处理,即编码时该126列对应的比特均为’0’,编码完成后再将这些’0’比特删掉。As mentioned earlier, the 126 bits corresponding to the first 126 columns of the parity check H matrix need to be shortened, that is, the bits corresponding to the 126 columns are all '0' during encoding, and these '0' bits are deleted after encoding .
可以理解的,上述H矩阵也可以以母矩阵的形式表示。需要说明的是,H矩阵还可以有其他的变形,H矩阵中的行和行的次序可以相互交换,H矩阵中的列和列的次序也可以相互交换,本申请实施例并不具体限定。It can be understood that the above H matrix can also be expressed in the form of a mother matrix. It should be noted that the H matrix can also have other deformations, the order of rows and rows in the H matrix can be exchanged, and the order of columns and columns in the H matrix can also be exchanged, which is not specifically limited in the embodiment of the present application.
示例七:码率为13/16,循环移位矩阵(CPM)的大小为42,信息比特长度为k=8064比特。Example 7: the code rate is 13/16, the size of the cyclic shift matrix (CPM) is 42, and the information bit length is k=8064 bits.
码率R=13/16的LDPC码,其奇偶校验H矩阵总的列的数目N1=(n+s),N1为10164,对应母矩阵总的列数为N0=N1/42=242,其奇偶校验H矩阵总的行的数目M1=(n+s-k),M1为2100,对应母矩阵总的行数为M0=M1/42=50,k个信息比特对应H矩阵中的k列,对应母矩阵中的k/Z列。该奇偶校验H矩阵的最大行重为15,即每行中最多15个1。The LDPC code of code rate R=13/16, the number N1=(n+s) of the total column of its parity check H matrix, N1 is 10164, and the total column number of corresponding mother matrix is N0=N1/42=242, The total row number M1=(n+s-k) of its parity check H matrix, M1 is 2100, and the total row number corresponding to the mother matrix is M0=M1/42=50, and k information bits correspond to k columns in the H matrix , corresponding to the k/Z columns in the mother matrix. The maximum row weight of the parity-check H matrix is 15, that is, there are at most 15 1s in each row.
根据奇偶校验H矩阵,生成1890个奇偶校验比特,获得码长为n0=10164的LDPC码码字C1,码字C1包括:s个待缩短比特、8064个信息比特和1890个奇偶校验比特;对C1进行缩短,得到其缩短后的码字C,码字C的真实码长为n=9954比特,包括:8064个信息比特和1890个奇偶校验比特。所需缩短比特为C1的前s=210比特,即为母矩阵的前5列对应的前210个比特,前210个比特的取值为0。According to the parity check H matrix, 1890 parity check bits are generated, and the LDPC code word C 1 with a code length of n0=10164 is obtained, and the code word C 1 includes: s bits to be shortened, 8064 information bits and 1890 parity Parity bits; C 1 is shortened to obtain its shortened codeword C, the real code length of codeword C is n=9954 bits, including: 8064 information bits and 1890 parity check bits. The required shortening bits are the first s=210 bits of C 1 , that is, the first 210 bits corresponding to the first 5 columns of the mother matrix, and the value of the first 210 bits is 0.
下面给出码率为13/16的奇偶校验H矩阵,奇偶校验H矩阵的矩阵形式可以表示为如下第0行至第49行的形式,其中,行的编号和列的编号都从0开始。如下第i行中的各个数字表示奇偶校验H矩阵第42i行中值为‘1’的列位置,0≤i≤49。H矩阵中第(42i+1)行至第(42i+41)行中‘1’的位置为H矩阵中的第42i行按照循环移位矩阵(CPM)经过循环移位得到。例如,第0行中的数字48表示奇偶校验H矩阵第0行第48列的位置取值为‘1’,第0行中的数字749表示奇偶校验H矩阵第0行中第749列的位置取值为‘1’。H矩阵第0行第48列的位置取值为‘1’,按照循环移位矩阵(CPM)经过循环移位,则可以得到H矩阵中第1行中取值为1的列位置为49,依次类推,而H矩阵中第36行中1的列位置为42。需要说明的是,行末尾的“-1”不代表任何含义,可以删除。The parity check H matrix with a code rate of 13/16 is given below. The matrix form of the parity check H matrix can be expressed as the following form from the 0th row to the 49th row, where the number of the row and the number of the column are all from 0 start. Each number in the i-th row as follows represents the column position of the value '1' in the 42ith row of the parity check H matrix, 0≤i≤49. The position of '1' in row (42i+1) to row (42i+41) in the H matrix is obtained by cyclic shifting in row 42i in the H matrix according to the cyclic shift matrix (CPM). For example, the
按照如上规则,奇偶校验H矩阵表示如下:According to the above rules, the parity check H matrix is expressed as follows:
如前所述,奇偶校验H矩阵前210列所对应的210个比特需要缩短处理,即编码时该210列对应的比特均为’0’,编码完成后再将这些’0’比特删掉。As mentioned above, the 210 bits corresponding to the first 210 columns of the parity check H matrix need to be shortened, that is, the bits corresponding to the 210 columns are all '0' during encoding, and these '0' bits are deleted after encoding .
可以理解的,上述H矩阵也可以以母矩阵的形式表示。需要说明的是,H矩阵还可以有其他的变形,H矩阵中的行和行的次序可以相互交换,H矩阵中的列和列的次序也可以相互交换,本申请实施例并不具体限定。It can be understood that the above H matrix can also be expressed in the form of a parent matrix. It should be noted that the H matrix can also have other deformations, the order of rows and rows in the H matrix can be exchanged, and the order of columns and columns in the H matrix can also be exchanged, which is not specifically limited in the embodiment of the present application.
示例八:码率为3/4,循环移位矩阵(CPM)的大小为42,信息比特长度为k=8064比特。Example 8: the code rate is 3/4, the size of the cyclic shift matrix (CPM) is 42, and the information bit length is k=8064 bits.
码率R=3/4的LDPC码,其奇偶校验H矩阵总的列的数目N1=(n+s),N1为11046,对应母矩阵总的列数为N0=N1/42=263,其奇偶校验H矩阵总的行的数目M1=(n+s-k),M1为2982,对应母矩阵总的行数为M0=M1/42=71,k个信息比特对应H矩阵中的k列,对应母矩阵中的k/Z列。该奇偶校验H矩阵的最大行重为12,即每行中最多12个1。The LDPC code of code rate R=3/4, the total column number N1=(n+s) of its parity-check H matrix, N1 is 11046, and the total column number corresponding to mother matrix is N0=N1/42=263, The total row number M1=(n+s-k) of its parity check H matrix, M1 is 2982, and the total row number corresponding to the mother matrix is M0=M1/42=71, and k information bits correspond to k columns in the H matrix , corresponding to the k/Z columns in the mother matrix. The maximum row weight of the parity-check H matrix is 12, that is, there are at most 12 1s in each row.
根据奇偶校验H矩阵,生成2688个奇偶校验比特,获得码长为n0=11046的LDPC码码字C1,码字C1包括:s个待缩短比特、8064个信息比特和2688个奇偶校验比特;对C1进行缩短,得到其缩短后的码字C,码字C的真实码长为n=10752比特,包括8064个信息比特和2688个奇偶校验比特。所需缩短比特为C1的前s=294比特,即为母矩阵的前7列对应于的前294个比特,前294个比特的取值为0。According to the parity check H matrix, generate 2688 parity check bits, and obtain the LDPC code word C 1 whose code length is n0=11046, the code word C 1 includes: s bits to be shortened, 8064 information bits and 2688 parity Parity bits; C 1 is shortened to obtain its shortened codeword C. The real code length of the codeword C is n=10752 bits, including 8064 information bits and 2688 parity bits. The required shortening bits are the first s=294 bits of C 1 , that is, the first 294 bits corresponding to the first 7 columns of the mother matrix, and the value of the first 294 bits is 0.
下面给出码率为3/4的奇偶校验H矩阵,奇偶校验H矩阵的矩阵形式可以表示为如下第0行至第70行的形式,其中,行的编号和列的编号都从0开始。如下第i行中的各个数字表示奇偶校验H矩阵第42i行中值为‘1’的列位置,0≤i≤70。H矩阵中第(42i+1)行至第(42i+41)行中‘1’的位置为H矩阵中的第42i行按照循环移位矩阵(CPM)经过循环移位得到。例如,第0行中的数字72表示奇偶校验H矩阵第0行第72列的位置取值为‘1’,第0行中的数字241表示奇偶校验H矩阵第0行中第241列的位置取值为‘1’。H矩阵第0行第72列的位置取值为‘1’,按照循环移位矩阵(CPM)经过循环移位,则可以得到H矩阵中第1行中取值为1的列位置为73,依次类推,而H矩阵中第12行中1的列位置为42。需要说明的是,行末尾的“-1”不代表任何含义,可以删除。A parity check H matrix with a code rate of 3/4 is given below. The matrix form of the parity check H matrix can be expressed as the following form from the 0th row to the 70th row, where the number of the row and the number of the column start from 0 start. Each number in the i-th row as follows represents the column position of the value '1' in the 42ith row of the parity check H matrix, 0≤i≤70. The position of '1' in row (42i+1) to row (42i+41) in the H matrix is obtained by cyclic shifting in row 42i in the H matrix according to the cyclic shift matrix (CPM). For example, the
按照如上规则,奇偶校验H矩阵表示如下:According to the above rules, the parity check H matrix is expressed as follows:
如前所述,奇偶校验H矩阵前294列所对应的294个比特需要缩短处理,即编码时该294列对应的比特均为’0’,编码完成后再将这些’0’比特删掉。As mentioned earlier, the 294 bits corresponding to the first 294 columns of the parity check H matrix need to be shortened, that is, the bits corresponding to the 294 columns are all '0' during encoding, and these '0' bits are deleted after encoding .
可以理解的,上述H矩阵也可以以母矩阵的形式表示。需要说明的是,H矩阵还可以有其他的变形,H矩阵中的行和行的次序可以相互交换,H矩阵中的列和列的次序也可以相互交换,本申请实施例并不具体限定。It can be understood that the above H matrix can also be expressed in the form of a mother matrix. It should be noted that the H matrix can also have other deformations, the order of rows and rows in the H matrix can be exchanged, and the order of columns and columns in the H matrix can also be exchanged, which is not specifically limited in the embodiment of the present application.
示例九:码率为5/8,循环移位矩阵(CPM)的大小为42,信息比特长度为k=8064比特。Example 9: the code rate is 5/8, the size of the cyclic shift matrix (CPM) is 42, and the information bit length is k=8064 bits.
码率R=5/8的LDPC码,其奇偶校验H矩阵总的列的数目N1=(n+s),N1为13440,对应母矩阵总的列数为N0=N1/42=320,其奇偶校验H矩阵总的行的数目M1=(n+s-k),M1为5376,对应母矩阵总的行数为M0=M1/42=128,k个信息比特对应H矩阵中的k列,对应母矩阵中的k/Z列。该奇偶校验H矩阵的最大行重为9,即每行中最多9个1。The LDPC code of code rate R=5/8, the number N1=(n+s) of the total column of its parity check H matrix, N1 is 13440, and the total column number of corresponding mother matrix is N0=N1/42=320, The total row number M1=(n+s-k) of its parity check H matrix, M1 is 5376, and the total row number corresponding to the mother matrix is M0=M1/42=128, and k information bits correspond to k columns in the H matrix , corresponding to the k/Z columns in the mother matrix. The maximum row weight of the parity-check H matrix is 9, that is, there are at most 9 1s in each row.
根据奇偶校验H矩阵,生成4872个奇偶校验比特,获得码长为n0=13440的LDPC码码字C1,码字C1包括:s个待缩短比特、8064个信息比特和4872个奇偶校验比特;对C1进行缩短,得到其缩短后的码字C,码字C的真实码长为n=12936比特:8064个信息比特和4872个奇偶校验比特。所需缩短比特为C1的前s=504比特,即为母矩阵的前12列对应的前504个比特,前504个比特的取值为0。According to the parity check H matrix, generate 4872 parity check bits, and obtain the LDPC code word C 1 whose code length is n0=13440, the code word C 1 includes: s bits to be shortened, 8064 information bits and 4872 parity Parity bits; C 1 is shortened to obtain its shortened codeword C, the real code length of the codeword C is n=12936 bits: 8064 information bits and 4872 parity check bits. The required shortening bits are the first s=504 bits of C 1 , that is, the first 504 bits corresponding to the first 12 columns of the mother matrix, and the value of the first 504 bits is 0.
下面给出码率为5/8的奇偶校验H矩阵,奇偶校验H矩阵的矩阵形式可以表示为如下第0行至第127行的形式,其中,行的编号和列的编号都从0开始。如下第i行中的各个数字表示奇偶校验H矩阵第42i行中值为‘1’的列位置,0≤i≤127。H矩阵中第(42i+1)行至第(42i+41)行中‘1’的位置为H矩阵中的第42i行按照循环移位矩阵(CPM)经过循环移位得到。例如,第0行中的数字11表示奇偶校验H矩阵第0行第11列的位置取值为‘1’,第0行中的数字239表示奇偶校验H矩阵第42i行中第239列的位置取值为‘1’。H矩阵第0行第11列的位置取值为‘1’,按照循环移位矩阵(CPM)经过循环移位,则可以得到H矩阵中第1行中取值为1的列位置为12,依次类推,而H矩阵中第31行中1的列位置为0。需要说明的是,行末尾的“-1”不代表任何含义,可以删除。A parity-check H matrix with a code rate of 5/8 is given below. The matrix form of the parity-check H matrix can be expressed as the following form from
按照如上规则,奇偶校验H矩阵表示如下:According to the above rules, the parity check H matrix is expressed as follows:
如前所述,奇偶校验H矩阵前504列所对应的504个比特需要缩短处理,即编码时该504列对应的比特均为’0’,编码完成后再将这些’0’比特删掉。As mentioned earlier, the 504 bits corresponding to the first 504 columns of the parity check H matrix need to be shortened, that is, the bits corresponding to the 504 columns are all '0' during encoding, and these '0' bits are deleted after encoding .
可以理解的,上述H矩阵也可以以母矩阵的形式表示。需要说明的是,H矩阵还可以有其他的变形,H矩阵中的行和行的次序可以相互交换,H矩阵中的列和列的次序也可以相互交换,本申请实施例并不具体限定。It can be understood that the above H matrix can also be expressed in the form of a mother matrix. It should be noted that the H matrix can also have other deformations, the order of rows and rows in the H matrix can be exchanged, and the order of columns and columns in the H matrix can also be exchanged, which is not specifically limited in the embodiment of the present application.
示例十:码率为1/2,循环移位矩阵(CPM)的大小为42,信息比特长度为k=8064比特。Example ten: the code rate is 1/2, the size of the cyclic shift matrix (CPM) is 42, and the information bit length is k=8064 bits.
码率R=1/2的LDPC码,其奇偶校验H矩阵总的列的数目N1=(n+s),N1为17052,对应母矩阵总的列数为N0=N1/42=406,其奇偶校验H矩阵总的行的数目M1=(n+s-k),M1为8988,对应母矩阵总的行数为M0=M1/42=214,k个信息比特对应H矩阵中的k列,对应母矩阵中的k/Z列。该奇偶校验H矩阵的最大行重为7,即每行中最多7个1。The LDPC code of code rate R=1/2, the total column number N1=(n+s) of its parity-check H matrix, N1 is 17052, and the total column number corresponding to mother matrix is N0=N1/42=406, The total row number M1=(n+s-k) of its parity check H matrix, M1 is 8988, and the total row number corresponding to the mother matrix is M0=M1/42=214, and k information bits correspond to k columns in the H matrix , corresponding to the k/Z columns in the mother matrix. The maximum row weight of the parity-check H matrix is 7, that is, there are at most 7 1s in each row.
根据奇偶校验H矩阵,生成8064个奇偶校验比特,获得码长为n0=17052的LDPC码码字C1,码字C1包括:s个待缩短比特、8064个信息比特和8064个奇偶校验比特;对C1进行缩短,得到其缩短后的码字C,码字C的真实码长为n=16128比特,包括:8064个信息比特和4872个奇偶校验比特。所需缩短比特为C1的前s=924比特,即为母矩阵的前22列所对应的前924个比特,前924个比特的取值为0。According to the parity check H matrix, generate 8064 parity check bits, and obtain the LDPC code word C 1 whose code length is n0=17052, the code word C 1 includes: s bits to be shortened, 8064 information bits and 8064 parity Parity bits; C 1 is shortened to obtain its shortened codeword C. The real code length of the codeword C is n=16128 bits, including: 8064 information bits and 4872 parity bits. The required shortening bits are the first s=924 bits of C 1 , that is, the first 924 bits corresponding to the first 22 columns of the mother matrix, and the value of the first 924 bits is 0.
下面给出码率为1/2的奇偶校验H矩阵,奇偶校验H矩阵的矩阵形式可以表示为如下第0行至第213行的形式,其中,行的编号和列的编号都从0开始。如下第i行中的各个数字表示奇偶校验H矩阵第42i行中值为‘1’的列位置,0≤i≤213。H矩阵中第(42i+1)行至第(42i+41)行中‘1’的位置为H矩阵中的第42i行按照循环移位矩阵(CPM)经过循环移位得到。例如,第0行中的数字289表示奇偶校验H矩阵第0行第289列的位置取值为‘1’,第0行中的数字924表示奇偶校验H矩阵第0行中第924列的位置取值为‘1’。H矩阵第0行第289列的位置取值为‘1’,按照循环移位矩阵(CPM)经过循环移位,则可以得到H矩阵中第1行中取值为1的列位置为290,依次类推,而H矩阵中第5行中1的列位置为252。需要说明的是,行末尾的“-1”不代表任何含义,可以删除。The parity check H matrix with a code rate of 1/2 is given below. The matrix form of the parity check H matrix can be expressed as the following form from the 0th row to the 213th row, where the number of the row and the number of the column start from 0 start. Each number in the i-th row as follows represents the column position of the value '1' in the 42ith row of the parity check H matrix, 0≤i≤213. The position of '1' in the (42i+1)th row to (42i+41)th row in the H matrix is obtained by cyclic shifting in the 42ith row in the H matrix according to the cyclic shift matrix (CPM). For example, the number 289 in the 0th row indicates that the position of the 289th column in the 0th row of the parity check H matrix is '1', and the number 924 in the 0th row indicates the 924th column in the 0th row of the parity check H matrix The value of the position is '1'. The position of the 289th column in
按照如上规则,奇偶校验H矩阵表示如下:According to the above rules, the parity check H matrix is expressed as follows:
如前所述,奇偶校验H矩阵前924列所对应的924个比特需要缩短处理,即编码时该924列对应的比特均为’0’,编码完成后再将这些’0’比特删掉。As mentioned earlier, the 924 bits corresponding to the first 924 columns of the parity check H matrix need to be shortened, that is, the bits corresponding to the 924 columns are all '0' during encoding, and these '0' bits are deleted after encoding .
可以理解的,上述H矩阵也可以以母矩阵的形式表示。需要说明的是,H矩阵还可以有其他的变形,H矩阵中的行和行的次序可以相互交换,H矩阵中的列和列的次序也可以相互交换,本申请实施例并不具体限定。It can be understood that the above H matrix can also be expressed in the form of a parent matrix. It should be noted that the H matrix can also have other deformations, the order of rows and rows in the H matrix can be exchanged, and the order of columns and columns in the H matrix can also be exchanged, which is not specifically limited in the embodiment of the present application.
图6示出了编码流程的一个示例。编码装置生产k个信息比特后,可在k个信息比特前填充s个值为0的待缩短比特,得到(k+s)个待编码比特。进一步的,根据前述实施例提供的任意一个H矩阵对(k+s)个待编码比特进行编码,得到码字C1,码长为n+s。最后,编码装置可将填充的s个值为0的待缩短比特删除,以得到最终的码长为n的码字C,输出码字C。Figure 6 shows an example of the encoding process. After the encoding device produces k information bits, s bits to be shortened with a value of 0 may be filled in front of the k information bits to obtain (k+s) bits to be encoded. Further, (k+s) bits to be coded are coded according to any H matrix provided in the foregoing embodiments to obtain a codeword C 1 with a code length of n+s. Finally, the encoding device may delete the filled s bits whose values are 0 to be shortened to obtain a final codeword C with a code length of n, and output the codeword C.
图7示出了译码流程的一个示例。译码装置接收到码字C经信道传输后的信号,经过似然估计得到n个比特的似然值,该似然值可以是概率,也可以是对数似然比。这n个比特的似然值包括k个信息比特所对应的似然值,和,(n-k)个奇偶校验比特所对应的似然值。进一步的,译码装置在该n比特似然值前填充s个值为0的待缩短比特相应的似然值,构成(s+n)个比特。根据编码时所使用的H矩阵,对(n+s)个比特所对应的似然值进行译码,得到(k+s)个比特;最后译码装置进行缩短处理,删除前s个比特,得到k个信息比特。Fig. 7 shows an example of the decoding process. The decoding device receives the signal of the code word C transmitted through the channel, and obtains a likelihood value of n bits through likelihood estimation, and the likelihood value may be a probability or a logarithmic likelihood ratio. The likelihood value of n bits includes the likelihood value corresponding to k information bits, and the likelihood value corresponding to (n-k) parity bits. Further, the decoding device fills in front of the n-bit likelihood value corresponding likelihood values of s bits to be shortened with a value of 0 to form (s+n) bits. According to the H matrix used during encoding, the likelihood values corresponding to (n+s) bits are decoded to obtain (k+s) bits; finally, the decoding device performs shortening processing to delete the first s bits, Get k information bits.
本申请实施例以5G新空口(5G new radio,5G NR)LDPC码为参考,进行了误码字率和运算复杂度性能对比分析。In the embodiment of the present application, the LDPC code of 5G new radio (5G new radio, 5G NR) is used as a reference, and a comparative analysis of bit error rate and computational complexity performance is carried out.
图8示出了本申请实施例提供的第一组LDPC码与5G NR LDPC码的误码字率仿真性能比较。图9示出了本申请实施例提供的第二组LDPC码与5G NR LDPC码的误码字率仿真性能比较。图8和图9中示出的结果曲线是在相同的码率和码长下仿真得到的,其中信息比特长度固定为8064,CPM大小为64,采用分层译码的最小和偏移(Min-Sum-Offset)译码算法,最大迭代次数50次,其中,横坐标表示信号噪声比(Signal-to-noise ratio,SNR),纵坐标表示误码字率,黑色实线为本申请实施例的LDPC编码方案误码字率的仿真结果曲线,黑色圈状实线为5G NR LDPC的误码字率的仿真结果曲线,黑色线状虚线为不可快速编码矩阵参考性能。例如,如图8中码率R为1/2的三条曲线所示,当信号噪声比SNR相等时,本申请实施例提出的LDPC码编码方案的误码字率明显低于5G NR LDPC的误码字率。由图8和图9可知,本申请实施例第一组编码方案和第二组编码方案在各个码率下误码字率性能均优于5G NRLDPC的误码字率性能,且码率越低,性能优势越明显。Fig. 8 shows the comparison of the word error rate simulation performance of the first group of LDPC codes provided by the embodiment of the present application and the 5G NR LDPC codes. FIG. 9 shows a comparison of the word error rate simulation performance of the second group of LDPC codes provided by the embodiment of the present application and the 5G NR LDPC codes. The result curves shown in Figure 8 and Figure 9 are simulated under the same code rate and code length, where the information bit length is fixed at 8064, the CPM size is 64, and the minimum sum offset (Min -Sum-Offset) decoding algorithm, the maximum number of iterations is 50 times, wherein the abscissa represents the signal-to-noise ratio (Signal-to-noise ratio, SNR), and the ordinate represents the bit error rate, and the black solid line is the embodiment of the present application The simulation result curve of the bit error rate of the LDPC coding scheme, the black circle solid line is the simulation result curve of the bit error rate of 5G NR LDPC, and the black linear dotted line is the reference performance of the non-fast encoding matrix. For example, as shown in the three curves with the code rate R being 1/2 in Figure 8, when the signal-to-noise ratio SNR is equal, the bit error rate of the LDPC coding scheme proposed in the embodiment of this application is significantly lower than that of 5G NR LDPC. code word rate. It can be seen from Figure 8 and Figure 9 that the code error rate performance of the first group of coding schemes and the second group of coding schemes in the embodiment of the present application is better than that of 5G NRLDPC at each code rate, and the lower the code rate is , the performance advantage is more obvious.
表1示出了本申请实施例提供的第一组LDPC码与5G NR LDPC码的运算复杂度的仿真性能比较。表2示出了本申请实施例提供的第二组LDPC码与5G NR LDPC码的运算复杂度的仿真性能比较。其中,表1中的第一行依次表示:码率R(Rate)、该码率下LDPC码的k个信息比特在母矩阵中对应的列数K0(K0=k/Z)、缩短s个待缩短比特后码字C在母矩阵中对应的列数C0(C0=n/Z)、s个待缩短比特所对应的母矩阵中所需打孔的列数S0(S0=s/Z)、循环移位矩阵的大小Z、校验矩阵的列度分布dv(即各个列重在所有列中所占百分比)、行度分布dc(即各个行重在所有行中所占百分比)、性能增益(Gain)、计算复杂度百分比(Computational complexity ratio,Comp.Ratio)。其中:性能增益(Gain)指在误码字率为10-3时的本申请实施例的LDPC方案相比5G NR LDPC方案的性能增益,计算复杂度百分比表示相同参数下本申请实施例的LDPC编码所需计算次数与5G NR LDPC编码所需计算次数的百分比;列度分布中的三个数字依次表示:列重,列重的总列数,以及列重列数与总列数的占比,例如,表1中的第一行的第一组数字:2 7488 0.438202,表示列重为2的列数为7488,占比为0.438202。计算复杂度表示相同参数下LDPC编码所需的计算次数,本申请实施例的方案相比5G NR LDPC在复杂度方面的优势可以用计算复杂度百分比体现。Table 1 shows the simulation performance comparison of the computational complexity of the first group of LDPC codes provided by the embodiment of the present application and the 5G NR LDPC codes. Table 2 shows the simulation performance comparison of the computational complexity of the second group of LDPC codes provided by the embodiment of the present application and the 5G NR LDPC codes. Wherein, the first row in Table 1 represents in sequence: the code rate R (Rate), the number of columns K0 (K0=k/Z) corresponding to the k information bits of the LDPC code under the code rate in the mother matrix, shortening the number of s The number of columns C0 (C0=n/Z) corresponding to the codeword C in the mother matrix after the bits to be shortened, and the number of columns S0 (S0=s/Z) that need to be punched in the mother matrix corresponding to the s bits to be shortened , the size Z of the cyclic shift matrix, the column degree distribution d v of the check matrix (that is, the percentage of each column weight in all columns), and the row degree distribution d c (that is, the percentage of each row weight in all rows) , performance gain (Gain), computational complexity percentage (Computational complexity ratio, Comp.Ratio). Among them: performance gain (Gain) refers to the performance gain of the LDPC scheme of the embodiment of the present application when the bit error rate is 10 -3 compared to the performance gain of the 5G NR LDPC scheme, and the calculation complexity percentage represents the LDPC of the embodiment of the present application under the same parameters The percentage of the number of calculations required for encoding to the number of calculations required for 5G NR LDPC encoding; the three numbers in the column degree distribution represent in turn: column weight, the total number of columns of the column weight, and the ratio of the number of columns to the total number of columns , for example, the first group of numbers in the first row in Table 1: 2 7488 0.438202, indicating that the number of columns with a column weight of 2 is 7488, and the proportion is 0.438202. Computational complexity refers to the number of calculations required for LDPC encoding under the same parameters. Compared with 5G NR LDPC, the solution in the embodiment of the present application has advantages in terms of complexity, which can be reflected by the percentage of computational complexity.
由表1和表2可见,本申请实施例第一组编码方案的计算复杂度与5G NR LDPC的计算复杂度的百分比均小于100%,也就是说第一组编码方案的LDPC编码的计算复杂度低于5G NR LDPC编码的计算复杂度;本申请实施例第二组编码方案的计算复杂度与5G NR LDPC的计算复杂度的百分比均小于100%,也就是说第二组编码方案的LDPC编码的计算复杂度低于5G NR LDPC编码的计算复杂度;因此本申请实施例第一组编码方案和本申请实施例第二组编码方案在各种码率下译码运算复杂度均低于同样参数下的5G NR LDPC码,并且码率越低,本申请实施例提出的LDPC编码方案的复杂度优势越明显。It can be seen from Table 1 and Table 2 that the percentage of the computational complexity of the first group of coding schemes in the embodiment of the present application and the computational complexity of 5G NR LDPC is less than 100%, which means that the calculation of the LDPC coding of the first group of coding schemes is complex degree is lower than the computational complexity of 5G NR LDPC coding; the percentage of the computational complexity of the second group of coding schemes in the embodiment of the present application and the computational complexity of 5G NR LDPC is less than 100%, that is to say, the LDPC of the second group of coding schemes The computational complexity of coding is lower than that of 5G NR LDPC coding; therefore, the decoding computational complexity of the first group of coding schemes in the embodiment of the present application and the second group of coding schemes in the embodiment of the present application are lower than The 5G NR LDPC code under the same parameters, and the lower the code rate, the more obvious the complexity advantage of the LDPC coding scheme proposed in the embodiment of this application.
因此,本申请实施例提供的LDPC码可有效提升系统的性能和可靠性。Therefore, the LDPC code provided by the embodiment of the present application can effectively improve the performance and reliability of the system.
表1Table 1
表2Table 2
参考图10,本申请实施例提供的一种LDPC码编码装置1000的示意图,该LDPC码编码装置1000可以执行上述任一方面的方法,可以是一个整机的设备,还可以是设备内的芯片或集成电路,该LDPC码编码装置1000包括:生成模块1001、编码模块1002、输出模块1003。Referring to FIG. 10 , a schematic diagram of an LDPC code encoding device 1000 provided in an embodiment of the present application, the LDPC code encoding device 1000 can perform any of the above-mentioned methods, it can be a complete device, or it can be a chip in the device Or an integrated circuit, the LDPC code encoding device 1000 includes: a
生成模块1001,用于获取k个信息比特,其中k=8064;编码模块1002,用于根据奇偶校验H矩阵,对所述k个信息比特进行LDPC编码,获得编码后的码字C,所述码字C的码长为n,码率R为k/n;其中,所述H矩阵为(n+s-k)×(n+s)阶的奇偶校验矩阵,所述H矩阵被划分为大小为Z×Z阶的子方阵,所述Z取值为64或42,所述子方阵为单位矩阵P0的循环移位或空矩阵,s为待缩短的比特数且为Z的正整数倍;输入输出模块1003,用于输出所述码字C。一个示例中,生成模块1001,编码模块1002,输出模块1003可以集成在一个处理单元中,输出模块1003可以为该处理单元的接口电路,用于输入和输出该处理单元与其他单元交互的信令或数据。The
可选的,所述装置还包括:填充模块1004,用于在所述k个信息比特前填充s个待缩短比特,得到k+s个待编码比特,所述s个待缩短比特的值为0;所述编码模块,用于对所述(s+k)个待编码比特进行LDPC编码,获得编码后的码字C1,所述码字C1的码长为n+s;删除模块1005:用于删除所述码字C1中的所述s个待缩短比特,得到所述码字C,其中,所述s个待缩短比特与所述H矩阵的前s列相对应。Optionally, the device further includes: a filling
需要说明的是,对于不同的码率,奇偶校验H矩阵可参考前述示例一至示例十或其变形形式,此处不再赘述。It should be noted that, for different code rates, the parity check H matrix may refer to the foregoing example 1 to example 10 or their modified forms, which will not be repeated here.
参考图11,本申请实施例提供了一种LDPC码编码装置1100。编码装置1100包括:处理器1101,可选的,还包括存储器1102。存储器1102可用于存储奇偶校验H矩阵。处理器1101可用于对k个信息比特根据奇偶校验H矩阵进行LDPC编码,从而得到LDPC编码后的码字c。可选的,处理器还可以用于从存储器1102存储的多个H矩阵中,确定一个H矩阵,用于进行LDPC编码。具体如何确定H矩阵,处理器可以依据码率或业务需求选择,本申请实施例并不具体限定。Referring to FIG. 11 , an embodiment of the present application provides an LDPC code encoding device 1100 . The encoding device 1100 includes: a processor 1101 , and optionally, a memory 1102 . The memory 1102 can be used to store the parity check H matrix. The processor 1101 may be configured to perform LDPC encoding on the k information bits according to the parity check H matrix, so as to obtain an LDPC-encoded code word c. Optionally, the processor may also be configured to determine an H matrix from the multiple H matrices stored in the memory 1102 for LDPC encoding. Specifically, how to determine the H matrix can be selected by the processor according to the code rate or service requirements, which is not specifically limited in this embodiment of the present application.
参考图12,本申请实施例提供的一种LDPC码译码装置1200的示意图,该LDPC码译码装置1200可以执行上述任一方面的方法,可以是一个整机的设备,还可以是设备内的芯片或集成电路,该LDPC码译码装置1200包括:输入输出模块1201、填充模块1202、译码模块1203。Referring to FIG. 12 , it is a schematic diagram of an LDPC code decoding device 1200 provided in an embodiment of the present application. The LDPC code decoding device 1200 can perform any of the above-mentioned methods, and can be a complete device or an internal device. chip or integrated circuit, the LDPC code decoding device 1200 includes: an input and output module 1201 , a
输入输出模块1201,获取经过LDPC编码后的码字C,码长为n;填充模块1202,用于在码字C的最前面填充值为0的s个待缩短比特,得到码字C1,所述s个待缩短比特的取值为0。译码模块1203,,用于根据奇偶校验H矩阵,对所述码字C1进行LDPC译码,获得译码后的(s+k)个比特,删除前s个值为0的待缩短比特,得到k个信息比特。其中,所述H矩阵为(n+s-k)×(n+s)阶的奇偶校验矩阵,所述H矩阵被划分为大小为Z×Z阶的子方阵,所述Z取值为64或42,所述子方阵为单位矩阵P0的循环移位或空矩阵,s为待缩短的比特数且为Z的正整数倍;The input and output module 1201 obtains the codeword C after LDPC encoding, and the code length is n; the
一个示例中,输入输出模块1201、填充模块1202、译码模块1203可以集成在一个处理单元中,输入输出模块1003可以为该处理单元的接口电路,用于输入和输出该处理单元与其他单元交互的信令或数据。In an example, the input and output module 1201, the
需要说明的是,对于不同的码率,奇偶校验H矩阵可参考前述示例一至示例十,此处不再赘述。It should be noted that, for different code rates, the parity check H matrix may refer to the foregoing example 1 to example 10, and details are not repeated here.
参考图13,本申请实施例提供了一种LDPC码译码装置1300。译码装置1300包括:处理器1301,可选的,还包括存储器1302。存储器1302可用于存储奇偶校验H矩阵。处理器1301可用于对码字比特根据奇偶校验H矩阵进行LDPC译码,从而得到LDPC译码后的信息比特。可选的,处理器还可以用于从存储器1302存储的多个H矩阵中,确定一个H矩阵,用于进行LDPC译码。具体如何确定H矩阵,处理器可以依据码率或业务需求选择,本申请实施例并不具体限定。可选的,存储器1302可以是集成在处理器1301的内部存储器,还可以是与处理器耦合的外部存储器。Referring to FIG. 13 , an embodiment of the present application provides an LDPC code decoding device 1300 . The decoding apparatus 1300 includes: a processor 1301 , and optionally, a memory 1302 . The memory 1302 can be used to store the parity check H matrix. The processor 1301 may be configured to perform LDPC decoding on codeword bits according to the parity check H matrix, so as to obtain LDPC-decoded information bits. Optionally, the processor may also be configured to determine an H matrix from the multiple H matrices stored in the memory 1302 for LDPC decoding. Specifically, how to determine the H matrix can be selected by the processor according to the code rate or service requirements, which is not specifically limited in this embodiment of the present application. Optionally, the memory 1302 may be an internal memory integrated in the processor 1301, or an external memory coupled with the processor.
图14示出在无线通信系统中的无线通信装置1400,该装置1400包括:处理器1401,发送模块1403,接收模块1404,射频模块1405,天线1406。射频模块1405和接收模块1404可对经由天线1406接收到的信号进行滤波、放大、解调、下变频、数字化以及解码等)并提供输入采样,射频模块1405和发送模块1403可以对待发送的信号进行编码、模拟转换、滤波、放大、调制和上变频后经由天线1406发送。可选的,所述装置1400还包括存储器1402。FIG. 14 shows a wireless communication device 1400 in a wireless communication system, and the device 1400 includes: a processor 1401 , a sending module 1403 , a receiving module 1404 , a radio frequency module 1405 , and an antenna 1406 . The radio frequency module 1405 and the receiving module 1404 can filter, amplify, demodulate, down-convert, digitize, and decode the signal received via the antenna 1406) and provide input sampling, and the radio frequency module 1405 and the transmitting module 1403 can perform signal processing on the signal to be transmitted. After coding, analog conversion, filtering, amplification, modulation and frequency up-conversion, it is sent via the antenna 1406 . Optionally, the apparatus 1400 further includes a memory 1402 .
一个示例中,所述装置1400可以被配置为执行LDPC编码的编码装置,可以执行上述任一方面涉及编码的方法。装置1400例如可以是接入点AP(基于图1中的AP111),站点(例如图1的站点112)等,还可以是接入点AP和站点内的芯片。In an example, the apparatus 1400 may be configured as an encoding apparatus for performing LDPC encoding, and may implement any method related to encoding in any aspect above. The apparatus 1400 may be, for example, an access point AP (based on
装置1400的发送模块1403中还可包括LDPC码编码器。编码器可用于对需要发送的信息比特进行编码处理,以生成码字。一个示例中,编码器可获取k个信息比特,并对k个信息比特根据奇偶校验H矩阵进行LDPC编码,从而得到LDPC编码后的码字c。其中,奇偶校验H矩阵可参考前述示例一至示例十,可根据码率选择其中的一种或多种奇偶校验H矩阵进行编码,此处不再赘述。码字C经由发送模块1403中的其他电路和射频模块1405进行进一步处理后输出至天线1406发送。The sending module 1403 of the device 1400 may further include an LDPC code encoder. The encoder can be used to encode the information bits to be sent to generate codewords. In an example, the encoder may obtain k information bits, and perform LDPC encoding on the k information bits according to the parity check H matrix, so as to obtain an LDPC-encoded codeword c. For the parity check H matrix, reference may be made to the foregoing examples 1 to 10, and one or more of the parity check H matrices may be selected for encoding according to the code rate, and details are not repeated here. The codeword C is further processed by other circuits in the sending module 1403 and the radio frequency module 1405, and then output to the antenna 1406 for transmission.
另一个示例中,所述装置1400可以被配置为执行LDPC编码的译码装置,可以执行上述任一方面涉及译码的方法。装置1400例如可以是接入点AP(基于图1中的AP111),站点(例如图1的站点112)等,还可以是接入点AP和站点内的芯片。In another example, the device 1400 may be configured as a decoding device for performing LDPC encoding, and may perform the method related to decoding in any aspect above. The apparatus 1400 may be, for example, an access point AP (based on
装置1400的接收模块1404可包括LDPC码译码器。译码器可用于对需要发送的信息比特进行译码处理,以生成码字。一个示例中,译码器可获取码字比特,并对码字比特根据奇偶校验H矩阵进行LDPC译码,从而得到LDPC译码后的信息比特。其中,奇偶校验H矩阵可参考前述示例一至示例十,可根据码率选择其中的一种或多种奇偶校验H矩阵进行译码,此处不再赘述。The receiving module 1404 of the device 1400 may include an LDPC code decoder. The decoder can be used to decode the information bits to be sent to generate codewords. In an example, the decoder may obtain the codeword bits, and perform LDPC decoding on the codeword bits according to the parity check H matrix, so as to obtain LDPC-decoded information bits. For the parity check H matrix, reference may be made to the foregoing examples 1 to 10, and one or more of the parity check H matrices may be selected for decoding according to the code rate, which will not be repeated here.
本申请实施例还提供了一种计算机程序产品,所述计算机程序产品包括:计算机程序代码,当所述计算机程序代码被计算机运行时,使得所述计算机执行上述各示例中的方法。An embodiment of the present application further provides a computer program product, the computer program product including: computer program code, when the computer program code is run by a computer, the computer is made to execute the methods in the above examples.
本申请实施例还提供了一种计算机可读介质,用于存储计算机程序,该计算机程序包括用于执行上述各示例中的方法的指令。An embodiment of the present application also provides a computer-readable medium for storing a computer program, where the computer program includes instructions for executing the methods in the foregoing examples.
本申请实施例还提供了一种芯片,包括处理器,用于从存储器中调用并运行所述存储器中存储的指令,使得安装有所述芯片的通信设备执行上述各示例中的方法。The embodiment of the present application also provides a chip, including a processor, configured to call and execute instructions stored in the memory from a memory, so that a communication device installed with the chip executes the methods in the above examples.
本申请实施例还提供另一种芯片,包括:输入接口、输出接口、处理器和存储器,所述输入接口、输出接口、所述处理器以及所述存储器之间通过内部连接通路相连,所述处理器用于执行所述存储器中的代码,当所述代码被执行时,所述处理器用于执行上述各示例中的方法。The embodiment of the present application also provides another chip, including: an input interface, an output interface, a processor, and a memory, the input interface, the output interface, the processor, and the memory are connected through an internal connection path, and the The processor is configured to execute the codes in the memory, and when the codes are executed, the processor is configured to execute the methods in the above examples.
本申请实施例还提供又一种芯片,包括一个或多个处理电路,以及输入输出接口。当所述芯片应用于编码装置中时,所述一个或多个处理电路可用于根据奇偶校验H矩阵进行编码,输入输出接口可用于输出编码后的码字C;当所述芯片应用于译码装置中时,所述一个或多个处理电路可用于根据奇偶校验H矩阵进行解码,输入输出接口可用于输入待译码的码字C,还用于输出译码后的信息比特。The embodiment of the present application also provides another chip, including one or more processing circuits, and an input and output interface. When the chip is used in an encoding device, the one or more processing circuits can be used for encoding according to the parity check H matrix, and the input and output interface can be used for outputting the encoded code word C; when the chip is used for decoding When in the coding device, the one or more processing circuits can be used for decoding according to the parity check H matrix, and the input and output interface can be used for inputting the code word C to be decoded, and also for outputting the decoded information bits.
本申请实施例还提供一种装置,用于实现上述各实施例中的方法。The embodiment of the present application further provides an apparatus for implementing the methods in the foregoing embodiments.
在上述实施例中,可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时,可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时,全部或部分地产生按照本申请所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中,或者从一个计算机可读存储介质向另一个计算机可读存储介质传输,例如,所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线)或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质,(例如,软盘、硬盘、磁带)、光介质(例如,DVD)、或者半导体介质(例如固态硬盘Solid StateDisk)。In the above embodiments, all or part of them may be implemented by software, hardware, firmware or any combination thereof. When implemented using software, it may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the processes or functions according to the present application will be generated in whole or in part. The computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website, computer, server, or data center Transmission to another website site, computer, server, or data center by wired (eg, coaxial cable, optical fiber, DSL) or wireless (eg, infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that can be accessed by a computer, or a data storage device such as a server or a data center integrated with one or more available media. The available media may be magnetic media (eg, floppy disk, hard disk, magnetic tape), optical media (eg, DVD), or semiconductor media (eg, Solid State Disk).
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