CN111324498A - Hardware information detection device, identification device and method - Google Patents

Abstract

The invention discloses a hardware information detection device, a hardware information identification device and a hardware information identification method. The hardware information detection device includes: the processing device comprises a detection port, the detection port is used for being connected to a resistance-capacitance circuit of hardware to be detected, the default level of the connection point of the detection port and the resistance-capacitance circuit in the hardware to be detected is a first level, wherein the processing device executes the following processing: setting a level of the connection point to a second level through the detection port, wherein the second level is different from the first level; setting the detection port to an interrupt mode triggered by a first level; detecting the time required for the level value of the detection port to change from the second level to the first level, wherein the time is the trigger time required for triggering interruption; and determining the information of the hardware to be detected based on the trigger time.

Description

Hardware information detection device, identification device and method

technical field

Embodiments of the present invention relate to the field of communication technologies, and in particular, to a hardware information detection device, a hardware information identification device, and a hardware information detection method.

Background technique

At present, the development of electronic products is becoming more and more globalized, and the update rhythm of electronic products is getting faster and faster. In addition, there are more and more adaptable peripherals for electronic products. Therefore, it is necessary to identify hardware version information of electronic products, and/or identify product information of peripheral devices in production activities.

For example, an electronic product needs to be supplied to users in many countries. Users in different countries have different customization needs. Therefore, different versions of hardware are designed for different countries. In addition, when the product is updated, the software needs to identify the version of the hardware in order to configure it accordingly. When products are updated quickly, multiple different versions of hardware need to be set up and identified. In addition, more and more peripherals can be connected to electronic products. Therefore, it is necessary to identify the product information of different peripherals. For example, the peripheral is a camera, earphone, charger, etc., or the model of the camera, earphone, and charger. .

Now, there are mainly two ways to identify the hardware version.

In the first method, use the CPU's GPIO (General Purpose Input Output) interface and preset pull-up and pull-down resistors to identify the hardware version. Specifically, as shown in Figure 1, four resistor locations R1, R2, R3, R4 can be placed between the power supply VCC and ground. R1 and R2 are connected in series between the power supply VCC and the ground, and the first GPIO interface GPIO 1 of the CPU is connected between R1 and R2. R3 and R4 are connected in series between the power supply VCC and the ground, and the second GPIO interface GPIO 2 of the CPU is connected between R1 and R4. Therefore, different high and low levels can be detected through the GPIO 1 and GPIO 2 interfaces to determine the version of the hardware. Table 1 shows the different settings of R1, R2, R3, R4, the levels detected by GPIO 1 and GPIO 2, and the corresponding hardware versions 1-4.

Table 1

R1 R2 R3 R4 GPIO 1 GPIO 2 Hardware version 1 10KΩ don't post 10KΩ don't post high high Hardware version 2 don't post 10KΩ don't post 10KΩ Low Low Hardware version 3 don't post 10KΩ 10KΩ don't post Low high Hardware version 4 10KΩ don't post don't post 10KΩ high Low

In the first method, if multiple hardware versions need to be detected, then multiple GPIO (General Purpose Input Output) interfaces and multiple sets of pull-up and pull-down resistors are required. This approach wastes limited GPIO port resources. Additionally, multiple sets of pull-up and pull-down resistors can affect device placement and routing.

In the second method, using the ADC (analog-to-digital conversion) port of the CPU can detect different voltage divider values to determine the hardware version. As shown in Figure 2, resistors R5 and R6 are connected in series between the power supply VCC and ground, and the ADC port is connected between R5 and R6. Different voltage divider values can be generated at the ADC port by setting different R5 and R6. The voltage divider value detected by the ADC port can represent different hardware versions. As an example, Table 2 below shows hardware versions 1-4 and the corresponding values of resistors R5, R6.

Table 2

R5 R6 Hardware version 1 1KΩ 10KΩ Hardware version 2 2KΩ 10KΩ Hardware version 3 3KΩ 10KΩ Hardware version 4 4KΩ 10KΩ

Generally, in a processing device such as a CPU, ADC (analog to digital conversion) ports/pins are relatively few and resources are limited. Therefore, there are usually no spare ADC pins for hardware revision detection. In addition, the analog-to-digital conversion processing is relatively complex and takes up more processing resources. Therefore, using the analog-to-digital conversion processing for hardware version detection results in a waste of resources to a certain extent.

Therefore, a new technical solution for detecting and identifying hardware versions or product information is required.

SUMMARY OF THE INVENTION

Embodiments of the present invention provide a hardware information detection device, a hardware information identification device, and a hardware information detection method to solve the technical problem of how to efficiently detect hardware information.

In order to solve the above-mentioned technical problems, the present invention is realized in this way.

In a first aspect, an embodiment of the present invention provides a hardware information detection device, including: a processing device, the processing device includes a detection port, the detection port is used for connecting to a resistor-capacitor circuit of the hardware to be detected, and the detection port is connected to a resistor - the default level of the connection point of the capacitive circuit in the hardware to be detected is the first level, wherein the processing device performs the following processing: setting the level of the connection point to the second level through the detection port, wherein, The second level is different from the first level; the detection port is set to an interrupt mode triggered by the first level; the detection port level value changes from the second level to the first level The time required for an interrupt is determined, and the time is the trigger time required to trigger an interrupt; and the information of the hardware to be detected is determined based on the trigger time.

In a second aspect, an embodiment of the present invention provides a hardware information identification device, including a resistor-capacitor circuit, where the resistor-capacitor circuit includes a connection point for connecting to a detection port, and the connection point is at a default power level in the hardware to be detected. level is the first level, and the resistance and capacitance of the resistor-capacitor circuit are set such that the time at which the resistor-capacitor circuit transitions from the second level to the first level identifies information of the hardware to be detected.

In a third aspect, an embodiment of the present invention provides a method for detecting hardware information, including: setting a level of a connection point between the detection port and the resistor-capacitor circuit to a second level different from the first level by using the detection port , where the first level is the default level of the connection point in the hardware to be detected; the detection port is set to an interrupt mode triggered by the first level; the detection port level value is determined by the first level The time required for the second level to change to the first level, the time being the trigger time required to trigger an interrupt; and the information of the hardware to be detected is determined based on the trigger time.

In this embodiment of the present invention, hardware information can be efficiently detected and identified by using different discharge times of the RC circuit to determine hardware information.

Other features and advantages of the present invention will become apparent from the following detailed description of exemplary embodiments of the present invention with reference to the accompanying drawings.

Description of drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.

FIG. 1 shows a circuit diagram of an apparatus for detecting a hardware version in the prior art.

FIG. 2 shows a circuit diagram of another device for detecting a hardware version in the prior art.

FIG. 3 shows a schematic diagram of a hardware structure of an electronic device implementing various embodiments of the present invention.

Figure 4 shows a graph of voltage versus time in an RC circuit.

FIG. 5 shows a circuit diagram of a system for detecting hardware information according to the first embodiment.

FIG. 6 shows a circuit diagram of a system for detecting hardware information according to the second embodiment.

FIG. 7 shows a circuit diagram of a system for detecting hardware information according to a third embodiment.

FIG. 8 shows a circuit diagram of a system for detecting hardware information according to a fourth embodiment.

FIG. 9 shows a schematic flowchart of a method for detecting hardware information according to a sixth embodiment.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are a part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present invention.

FIG. 1 is a schematic diagram of a hardware structure of an electronic device that can be used to implement various embodiments of the present invention.

The electronic device 100 includes but is not limited to: a radio frequency unit 101, a network module 102, an audio output unit 103, an input unit 104, a sensor 105, a display unit 106, a user input unit 107, an interface unit 108, a memory 109, a processor 110, and Power 111 and other components. Those skilled in the art can understand that the structure of the electronic device shown in FIG. 1 does not constitute a limitation on the electronic device, and the electronic device may include more or less components than the one shown, or combine some components, or different components. layout. In this embodiment of the present invention, electronic devices include but are not limited to mobile phones, tablet computers, notebook computers, handheld computers, vehicle-mounted terminals, wearable devices, pedometers, household appliances, medical devices, network devices, and the like.

It should be understood that, in this embodiment of the present invention, the radio frequency unit 101 may be used for receiving and sending signals during sending and receiving of information or during a call. Specifically, after the radio frequency unit 101 receives the downlink data from the base station, the processor 110 processes it. In addition, the uplink data is sent to the base station. Generally, the radio frequency unit 101 includes, but is not limited to, an antenna, at least one amplifier, a transceiver, a coupler, a low noise amplifier, a duplexer, and the like. In addition, the radio frequency unit 101 can also communicate with the network and other devices through a wireless communication system.

The electronic device provides the user with wireless broadband Internet access through the network module 102, such as helping the user to send and receive emails, browse web pages, access streaming media, and the like.

The audio output unit 103 may convert audio data received by the radio frequency unit 101 or the network module 102 or stored in the memory 109 into audio signals and output as sound. Also, the audio output unit 103 may also provide audio output related to a specific function performed by the electronic device 100 (e.g., call signal reception sound, message reception sound, etc.). The audio output unit 103 includes a speaker, a buzzer, a receiver, and the like.

The input unit 104 is used to receive audio or video signals. The input unit 104 may include a graphics processor (Graphics Processing Unit, GPU) 1041 and a microphone 1042. The graphics processor 1041 captures images of still pictures or videos obtained by an image capture device (such as a camera) in a video capture mode or an image capture mode data is processed. The processed image frames can be displayed on the display unit 106. The image frames processed by the graphics processor 1041 may be stored in the memory 109 (or other storage medium) or transmitted via the radio frequency unit 101 or the network module 102. The microphone 1042 can receive sound and can process such sound into audio data. The processed audio data can be converted into a format that can be transmitted to a mobile communication base station via the radio frequency unit 101 for output in the case of a telephone conversation mode.

The electronic device 100 also includes at least one sensor 105, such as a light sensor, a motion sensor, and other sensors. Specifically, the light sensor includes an ambient light sensor and a proximity sensor, wherein the ambient light sensor can adjust the brightness of the display panel 1061 according to the brightness of the ambient light, and the proximity sensor can turn off the display panel 1061 and the proximity sensor when the electronic device 100 is moved to the ear. / or backlight. As a kind of motion sensor, the accelerometer sensor can detect the magnitude of acceleration in all directions (usually three axes), and can detect the magnitude and direction of gravity when stationary, and can be used to identify the posture of electronic devices (such as horizontal and vertical screen switching, related games , magnetometer attitude calibration), vibration recognition related functions (such as pedometer, tapping), etc.; the sensor 105 may also include a fingerprint sensor, a pressure sensor, an iris sensor, a molecular sensor, a gyroscope, a barometer, a hygrometer, a thermometer, Infrared sensors, etc., are not repeated here.

The display unit 106 is used to display information input by the user or information provided to the user. The display unit 106 may include a display panel 1061, and the display panel 1061 may be configured in the form of a liquid crystal display (LCD), an organic light-emitting diode (OLED), or the like.

The user input unit 107 may be used to receive input numerical or character information, and generate key signal input related to user settings and function control of the electronic device. Specifically, the user input unit 107 includes a touch panel 1071 and other input devices 1072. The touch panel 1071, also referred to as a touch screen, can collect the user's touch operations on or near it (such as the user's finger, stylus, etc., any suitable object or attachment on or near the touch panel 1071). operate). The touch panel 1071 may include two parts, a touch detection device and a touch controller. Among them, the touch detection device detects the touch orientation of the user, and detects the signal brought by the touch operation, and transmits the signal to the touch controller; the touch controller receives the touch information from the touch detection device, converts it into contact coordinates, and sends it to the touch controller. To the processor 110, the command sent by the processor 110 is received and executed. In addition, the touch panel 1071 can be implemented in various types such as resistive, capacitive, infrared, and surface acoustic waves. In addition to the touch panel 1071, the user input unit 107 may also include other input devices 1072. Specifically, other input devices 1072 may include, but are not limited to, physical keyboards, function keys (such as volume control keys, switch keys, etc.), trackballs, mice, and joysticks, which will not be repeated here.

Further, the touch panel 1071 can be covered on the display panel 1061. When the touch panel 1071 detects a touch operation on or near it, it transmits it to the processor 110 to determine the type of the touch event, and then the processor 110 determines the type of the touch event according to the touch The type of event provides corresponding visual output on display panel 1061 . Although in FIG. 3 , the touch panel 1071 and the display panel 1061 are used as two independent components to realize the input and output functions of the electronic device, but in some embodiments, the touch panel 1071 and the display panel 1061 may be integrated The implementation of the input and output functions of the electronic device is not specifically limited here.

The interface unit 108 is an interface for connecting an external device to the electronic device 100 . For example, external devices may include wired or wireless headset ports, external power (or battery charger) ports, wired or wireless data ports, memory card ports, ports for connecting devices with identification modules, audio input/output (I/O) ports, video I/O ports, headphone ports, and more. The interface unit 108 may be used to receive input (eg, data information, power, etc.) from external devices and transmit the received input to one or more elements within the electronic device 100 or may be used between the electronic device 100 and external Transfer data between devices.

The memory 109 may be used to store software programs as well as various data. The memory 109 may mainly include a stored program area and a stored data area, wherein the stored program area may store an operating system, an application program (such as a sound playback function, an image playback function, etc.) required for at least one function, and the like; Data created by the use of the mobile phone (such as audio data, phone book, etc.), etc. Additionally, memory 109 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other volatile solid state storage device.

As a processing device, the processor 110 is the control center of the electronic equipment, and uses various interfaces and lines to connect various parts of the entire electronic equipment, by running or executing the software programs and/or modules stored in the memory 109, and calling the stored in the memory. 109, perform various functions of the electronic device and process data, so as to monitor the electronic device as a whole. The processor 110 may include one or more processing units; preferably, the processor 110 may integrate an application processor and a modem processor, wherein the application processor mainly processes the operating system, user interface, and application programs, etc., and the modem The processor mainly handles wireless communication. It can be understood that the above-mentioned modem processor may not be integrated into the processor 110.

The processor 110 typically includes various ports (pins), eg, multiple GPIO ports. Hardware information such as the hardware version of electronic device 100 can be detected using the GPIO ports. In addition, when a peripheral device such as a printer, a camera, etc. is connected to the electronic device 100, the processor 110 can detect the hardware information of the peripheral device through the GPIO port, thereby identifying the peripheral device.

The electronic device 100 may also include a power supply 111 (such as a battery) for supplying power to various components. Preferably, the power supply 111 may be logically connected to the processor 110 through a power management system, so as to manage charging, discharging, and power consumption management through the power management system and other functions.

In addition, the electronic device 100 includes some functional modules not shown, which will not be repeated here.

It is proposed to use the GPIO port with the interrupt function, and use the resistance-capacitor circuit (RC circuit) to detect the hardware information with different discharge times. In the RC circuit, by setting the resistance value of the resistor and the capacitance value of the capacitor to different values, the discharge time of the RC circuit will be different. The larger the time constant τ of the RC circuit, the longer the time required for discharge.

Figure 4 shows a graph of voltage versus time in an RC circuit. In Figure 4, the voltage Uc in the RC circuit is normalized. As shown in Fig. 4, the voltage Uc drops to 0.37Uc with the elapse of time τ. After time 2.3τ, the voltage Uc drops to 0.10Uc.

Therefore, different hardware information can be detected by detecting different discharge times of the RC circuit. Here, a hardware information detection device can be provided, including: a processing device, the processing device includes a detection port, the detection port is used to connect to a resistance-capacitance circuit of the hardware to be detected, and the detection port is connected to the resistance-capacitance circuit. The default level in the hardware to be detected is the first level. The processing device performs the following processing: setting the level of the connection point to a second level through the detection port, wherein the second level is different from the first level; setting the detection port to be controlled by the first level Triggered interrupt mode; detecting the time required for the detection port level value to change from the second level to the first level, the time is the trigger time required to trigger an interrupt; and based on the The trigger time determines the information of the hardware to be detected.

For example, the detection port is a GPIO port of the processing device.

In order to ensure that the RC circuit reaches a stable state at the second level, after the processing device sets the level of the connection point to the second level through the detection port, the hardware detection device needs to wait for a time greater than 100ms.

The information of the hardware to be detected may include version information of the hardware to be detected, product information of the hardware to be detected, and the like.

According to different circuit settings, the first level and the second level can be respectively a high level and a low level, or a low level and a high level, or two power levels set between the high level and the low level by a special device. flat. The default level refers to such a level: under the condition of no external circuit influence, when the hardware to be detected is powered on, under stable conditions, the level of the connection point between the detection port and the RC circuit is the default level.

Since different RC time constants can be set by setting different resistance and capacitance values, various hardware information can be represented. Therefore, only one GPIO port can detect various hardware information here.

In addition, since there is no need to set up multiple groups of pull-up and pull-down resistors, wiring resources in hardware can be saved, and the possibility of mutual interference between wirings can be reduced.

In addition, this method does not need to occupy limited ADC resources.

Each of the different embodiments will be described below with reference to FIGS. 5-9 .

[First Embodiment]

FIG. 5 shows a circuit diagram of a system for detecting hardware information according to the first embodiment.

FIG. 5 shows the hardware information detection device 110 and the hardware information identification device 120 . The hardware information detection device 110 and the hardware information identification device 120 may be located in the same electronic device, or may be located in different electronic devices, for example, in the main electronic device and the peripheral device, respectively.

The hardware information detection device 110 includes the processing device 10 . The processing device 10 may be a central processing unit and includes a detection port, for example, a GPIO port GPIOA. The processing device 10 may also include a timer 11 for recording the trigger time.

In Fig. 5, the resistor-capacitor circuits in the hardware information identification device 120 are resistor-capacitor parallel circuits Ra, Ca. One end of the resistor-capacitor parallel circuit is grounded. The other end of the resistor-capacitor parallel circuit is connected to the detection port (GPIOA) as the connection point A. In this case, the first level is a low level, and the second level is a high level.

When starting to detect hardware information, set port GPIOA to output high level. at this time. The level of connection point A is high. For example, wait 100ms for the RC parallel circuit to stabilize.

Next, set port GPIOA to low-level trigger interrupt mode and turn on timer 11.

When the port GPIOA triggers an interrupt, the time of the timer is read out as the trigger time. Different Ra and Ca values can be set, resulting in different trigger times. Different hardware information can be determined based on different trigger times. For example, Table 3 below shows the resistor values, capacitor values and their corresponding trigger times.

table 3

[Second Embodiment]

FIG. 6 shows a circuit diagram of a system for detecting hardware information according to the second embodiment.

FIG. 6 shows the hardware information detection device 210 and the hardware information identification device 220 .

The hardware information detection device 210 includes a processing device 20 . The processing device 20 may be a central processing unit and includes a detection port, such as a GPIO port GPIOB. The processing device 20 may also include a timer 21 for calculating the trigger time.

In Fig. 6, the resistor-capacitor circuits in the hardware information identification device 220 are resistor-capacitor parallel circuits Rb, Cb. One end of the resistor-capacitor parallel circuit is connected to the power supply VCC. The other end of the resistor-capacitor parallel circuit is connected to the detection port (GPIOA) as the connection point A. In this case, the first level is a high level, and the second level is a low level.

When starting to detect hardware information, set the port GPIOB to output low level. at this time. The level of connection point B is low. For example, wait 100ms for the RC parallel circuit to stabilize.

Next, set port GPIOB to high-level trigger interrupt mode, and turn on timer 21.

When the port GPIOB triggers an interrupt, the time of the timer is read out as the trigger time. Different Rb and Cb values can be set, resulting in different trigger times. Different hardware information can be determined based on different trigger times.

In the second embodiment, since a GPIO port is not required to set a high level, the power burden on the processing device can be reduced.

In addition, the level required to trigger the GPIOB port can be adjusted to a certain extent by setting the level of VCC.

[Third Embodiment]

FIG. 7 shows a circuit diagram of a system for detecting hardware information according to a third embodiment.

FIG. 7 shows the hardware information detection device 310 and the hardware information identification device 320 .

The hardware information detection device 310 includes a processing device 30 . The processing device 30 may be a central processing unit and includes a detection port, such as a GPIO port GPIOC. A timer 31 may also be included in the processing device 30 for calculating the trigger time.

In Fig. 7, the resistor-capacitor circuits in the hardware information identification device 320 are resistor-capacitor series circuits Rc, Cc. The resistor terminal Rc of the resistor-capacitor series circuit is connected to the power supply, and the capacitor terminal Cc of the resistor-capacitor series circuit is grounded. The detection port (GPIOC) is connected between the capacitor Cc and the resistor Rc in the resistor-capacitor series circuit as the connection point C. In this case, the first level is a high level, and the second level is a low level.

When starting to detect hardware information, the port GPIOC is set to output low level. at this time. The level of connection point C is low. For example, wait 100ms for the RC series circuit to stabilize.

Next, set the port GPIOC to high-level trigger interrupt mode, and turn on the timer 31.

When the port GPIOC triggers an interrupt, the time of the timer is read out as the trigger time. Different Rc and Cc values can be set, resulting in different trigger times. Different hardware information can be determined based on different trigger times. For example, Table 4 below shows the resistor values, capacitor values and their corresponding trigger times.

Table 4

R1 C1 time Hardware version 1 1KΩ 0.1uF 0.1ms Hardware version 2 5KΩ 0.1uF 0.5ms Hardware version 3 10KΩ 0.1uF 1ms Hardware version 4 15KΩ 0.1uF 1.5ms Hardware version 5 20KΩ 0.1uF 2ms Hardware version 6 25KΩ 0.1uF 2.5ms Hardware version 7 30KΩ 0.1uF 3.0ms Hardware version 8 35KΩ 0.1uF 3.5ms Hardware version 9 40KΩ 0.1uF 4.0ms Hardware version 10 45KΩ 0.1uF 4.5ms Hardware version 11 50KΩ 0.1uF 5.0ms Hardware version 12 55KΩ 0.1uF 5.5ms Hardware version 13 60KΩ 0.1uF 6.0ms Hardware version 14 65KΩ 0.1uF 6.5ms Hardware version 15 70KΩ 0.1uF 7.0ms Hardware version 16 75KΩ 0.1uF 7.5ms Hardware version 17 80KΩ 0.1uF 8.0ms Hardware version 18 85KΩ 0.1uF 8.5ms Hardware version 19 90KΩ 0.1uF 9.0ms Hardware version 20 95KΩ 0.1uF 9.5ms Hardware version 21 100KΩ 0.1uF 10.0ms

[Fourth Embodiment]

FIG. 8 shows a circuit diagram of a system for detecting hardware information according to a fourth embodiment.

FIG. 8 shows the hardware information detection device 410 and the hardware information identification device 420 .

The hardware information detection device 410 includes a processing device 40 . The processing device 40 may be a central processing unit and includes a detection port, such as a GPIO port GPIOD. The processing device 40 may also include a timer 41 for calculating the trigger time.

In Fig. 8, the resistor-capacitor circuits in the hardware information identification device 420 are resistor-capacitor series circuits Rd, Cd. The resistor terminal Rd of the resistor-capacitor series circuit is grounded, and the capacitor terminal Cd of the resistor-capacitor series circuit is connected to the power supply. The detection port (GPIOD) is connected between the capacitor Cd and the resistor Rd in the resistor-capacitor series circuit as the connection point D. In this case, the first level is a low level, and the second level is a high level.

When starting to detect hardware information, the port GPIOD is set to output high level. at this time. The level of connection point D is high. For example, wait 100ms for the RC series circuit to stabilize.

Next, the port GPIOD is set to low level trigger interrupt mode, and the timer 41 is turned on.

When the port GPIOD triggers an interrupt, the time of the timer is read out as the trigger time. Different Rd and Cd values can be set, resulting in different trigger times. Different hardware information can be determined based on different trigger times.

[Fifth Embodiment]

As shown in Figures 5-8, the embodiments disclosed herein also include a hardware information identification device including a resistor-capacitor circuit, such as an RC series circuit or an RC parallel circuit. The resistor-capacitor circuit includes a connection point for connection to the detection port, the default level of the connection point in the hardware to be detected is the first level, and the resistance and capacitance of the resistor-capacitor circuit are set such that the resistance - The time at which the capacitive circuit transitions from the second level to the first level identifies the information of the hardware to be detected. As shown in Tables 3 and 4 above, different transition times (trigger times) can be set with different resistor and capacitor values.

[Sixth Embodiment]

FIG. 9 shows a schematic flowchart of a method for detecting hardware information according to a sixth embodiment.

As shown in FIG. 9, in step S2, the level of the connection point between the detection port and the resistor-capacitor circuit is set to a second level different from the first level by the detection port, wherein the first level is the The default level of the connection point in the hardware to be detected.

In step S4, the detection port is set to the interrupt mode triggered by the first level.

In step S6, the time required for the level value of the detection port to change from the second level to the first level is detected, and this time is the trigger time required for triggering the interrupt.

In step S8, the information of the hardware to be detected is determined based on the trigger time.

The above embodiments may refer to each other, and in descriptions about the following embodiments, descriptions of the same or similar elements as those in the previous embodiments are omitted.

It should be noted that, herein, the terms "comprising", "comprising" or any other variation thereof are intended to encompass non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements, It also includes other elements not expressly listed or inherent to such a process, method, article or apparatus. Without further limitation, an element qualified by the phrase "comprising a..." does not preclude the presence of additional identical elements in a process, method, article or apparatus that includes the element.

The embodiments of the present invention have been described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific embodiments, which are merely illustrative rather than restrictive. Under the inspiration of the present invention, without departing from the spirit of the present invention and the scope protected by the claims, many forms can be made, which all belong to the protection of the present invention.

Claims (10)

1. A hardware information detection apparatus comprising:

processing means comprising a detection port for connection to a resistor-capacitor circuit of the hardware to be detected, a default level of a connection point of the detection port and the resistor-capacitor circuit in the hardware to be detected being a first level,

wherein the processing device executes the following processing:

setting a level of the connection point to a second level through the detection port, wherein the second level is different from the first level;

setting the detection port to an interrupt mode triggered by a first level;

detecting the time required for the level value of the detection port to change from the second level to the first level, wherein the time is the trigger time required for triggering interruption; and

and determining the information of the hardware to be detected based on the trigger time.

2. The hardware detection device according to claim 1, wherein, in a case where the resistor-capacitor circuit is a resistor-capacitor parallel circuit, one end of the resistor-capacitor parallel circuit is grounded, and the other end of the resistor-capacitor parallel circuit is connected to the detection port as a connection point, the first level is a low level, and the second level is a high level.

3. The hardware detection device according to claim 1, wherein, in a case where the resistor-capacitor circuit is a resistor-capacitor parallel circuit, one end of the resistor-capacitor parallel circuit is connected to a power supply, and the other end of the resistor-capacitor parallel circuit is connected to the detection port as a connection point, the first level is a high level, and the second level is a low level.

4. The hardware detection device according to claim 1, wherein, in a case where the resistor-capacitor circuit is a resistor-capacitor series circuit, a resistor end of the resistor-capacitor series circuit is connected to a power supply, a capacitor end of the resistor-capacitor series circuit is connected to ground, and the detection port is connected between a capacitor and a resistor in the resistor-capacitor series circuit as the connection point, the first level is a high level, and the second level is a low level.

5. The hardware detection device according to claim 1, wherein, in a case where the resistor-capacitor circuit is a resistor-capacitor series circuit, a resistor end of the resistor-capacitor series circuit is grounded, a capacitor end of the resistor-capacitor series circuit is connected to a power supply, and the detection port is connected between a capacitor and a resistor in the resistor-capacitor series circuit as the connection point, the first level is a low level, and the second level is a high level.

6. The hardware detection device according to claim 1, wherein the information of the hardware to be detected includes at least one of version information of the hardware to be detected and product information of the hardware to be detected.

7. The hardware detection device of claim 1, wherein the detection port is a GPIO port of the processing device.

8. The hardware detection device of claim 1, wherein the hardware detection device waits more than 100ms after the processing device sets the level of the connection point to the second level through the detection port.

9. A hardware information identification apparatus comprising a resistor-capacitor circuit comprising a connection point for connection to a detection port, the connection point having a default level in hardware to be detected which is a first level, the resistor and capacitor of the resistor-capacitor circuit being arranged such that: the time at which the resistor-capacitor circuit transitions from the second level to the first level is used to identify information about the hardware to be tested.

10. A hardware information detection method comprises the following steps:

setting the level of a connection point of the detection port and the resistor-capacitor circuit to a second level different from a first level through the detection port, wherein the first level is a default level of the connection point in the hardware to be detected;

setting the detection port to an interrupt mode triggered by a first level;

detecting the time required for the level value of the detection port to change from the second level to the first level, wherein the time is the trigger time required for triggering interruption; and

and determining the information of the hardware to be detected based on the trigger time.

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