CN111341651A - Transistor epitaxial layer fabrication method - Google Patents
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Abstract
本发明公开了晶体管外延层制作方法，晶体管外延层制作方法包括至少以下过程：对晶体基板进行一次或多次离子植入处理，使得离子掺杂深度达到第一预定深度；对离子植入处理后的晶体基板进行高温化扩散处理，使得离子掺杂深度达到第二预定深度并稳定，以此得到离子掺杂深度达到第二预定深度的晶体管外延层。本发明采用多次、多种形式的物理渗透的方式，可以以低成本、高质量的构造出大深度的掺杂层。其先采用高能量离子植入技术，可以解决离子由外界进入基板内部的突变问题，再配合低成本的高温扩散渗透，使其离子自由扩散渗透形成更加深的掺杂层。
The invention discloses a method for manufacturing a transistor epitaxial layer. The method for manufacturing a transistor epitaxial layer includes at least the following processes: performing one or more ion implantation treatments on a crystal substrate so that the ion doping depth reaches a first predetermined depth; The crystal substrate is subjected to high temperature diffusion treatment, so that the ion doping depth reaches the second predetermined depth and is stable, thereby obtaining the transistor epitaxial layer with the ion doping depth reaching the second predetermined depth. The invention adopts the physical infiltration method of multiple times and various forms, and can construct a large-depth doped layer with low cost and high quality. It first adopts high-energy ion implantation technology, which can solve the problem of sudden change of ions entering the substrate from the outside, and then cooperate with low-cost high-temperature diffusion and penetration, so that ions can freely diffuse and penetrate to form a deeper doped layer.
Description
技术领域technical field
本发明涉及外延层制造技术，主要涉及晶体管外延层制作方法。The invention relates to an epitaxial layer manufacturing technology, and mainly relates to a transistor epitaxial layer manufacturing method.
背景技术Background technique
外延是半导体工艺当中的一种，硅片最底层是P型衬底硅，然后在衬底上生长一层单晶硅，这层单晶硅称为外延层，再后来在外延层上主任基区、发射区等。Epitaxy is one of the semiconductor processes. The bottom layer of the silicon wafer is P-type substrate silicon, and then a layer of single crystal silicon is grown on the substrate. area, launch area, etc.
现有生长外延层有多种方法，按照反应机理，可以分为化学反应生长法和物理反应生长法。There are various methods for growing epitaxial layers. According to the reaction mechanism, they can be divided into chemical reaction growth method and physical reaction growth method.
在现有的外延加工中，多数采用的表面生长方法完成外延，必如，在衬底表面沉积化学反应生长、采用沉积、溅射等方法在表面生长。最常见的就是衬底表面沉积化学反应生长。In the existing epitaxy processing, most of the surface growth methods are used to complete the epitaxy, such as depositing chemical reaction growth on the substrate surface, using deposition, sputtering and other methods to grow on the surface. The most common is the deposition of chemical reaction growth on the substrate surface.
在现有技术向内生长外延层的技术中，比较常见的是采用离子注入，然后进行退火处理来恢复完整晶格。这种工艺一般采用低于400℃的多次退火处理来实现恢复完整晶格完整性的问题。Among the prior art techniques for inwardly growing epitaxial layers, it is more common to use ion implantation followed by annealing to restore a complete crystal lattice. This process typically employs multiple annealing treatments below 400°C to achieve the problem of restoring full lattice integrity.
但无论是表面外延处理工艺还是内生长外延处理工艺，都存在较为突出的问题：现有工艺复杂、成本高，无法获得掺杂深度大、均匀性好的外延层。However, whether it is a surface epitaxy treatment process or an in-growth epitaxy treatment process, there are relatively prominent problems: the existing process is complicated, the cost is high, and an epitaxial layer with a large doping depth and good uniformity cannot be obtained.
发明内容SUMMARY OF THE INVENTION
本发明的主要目的之一就是可以提高生产质量、低成本制造外延基板。One of the main purposes of the present invention is to improve the production quality and manufacture the epitaxial substrate at low cost.
为达上述目的，本发明提供一种晶体管外延层制作方法，In order to achieve the above purpose, the present invention provides a method for fabricating a transistor epitaxial layer,
晶体管外延层制作方法包括至少以下过程：The method for fabricating a transistor epitaxial layer includes at least the following processes:
对晶体基板进行一次或多次离子植入处理，使得离子掺杂深度达到第一预定深度；performing one or more ion implantation treatments on the crystal substrate, so that the ion doping depth reaches a first predetermined depth;
对离子植入处理后的晶体基板进行高温化扩散处理，使得离子掺杂深度达到第二预定深度并稳定，以此得到离子掺杂深度达到第二预定深度的晶体管外延层。The crystal substrate after the ion implantation treatment is subjected to a high temperature diffusion treatment, so that the ion doping depth reaches a second predetermined depth and is stable, thereby obtaining a transistor epitaxial layer with the ion doping depth reaching the second predetermined depth.
本发明所述的晶体管外延层制作方法，所述高温化扩散处理具体为：对离子植入处理后的晶体基板进行渐变升温处理至预定温度、并在预定温度处进行预定时间的保温处理、再由第一预定温度进行渐变降温处理。In the method for fabricating a transistor epitaxial layer according to the present invention, the high-temperature diffusion treatment is specifically: performing a gradual heating process on the crystal substrate after the ion implantation treatment to a predetermined temperature, and performing a heat preservation treatment at the predetermined temperature for a predetermined time, and then The gradual cooling process is performed from the first predetermined temperature.
本发明所述的晶体管外延层制作方法，所述高温化扩散处理具体为：对离子植入处理后的晶体基板放置与预定温度进行保温预定时间后取出自然冷却。In the method for fabricating a transistor epitaxial layer according to the present invention, the high temperature diffusion treatment is specifically as follows: the crystal substrate after ion implantation treatment is placed at a predetermined temperature for a predetermined time, and then taken out for natural cooling.
本发明所述的晶体管外延层制作方法，所述预定温度为T，1000摄氏度≤T＜1414摄氏度。In the method for fabricating a transistor epitaxial layer according to the present invention, the predetermined temperature is T, and 1000 degrees Celsius≤T<1414 degrees Celsius.
本发明所述的晶体管外延层制作方法，所述预定温度为T，1100摄氏度≤T≤1200摄氏度。In the method for fabricating a transistor epitaxial layer according to the present invention, the predetermined temperature is T, and 1100 degrees Celsius≤T≤1200 degrees Celsius.
本发明所述的晶体管外延层制作方法，所述离子植入处理采用高能量离子植布机进行离子植入处理。In the method for fabricating the transistor epitaxial layer of the present invention, the ion implantation treatment adopts a high-energy ion implanter to perform the ion implantation treatment.
本发明所述的晶体管外延层制作方法，所述离子植入处理采用百万级电子伏特的离子植布机进行离子植入处理。In the method for fabricating a transistor epitaxial layer of the present invention, the ion implantation treatment adopts an ion implanter with a million electron volts to perform the ion implantation treatment.
本发明所述的晶体管外延层制作方法，所述晶体基板为硅基板，所述离子为磷离子、砷离子、锑离子中的至少1种。In the method for manufacturing a transistor epitaxial layer of the present invention, the crystal substrate is a silicon substrate, and the ions are at least one of phosphorus ions, arsenic ions, and antimony ions.
本发明所述的晶体管外延层制作方法，在离子植入处理之前，还包括调节离子植入剂量，所述离子植入剂量大小依据所需电阻率的大小进行调节。The method for fabricating the transistor epitaxial layer of the present invention further includes adjusting the ion implantation dose before the ion implantation treatment, and the ion implantation dose is adjusted according to the required resistivity.
本发明所述的晶体管外延层制作方法，第一预定深度与离子植入处理次数呈正比。In the method for fabricating the transistor epitaxial layer of the present invention, the first predetermined depth is proportional to the number of ion implantation treatments.
本发明与现有技术相比，本发明是在硅基板(n-p type substrate)基础上，提出有別于目前外延制作方式。利用离子植入机使用高能量植入技术，将高能量离子剂量植入硅基板内。配合使用高温扩散方式，将植入的离子进一步推向硅基板深处，最后形成外延基板，取代目前外延制作方法。藉此方式可以生产高质量、低成本的外延基板。本发明还可以，利用调整植入剂量的大小，可制作不同电阻率的外延。本发明还可以，使用多次高能量离子布植植入，调整外延厚度。本发明还可以，使用多次高温退火的方式，调整外延厚度。本发明还可以，可制作双层外延基板。本发明还可以，可制作适用于高、低压功率器件所需外延基板。Compared with the prior art, the present invention is based on a silicon substrate (n-p type substrate), and is different from the current epitaxy fabrication method. High energy ion doses are implanted into silicon substrates using high energy implantation techniques using an ion implanter. In conjunction with the high temperature diffusion method, the implanted ions are further pushed to the depth of the silicon substrate, and finally an epitaxial substrate is formed, replacing the current epitaxial fabrication method. In this way, high-quality, low-cost epitaxial substrates can be produced. The present invention can also make epitaxy with different resistivity by adjusting the implant dose. The present invention can also use multiple high-energy ion implantation to adjust the epitaxial thickness. In the present invention, the epitaxial thickness can also be adjusted by using multiple high-temperature annealing methods. The present invention can also manufacture a double-layer epitaxial substrate. The present invention can also manufacture epitaxial substrates suitable for high and low voltage power devices.
附图说明Description of drawings
此处所说明的附图用来提供对本发明实施例的进一步理解，构成本申请的一部分，并不构成对本发明实施例的限定。在附图中：The accompanying drawings described herein are used to provide further understanding of the embodiments of the present invention, and constitute a part of the present application, and do not constitute limitations to the embodiments of the present invention. In the attached image:
图1为本发明的制造流程图。FIG. 1 is a manufacturing flow chart of the present invention.
具体实施方式Detailed ways
为使本发明的目的、技术方案和优点更加清楚明白，下面结合实施例和附图，对本发明作进一步的详细说明，本发明的示意性实施方式及其说明仅用于解释本发明，并不作为对本发明的限定。In order to make the purpose, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the embodiments and the accompanying drawings. as a limitation of the present invention.
实施例1Example 1
如图1所示，As shown in Figure 1,
本实施例为了实现较深的掺杂层，其采用多级构造掺杂深度的设计理念，即先采用离子植入处理获得第一预定深度的离子掺杂层，再配合高温处理在第一预定深度的离子掺杂层的基础上使得第一预定深度的离子掺杂层继续扩散，使掺杂物继续向基板深处扩散，从而获得更高深度的第二预定深度的离子掺杂层。从而提高外延层质量，该技术构思的成本较低，操作简单。基于上述构思，所能提供一种晶体管外延层制作方法，所述晶体管外延层制作方法包括至少以下过程：对晶体基板进行一次或多次离子植入处理，使得离子掺杂深度达到第一预定深度；再对离子植入处理后的晶体基板进行高温化扩散处理，使得离子掺杂深度达到第二预定深度并稳定，以此得到离子掺杂深度达到第二预定深度的晶体管外延层。该实施例利用离子植入机使用高能量植入技术，将高能量离子剂量植入硅基板内。配合使用高温扩散的方式，将植入的离子推向硅基板深处，最后形成外延基板，取代目前外延制作方法。藉此方式可以生产高质量、低成本的外延基板。In this embodiment, in order to achieve a deeper doped layer, the design concept of a multi-level structure doping depth is adopted, that is, an ion implantation process is used to obtain an ion doped layer of a first predetermined depth, and then a high temperature process is used to obtain a first predetermined depth of the ion doping layer. On the basis of the deep ion doping layer, the ion doping layer of the first predetermined depth continues to diffuse, so that the dopant continues to diffuse deep into the substrate, thereby obtaining the ion doping layer of a second predetermined depth with a higher depth. Thus, the quality of the epitaxial layer is improved, the cost of the technical concept is low, and the operation is simple. Based on the above concept, a method for fabricating a transistor epitaxial layer can be provided, the method for fabricating a transistor epitaxial layer includes at least the following process: performing one or more ion implantation treatments on the crystal substrate, so that the ion doping depth reaches a first predetermined depth and then perform high temperature diffusion treatment on the crystal substrate after the ion implantation treatment, so that the ion doping depth reaches the second predetermined depth and is stable, thereby obtaining the transistor epitaxial layer with the ion doping depth reaching the second predetermined depth. This embodiment uses an ion implanter to implant a high energy ion dose into a silicon substrate using a high energy implantation technique. In combination with the high-temperature diffusion method, the implanted ions are pushed deep into the silicon substrate, and finally an epitaxial substrate is formed, replacing the current epitaxial fabrication method. In this way, high-quality, low-cost epitaxial substrates can be produced.
参考图1所示，先选择一预定厚度的晶体基板，晶体基板选择硅基板，将预定量的掺杂物装载于高能量离子植入机(High Energy Lon lmplant)中，启动高能量离子植入机对硅基板(si substrate)进行离子植入作业，在其硅基板的上表面向内方向形成以第一预定深度的掺杂层，再然后将其整体放置于高温处理进程中，进行热扩散，迫使掺杂的离子进一步的向硅基板的深度方向扩散到第二预定深度，其所形成的扩散区即为EPl laye。Referring to FIG. 1, first select a crystal substrate with a predetermined thickness, the crystal substrate is a silicon substrate, and a predetermined amount of dopant is loaded into a high energy ion implanter (High Energy Lon Implant) to start the high energy ion implantation. The machine performs ion implantation on the silicon substrate (si substrate), and forms a doping layer with a first predetermined depth inward on the upper surface of the silicon substrate, and then the whole is placed in a high temperature treatment process for thermal diffusion. , the doped ions are forced to further diffuse to the second predetermined depth in the depth direction of the silicon substrate, and the formed diffusion region is the EP1 layere.
实施例2Example 2
如图1所示，As shown in Figure 1,
在上述实施例的基础上，On the basis of the above-mentioned embodiment,
本实施例可以提供一种更加具体的高温处理进程，即所述高温化扩散处理具体为：对离子植入处理后的晶体基板进行渐变升温处理至预定温度、并在预定温度处进行预定时间的保温处理、再由第一预定温度进行渐变降温处理。本实施例采用渐变升温处理，可以使得离子扩散由高浓度缓慢扩展逐渐过渡到低浓度快速扩散，从而致使扩散均匀，获得均匀的外延层。This embodiment can provide a more specific high-temperature treatment process, that is, the high-temperature diffusion treatment is specifically: performing a gradual heating process on the crystal substrate after the ion implantation treatment to a predetermined temperature, and performing a predetermined time at the predetermined temperature. The heat preservation treatment is performed, and then the gradual cooling treatment is performed at the first predetermined temperature. In this embodiment, the gradual heating process is adopted, which can make the ion diffusion gradually transition from slow expansion of high concentration to rapid diffusion of low concentration, so as to make the diffusion uniform and obtain a uniform epitaxial layer.
实施例3Example 3
如图1所示，As shown in Figure 1,
在上述实施例的基础上，On the basis of the above-mentioned embodiment,
本实施例可以提供另外一种更加具体的高温处理进程，即所述高温化扩散处理具体为：对离子植入处理后的晶体基板放置与预定温度进行保温预定时间后取出自然冷却。This embodiment can provide another more specific high-temperature treatment process, that is, the high-temperature diffusion treatment specifically includes: placing the crystal substrate after ion implantation treatment at a predetermined temperature for a predetermined time, and then taking it out for natural cooling.
另外，在上述实施例2和实施例3中，优选的，所述预定温度为T，1000摄氏度≤T＜1414摄氏度。其中还可以设定最佳参数为：预定温度为T，1100摄氏度≤T≤1200摄氏度。所述1414摄氏度为硅融化温度。In addition, in the above Embodiment 2 and Embodiment 3, preferably, the predetermined temperature is T, and 1000 degrees Celsius≤T<1414 degrees Celsius. The optimal parameters can also be set as follows: the predetermined temperature is T, and 1100 degrees Celsius≤T≤1200 degrees Celsius. The 1414 degrees Celsius is the melting temperature of silicon.
另外，在上述实施例中，优选的，所述离子植入处理采用高能量离子植布机进行离子植入处理。In addition, in the above embodiment, preferably, the ion implantation treatment adopts a high-energy ion implanter to perform the ion implantation treatment.
所述离子植入处理采用百万级电子伏特的离子植布机进行离子植入处理。The ion implantation process uses a million electron volt ion implanter to perform the ion implantation process.
所述离子为磷离子、砷离子、锑离子中的至少1种。The ions are at least one of phosphorus ions, arsenic ions, and antimony ions.
在离子植入处理之前，还包括调节离子植入剂量，所述离子植入剂量大小依据所需电阻率的大小进行调节。Before the ion implantation process, the ion implantation dose is also adjusted, and the ion implantation dose is adjusted according to the required resistivity.
第一预定深度与离子植入处理次数呈正比。The first predetermined depth is proportional to the number of ion implantation treatments.
本发明采用多次、多种形式的物理渗透的方式，可以以低成本、高质量的构造出大深度的掺杂层。其先采用高能量离子植入技术，可以解决离子由外界进入基板内部的突变问题，再配合低成本的高温扩散渗透，使其离子自由扩散渗透形成更加深的掺杂层。The present invention adopts the physical infiltration method of multiple times and various forms, and can construct a large-depth doped layer with low cost and high quality. It first adopts high-energy ion implantation technology, which can solve the problem of sudden change of ions entering the substrate from the outside, and then cooperates with low-cost high-temperature diffusion and penetration to make ions free to diffuse and penetrate to form a deeper doped layer.
以上所述的具体实施方式，对本发明的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本发明的具体实施方式而已，并不用于限定本发明的保护范围，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。The specific embodiments described above further describe the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention, and are not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.
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