CN111341834B - Test structure and semiconductor device - Google Patents

Abstract

A test structure and a semiconductor device provided by the present invention, the test structure includes a first doping type region and a second doping type region, the first doping type region includes at least one doping depth sub-region, each The subregions have at least one first active region; the second doping type region includes at least one doping depth subregion, and each subregion has at least one second active region; the first doping type region Adjacent to the second doping type region, the first active region and the second active region are connected in series to form a series circuit, and the current of the test structure is detected through the series circuit. By arranging the first active region and the second active region in the test structure collectively, the present invention can quickly and timely monitor the problem of current short circuit in the active region, and can also save the area of the test structure.

Description

A test structure and semiconductor device

technical field

The invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a test structure and a semiconductor device.

Background technique

WAT (Wafer acceptance test, wafer acceptance test) is an electrical measurement of the chip after the process is completed, and is used to check whether each process meets the standard. The test items include device characteristic test, capacitance test, contact resistance test, breakdown test etc.

In the WAT of the flash memory, it was found that the leakage failure of the flash memory occurred during the short-circuit test of the P-type doped region of the wafer, that is, the problem of current short circuit occurred. After analysis, it was found that it was caused by incomplete etching of STI (Shallow Trench Isolation Region) on the substrate.

Contents of the invention

The invention provides a test structure and a semiconductor device to monitor the current short circuit problem caused by incomplete etching of STI.

In order to solve the above technical problems, the present invention provides a test structure, comprising:

a region of a first doping type comprising at least one sub-region of doping depth, each of said sub-regions having at least one first active region;

a region of a second doping type comprising at least one sub-region of doping depth, each of said sub-regions having at least one second active region;

The first doping type region and the second doping type region are arranged adjacent to each other, the first active region and the second active region are connected in series to form a series circuit, and the test is detected through the series circuit Structure current.

Optionally, the first doping type region includes a first subregion, a second subregion and a third subregion, and the first subregion, the second subregion and the third subregion are separated by a shallow trench isolation structure. interval.

Further, the first active region of the first subregion, the first active region of the second subregion and the first active region of the third subregion are arranged in parallel, and between each of the first active regions separated by shallow trench isolation structures.

Furthermore, the adjacent first active regions in the first subregion are arranged in parallel, the adjacent first active regions in the second subregion are arranged in parallel, and the adjacent first active regions in the third subregion The regions are arranged in parallel, and each of the first active regions is separated by an STI.

Optionally, the second doping type region includes a fourth sub-region, a fifth sub-region and a sixth sub-region, and the fourth sub-region, the fifth sub-region and the sixth sub-region pass through the shallow trench isolation structure interval.

Further, the second active region of the fourth subregion, the second active region of the fifth subregion and the second active region of the sixth subregion are arranged in parallel, and each of the second active regions are separated by shallow trench isolation structures.

Furthermore, the adjacent second active regions in the fourth subregion are arranged in parallel, the adjacent second active regions in the fifth subregion are arranged in parallel, and the adjacent second active regions in the sixth subregion The second active regions are arranged in parallel, and each of the second active regions is separated by a shallow trench isolation structure.

Optionally, a connection point is also included, the connection point is arranged on the first active region and the second active region, and the connection point of the first active region and the second active region is connected The first active area and the second active area are connected in series.

The present invention also provides a semiconductor device, including the above-mentioned test structure.

Optionally, a functional structure is also included, and the functional structure and the test structure are arranged adjacent to each other.

Compared with the prior art, the present invention has the following beneficial effects:

A test structure and a semiconductor device provided by the present invention, the test structure includes a first doping type region and a second doping type region, the first doping type region includes at least one doping depth sub-region, each The subregions have at least one first active region; the second doping type region includes at least one doping depth subregion, and each subregion has at least one second active region; the first doping type region Adjacent to the second doping type region, the first active region and the second active region are connected in series to form a series circuit, and the current of the test structure is detected through the series circuit. By arranging the first active region and the second active region in the test structure collectively, the present invention can quickly and timely monitor the problem of current short circuit in the active region, and can also save the area of the test structure.

Description of drawings

Fig. 1 is a structural schematic diagram of an incomplete STI etching;

FIG. 2 is a top view of a test structure according to an embodiment of the present invention.

Explanation of reference signs:

In Figure 1:

a-protrusion; h2-protrusion groove depth; h1-groove depth of other parts;

In Figure 2:

110-the first sub-region; 111-the first active region of the first sub-region; 120-the second sub-region; 121-the first active region of the second sub-region; 130-the third sub-region; 131-the first The first active region of the three sub-regions;

210-the fourth sub-region; 211-the second active region of the fourth sub-region; 220-the fifth sub-region; 221-the second active region of the fifth sub-region; 230-the sixth sub-region; 231-the first The second active region of the six sub-regions.

Detailed ways

As mentioned in the background art, a current short circuit problem is found in the WAT of the flash memory, and FIG. 1 is a schematic structural diagram of an incomplete STI etching. As shown in Figure 1, the analysis found: Problem 1: Bad protrusion a appeared during STI etching, that is, the groove depth h2 of the protrusion a is smaller than the groove depth h1 of other parts of the STI groove bottom, that is, the STI groove bottom is uneven; the problem 2. The actual etching depth of the STI is less than the etching depth required by the design, resulting in the depth of doping ions (such as P-type doping ions) in the doped region being deeper than the depth of the STI groove, resulting in the problem of current short circuit.

Based on the above analysis, the test structure includes a region of the first doping type and a region of the second doping type, the region of the first doping type includes at least one sub-region with a doping depth, and each sub-region has at least one first doping type source region; the second doping type region, including at least one sub-region of doping depth, each sub-region has at least one second active region; the first doping type region and the second doping type The regions are arranged adjacently, the first active region and the second active region are connected in series to form a series circuit, and the current of the test structure is detected through the series circuit. By arranging the first active region and the second active region in the test structure collectively, the present invention can quickly and timely monitor the problem of current short circuit in the active region, and can also save the area of the test structure.

A test structure and semiconductor device of the present invention will be further described in detail below. The invention will now be described in more detail with reference to the accompanying drawings, in which preferred embodiments of the invention are shown, it being understood that those skilled in the art may modify the invention described herein and still achieve the advantageous effects of the invention. Therefore, the following description should be understood as the broad knowledge of those skilled in the art, but not as a limitation of the present invention.

In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions and constructions are not described in detail since they would obscure the invention with unnecessary detail. It should be appreciated that in the development of any actual embodiment, numerous implementation details must be worked out to achieve the developer's specific goals, such as changing from one embodiment to another in accordance with system-related or business-related constraints. Additionally, it should be recognized that such a development effort might be complex and time consuming, but would nevertheless be merely a routine undertaking for those skilled in the art.

In order to make the purpose and features of the present invention more comprehensible, the specific implementation manners of the present invention will be further described below in conjunction with the accompanying drawings. It should be noted that the drawings are all in a very simplified form and use imprecise ratios, which are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

The present invention provides a test structure, and FIG. 2 is a top view of the test structure in an embodiment of the present invention. As shown in FIG. 2 , the test structure includes a region of a first doping type and a region of a second doping type formed in a substrate, and the regions of the first doping type and the second doping type are adjacently arranged. In this embodiment, the doping type of the first doping type region is P type, and the doping type of the second doping type region is N type. In other embodiments, the doping type of the first doping type region may be N type, and the doping type of the second doping type region may be P type.

The first doping type region may include at least one subregion with a doping depth. In this embodiment, the first doping type region includes, for example, a first subregion (P+ region) 110, a second subregion (PLDD1 area) 120 and a third sub-area (PLDD2 area) 130 . The first sub-region (P+ region) 110 , the second sub-region ( PLDD1 ) 120 and the third sub-region ( PLDD2 ) 130 are arranged adjacently and separated by STI.

The P+ region 110, the PLDD1 region 120, and the PLDD2 region 130 all include at least one first active region, and the active regions between adjacent subregions are arranged in parallel, that is, the first active region of the first subregion region 111, the first active region 121 of the second subregion, and the first active region 131 of the third subregion are arranged in parallel, and each of the first active regions is separated by STI, and at the same time, the Each of the first active regions in the P+ region 110, PLDD1 region 120 and PLDD2 region 130 is arranged in parallel, that is to say, the adjacent first active regions 111 in the first subregion are arranged in parallel, and the second subregion The adjacent first active regions 121 in the third sub-region are arranged in parallel, the adjacent first active regions 131 in the third sub-region are arranged in parallel, and each of the first active regions 111, 121, 131 is separated by STI open. The STI is used to isolate the adjacent first active regions to avoid current short circuit.

Each of the first active regions 111, 121, 131 has a first end and a second end, and each of the first active regions 111, 121, 131 is provided with a connection point 300. In this embodiment, Some of the connection points of the first active regions 111, 121, 131 are arranged on the first end, some of the connection points of the first active regions 111, 121, 131 are arranged on the second end, and are adjacent to the second end. The connection point 300 on an active region is not set at the first end or the second end at the same time, that is to say, the connection points 300 on two first active regions spaced apart from each other are simultaneously located at the first end or the second end. end, two adjacent first active regions, one of their connection points is set at the first end, and the other is set at the second end. In other embodiments, the connection points may all be set at the first end or the second end of the first active region, or between the first end and the second end of the first active region. Each of the first active regions is connected in series by connecting each of the first active regions at the connection point.

The second doping type region is separated from the first doping type region by an intermediate STI, and in this embodiment, the intermediate STI is arranged in parallel with all active regions in the first doping type region , in other embodiments, the middle STI may also be arranged vertically to all active regions in the first doping type region.

The second doping type region may also include at least one sub-region with a doping depth. In this embodiment, the second doping type region includes, for example, a fourth sub-region (N+ region) 210, a fifth sub-region region (NLDD1 region) 220 and a sixth subregion (NLDD2 region) 230 . The fourth sub-region (N+ region) 210, the fifth sub-region (NLDD1 region) 220 and the sixth sub-region (NLDD2 region) 230 are arranged adjacently and separated by STI.

The N+ region 210, the NLDD1 region 220 and the NLDD2 region 230 all include at least one second active region, and the second active regions between adjacent subregions are arranged in parallel, that is, the second active region of the fourth subregion The active region 211, the second active region 221 of the fifth subregion, and the second active region 231 of the sixth subregion are arranged in parallel, and each of the second active regions is separated by STI, and at the same time, Each of the second active regions in the N+ region 210, the NLDD1 region 220 and the NLDD2 region 230 is arranged in parallel, that is, the adjacent second active regions 211 in the fourth subregion are arranged in parallel, and the fifth The adjacent second active regions 221 in the sub-region are arranged in parallel, and the adjacent second active regions 231 in the sixth sub-region are arranged in parallel, and each of the second active regions 211, 221, 231 passes through STIs are spaced apart. The STI is used to isolate the adjacent second active region to avoid current short circuit.

Each of the second active regions 211, 221, 231 has a first end and a second end, and each of the second active regions 211, 221, 231 is provided with a connection point 300. In this embodiment, Part of the connection points 300 of the second active regions 211, 221, 231 are arranged on the first end, and part of the connection points 300 of the second active regions 211, 221, 231 are arranged on the second end, and the corresponding The connection points 300 adjacent to the second active regions 211, 221, 231 are not set at the first end or the second end at the same time, that is to say, the connection points 300 on the two second active regions spaced apart from each other are at the same time Located at the first end or the second end, two adjacent second active regions, one of their connection points is set at the first end, and the other is set at the second end. In other embodiments, the connection points may all be set at the first end or the second end of the first active region, or between the first end and the second end of the first active region. Each of the second active regions is connected in series by connecting each of the second active regions at the connection point. The first active region is connected in series with the second active region to form a series circuit, one end of the series circuit can be connected to a high voltage Vh, and the other end to be connected to a low voltage Vl to detect the current flowing through the first active region. The current sum of the source region and the second active region is used to determine whether there is an active region with a current short circuit.

Please continue to refer to FIG. 2 , the present invention also provides a semiconductor device, such as a flash memory. The semiconductor device includes a functional structure and a test structure, and the functional structure and the test structure are adjacently arranged. The functional structure includes at least one first active region and at least one second active region, the first active region in the functional structure corresponds to the first active region of the test structure one by one, and simultaneously prepared, that is to say, the number of first active regions in the functional structure is the same as the number of first active regions in the test structure, and when the first active region is prepared in the functional structure, the number of first active regions is simultaneously prepared in the test structure An identical (same doping depth) first active region. The second active regions in the functional structure and the second active regions of the test structure are in one-to-one correspondence, and are prepared at the same time, that is to say, the number of the second active regions in the functional structure is the same as that of the test structure. The number of the second active regions is the same, and a same (same doping depth) second active region is prepared in the test structure at the same time when the functional structure is prepared to prepare the second active region. In this embodiment, it can be judged whether there is a problem in the first active region and the second active region in the functional structure through the sum of currents in the active regions in the test structure. The first active area and the second active area in the test structure make it possible to quickly and timely monitor the problem of the short circuit of the active area current during WAT. The active area is arranged in a concentrated manner, which saves the area of the test structure.

To sum up, the present invention provides a test structure and a semiconductor device. The test structure includes a first doping type region and a second doping type region, and the first doping type region includes at least one sub-region of doping depth. region, each subregion has at least one first active region; the second doping type region includes at least one doping depth subregion, and each subregion has at least one second active region; the first doping type The impurity type region is adjacent to the second doping type region, the first active region and the second active region are connected in series to form a series circuit, and the current of the test structure is detected through the series circuit. By arranging the first active region and the second active region in the test structure collectively, the present invention can quickly and timely monitor the problem of current short circuit in the active region, and can also save the area of the test structure.

In addition, it should be noted that, unless otherwise specified or pointed out, the descriptions of the terms "first", "second", etc. in the specification are only used to distinguish each component, element, step, etc. in the specification, rather than to express The logical relationship or sequential relationship between various components, elements, and steps, etc.

It can be understood that although the present invention has been disclosed above with preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or be modified to be equivalent to equivalent changes. Example. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention, which do not deviate from the technical solution of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims (10)

1. A test structure, characterized in that, comprising: a region of a first doping type comprising at least one sub-region of doping depth, each of said sub-regions having at least one first active region; The second doping type region includes at least one sub-region with doping depth, each of the sub-regions has at least one second active region, wherein the doping type of the first doping type region is P type, The doping type of the second doping type region is N type, or, the doping type of the first doping type region is N type, and the doping type of the second doping type region is P type; The first doping type region and the second doping type region are arranged adjacent to each other, the first active region and the second active region are connected in series to form a series circuit, and the test is detected through the series circuit Structure current. 2. The test structure according to claim 1, wherein the first doping type region comprises a first sub-region, a second sub-region and a third sub-region, the first sub-region, the second sub-region The region and the third sub-region are separated by a shallow trench isolation structure. 3. The test structure according to claim 2, wherein the first active region of the first subregion, the first active region of the second subregion, and the first active region of the third subregion arranged in parallel, and each of the first active regions is separated by a shallow trench isolation structure. 4. The test structure according to claim 3, wherein the adjacent first active regions in the first sub-region are arranged in parallel, and the adjacent first active regions in the second sub-region are arranged in parallel It is set that the adjacent first active regions in the third sub-region are arranged in parallel, and each of the first active regions is separated by STI. 5. The test structure according to claim 1, wherein the second doping type region comprises a fourth sub-region, a fifth sub-region and a sixth sub-region, the fourth sub-region, the fifth sub-region The region and the sixth subregion are separated by a shallow trench isolation structure. 6. The test structure according to claim 5, wherein the second active region of the fourth subregion, the second active region of the fifth subregion, and the second active region of the sixth subregion arranged in parallel, and each of the second active regions is separated by a shallow trench isolation structure. 7. The test structure according to claim 6, wherein the adjacent second active regions in the fourth subregion are arranged in parallel, and the adjacent second active regions in the fifth subregion are arranged in parallel It is set that the adjacent second active regions in the sixth sub-region are arranged in parallel, and each of the second active regions is separated by a shallow trench isolation structure. 8. The test structure according to claim 1, further comprising a connection point, the connection point being arranged on the first active region and the second active region, the first active region and the second active region The connection point of the second active area connects the first active area and the second active area in series. 9. A semiconductor device, comprising the test structure according to any one of claims 1-8. 10. The semiconductor device according to claim 9, further comprising a functional structure, the functional structure and the test structure are arranged adjacent to each other.