CN111430297B - Semiconductor structure and method of forming the same - Google Patents

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the method comprises the following steps: providing a first substrate comprising a first chip region comprising a first region and a second region, the first substrate having opposing first and second faces; forming a first functional unit on a first face of the first region; forming a peelable module and a peelable film on the first side of the second region; providing a second substrate, wherein the second substrate comprises a second chip area, and a second functional unit is arranged in the second chip area; bonding the first side of the first substrate towards the second substrate surface after forming the peelable module; after bonding the first side of the first substrate towards the second substrate surface, removing the first substrate to expose the peelable module. Therefore, the manufacturing time of the chip is reduced, the manufacturing cost of the chip is reduced, and the yield of the chip is improved.

Description

Semiconductor structure and method of forming the same

technical field

The present invention relates to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.

Background technique

Today, the use of artificial intelligence is appearing in more and more fields, such as autonomous driving, image recognition, medical diagnosis, games, financial data analysis and search engines.

In order to meet the more functional requirements of artificial intelligence for a single emulated chip, two wafers with different functions are usually bonded, so that a single emulated chip has different functions.

However, existing chips take longer to manufacture, cost more, and require improved yields.

SUMMARY OF THE INVENTION

The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to reduce the chip manufacturing time, reduce the chip manufacturing cost, and improve the chip yield.

In order to solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing a first substrate, the first substrate includes a first chip area, and the first chip area includes a first area and a second chip area. Two areas, the first substrate has opposite first and second sides; a first functional unit is formed on the first side of the first area; peelable is formed on the first side of the second area module, and the side surface of the peelable module and the surface facing away from the first side form a peelable film surrounding the peelable module; a second substrate is provided, the second substrate includes a second chip area, the There is a second functional unit in the second chip area; after the peelable module is formed, the first surface of the first substrate is bonded toward the surface of the second substrate, and the first surface is perpendicular to the first surface. In the direction, the first chip area overlaps with the second chip area, and the circuit of the first functional unit is electrically interconnected with the circuit of the second functional unit; when the first surface of the first substrate faces the After the surface of the second substrate is bonded, the first substrate is removed to expose the peelable module.

Optionally, the method further includes: after removing the first substrate, removing the peelable module and the peelable film to form a first opening.

Optionally, the process of removing the strippable film includes a wet etching process.

Optionally, the method for removing the peelable module includes: after removing the peelable film, or while removing the peelable film, using several suction cups to adsorb on the surface of the peelable module, and pulling the plurality of suction cups to remove the peelable module.

Optionally, the method for removing the peelable module includes: using a plurality of suction cups to adsorb on the surface of the peelable module, and pulling the plurality of suction cups to remove the peelable module.

Optionally, the method for removing the peelable film includes: after removing the peelable module, etching the peelable film until the peelable film is removed.

Optionally, it further includes: forming a fifth dielectric layer in the first opening, and a fourth metal interconnection layer located in the fifth dielectric layer, the fourth metal interconnection layer and the second The circuits of the functional units are electrically interconnected, and the fourth metal interconnection layer is exposed on the surface of the fifth dielectric layer.

Optionally, it further includes: after forming the first opening, providing a third chip; embedding the third chip into the first opening; after embedding the third chip into the first opening, inserting the third chip into the first opening. The third chip is bonded to the second substrate, and the circuit of the third chip is electrically interconnected with the circuit of the second functional unit.

Optionally, the circuit of the second functional unit includes a second functional circuit and a second metal interconnection layer, the second functional circuit is electrically interconnected with the second metal interconnection layer, and the second The surface of the substrate exposes the surface of the second metal layer.

Optionally, the third chip has a third functional circuit and a third metal interconnection layer, the third functional circuit is electrically interconnected with the third metal interconnection layer, and the surface of the third chip is exposed. the third metal interconnection layer; the method of bonding the third chip and the second substrate comprising: after removing the peelable module and the peelable film, exposing the second surface to the second substrate The surface of two metal interconnection layers; the second metal interconnection layer and the third metal interconnection layer are bonded.

Optionally, it further includes: after bonding the third chip and the second substrate, forming a first conductive plug in the third chip, and the first conductive plug is interconnected with the second metal The layers are electrically interconnected, and the first conductive plugs are electrically interconnected with circuitry within the third chip.

Optionally, it further includes: after removing the first substrate, forming a second conductive plug penetrating the strippable module and the strippable film, the second conductive plug and the circuit of the strippable module are electrically interconnected. and the second conductive plug is electrically interconnected with the circuit of the second functional unit.

Optionally, the method for forming the strippable film and the strippable module includes: forming an initial strippable module on the first surface of the second region; and etching the initial strippable module to form the strippable module A module and a peelable film opening surrounding all side walls of the peelable module; a peelable film is formed in the peelable film opening and on the surface of the peelable module.

Optionally, it further includes: before forming the initial peelable module, forming a first dielectric layer on the first surface of the second region, the material of the first dielectric layer and the material of the peelable film The same; the method for forming the peelable module further includes: forming the initial peelable module on the surface of the first dielectric layer.

Optionally, the method for forming the peelable film includes: before forming the peelable module, forming a third dielectric layer on the first surface of the second region and a peelable film in the third dielectric layer. stripping the groove; forming the strippable module in the strippable groove; forming a fourth medium layer on the surface of the strippable module.

Optionally, the method further includes: before bonding the first substrate and the second substrate, forming a first adhesive layer on the surface of the first functional unit.

Optionally, the method further includes: before bonding the first substrate and the second substrate, forming a first adhesive layer on the surface of the first functional unit and the surface of the peelable film.

Optionally, it further includes: before bonding the first substrate and the second substrate, forming a first metal interconnection layer in the first adhesive layer of the first region, the first adhesive layer The surface of the bonding layer exposes the surface of the first metal interconnection layer, and the first metal interconnection layer is electrically interconnected with the circuit of the first functional unit.

Optionally, the method further includes: before bonding the first substrate and the second substrate, forming a second adhesive layer on the second chip area overlapping the first area.

Optionally, the process of removing the first substrate includes a thinning process.

Optionally, the thinning process includes one or a combination of an etch-back process or a chemical mechanical polishing process.

Optionally, the material of the peelable film includes one of anti-reflection material, photoresist or glue.

Optionally, the circuit of the first functional unit includes a logic control circuit or a memory circuit.

Optionally, the circuit of the second functional unit includes a logic control circuit or a memory circuit.

Optionally, the peelable module has one or a combination of one or more of a logic control circuit, a memory circuit, a dummy gate structure and a micro-motor system.

Optionally, the third chip has a logic control circuit, a memory circuit, and a combination of one or more of a micro-motor system.

Correspondingly, the technical solution of the present invention also provides a semiconductor structure formed by the above-mentioned forming method, comprising: a second substrate, the second substrate includes a second chip area, and the second chip area has a second functional unit a first functional unit located on the second chip area, the first functional unit is bonded to the second substrate, and the circuit of the first functional unit is electrically interconnected with the circuit of the second functional unit ; a peelable module on the second chip area; a peelable film on the side of the peelable module and a surface facing the second substrate surface and surrounding the peelable module.

Compared with the prior art, the technical scheme of the present invention has the following beneficial effects:

In the method for forming a semiconductor structure according to the technical solution of the present invention, the adhesiveness between the peelable film and the peelable module and between the peelable film and the surface of the second substrate is poor. In one aspect, forming a peelable film surrounding the peelable module on a side of the peelable module and a surface facing away from the first side when a defect in the peelable module is detected in the manufacturing process, and Removing the first substrate to expose the surface of the peelable module, can remove the peelable module after the first substrate and the second substrate are bonded, and embed or embed at the original peelable module and the peelable film Other modules are formed, so that the bonded first functional unit and the second functional unit can be reused, so as to improve the yield of the chip, and reduce the manufacturing time and cost of the chip. On the other hand, when the chip requires a variety of different functions, a peelable film surrounding the peelable module is formed on the side of the peelable module and the surface facing away from the first side, and the first surface is removed. a substrate to expose the surface of the peelable module, after the first substrate and the second substrate are bonded, the first functional unit and the second functional unit can be used as a basic module, and the peelable film can be used at the original peelable module Other chips are embedded at the same base module design, so that different functional module designs are superimposed on the same basic module design, so that the chip has different functions, which reduces the overall design time and complexity of the chip, and reduces the manufacturing time and cost of the chip.

Description of drawings

1 to 10 are schematic cross-sectional structural views of each step of a method for forming a semiconductor structure according to an embodiment of the present invention;

11 is a schematic cross-sectional structure diagram of steps of a method for forming a semiconductor structure according to another embodiment of the present invention;

12 is a schematic cross-sectional structure diagram of steps of a method for forming a semiconductor structure according to another embodiment of the present invention;

13 to FIG. 16 are schematic cross-sectional structural views of various steps of a method for forming a semiconductor structure according to another embodiment of the present invention.

Detailed ways

As described in the background art, in order to meet the more functional requirements of artificial intelligence for a single simulation chip, two wafers with different functional modules are usually bonded, and the bonded wafers are cut to form several wafers with various functions. functional chip.

However, on the one hand, after the two wafers are bonded, when the formed functional module has defects, the defective part cannot be replaced, and a new wafer needs to be remanufactured, resulting in some defects in the old wafer. Chips are scrapped, reducing chip yield. On the other hand, when chips with different functions are required, a new design of the entire chip is required, thereby increasing the overall design time and complexity of the chip. To sum up, the existing chip manufacturing time is long, the cost is high, and the yield rate needs to be improved.

In order to solve the above-mentioned technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure. When the peelable module has a manufacturing defect, or when a chip with different functional modules needs to be formed, the peelable film and the peelable module are formed. , after the first substrate and the second substrate are bonded, the first substrate and the second substrate after bonding can be reused by removing the peelable film and the peelable module, so as to improve the yield of the chip and reduce the number of chips manufacturing time and cost.

In order to make the above objects, features and beneficial effects of the present invention more clearly understood, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 to FIG. 10 are schematic cross-sectional structural diagrams of various steps of a method for forming a semiconductor structure according to an embodiment of the present invention.

Referring to FIG. 1, a first substrate 100 is provided, the first substrate 100 includes a first chip area, the first chip area A includes a first area I and a second area II, and the first substrate 100 has opposite The first side 101 and the second side 102 .

The material of the first substrate 100 is a semiconductor material.

In this embodiment, the material of the first substrate 100 is silicon. In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-component semiconductor material composed of Group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator. Among them, the multi-component semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

Referring to FIG. 2 , a first functional unit 110 is formed on the first surface 101 of the first region I.

In this embodiment, the material of the first functional unit 110 is silicon. In other embodiments, the material of the first functional unit includes silicon carbide, silicon germanium, a multi-component semiconductor material composed of Group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator. Among them, the multi-component semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

In this embodiment, the first functional unit 110 includes a device layer (not shown). The device layer may include device structures, eg, PMOS transistors or NMOS transistors. The device layer may also include an interconnect structure electrically connected to the device structure, and an insulating layer surrounding the device structure and the interconnect structure.

In this embodiment, the circuit of the first functional unit 110 includes a logic control circuit, and the logic control circuit is used to perform logic control on the circuit of the second functional unit formed subsequently.

In another embodiment, the circuit of the first functional unit includes a memory circuit.

In this embodiment, the process of forming the first functional unit 110 includes a deposition process and an etching process.

Subsequently, a peelable module is formed on the first surface of the second area II, and the side surface of the peelable module and the surface 101 facing away from the first surface form a peelable film surrounding the peelable module , please refer to FIG. 3 to FIG. 5 for the specific steps of forming the peelable film and the peelable module.

It should be noted that, in this embodiment, although the first functional unit 110 is formed before the peelable module, the first functional unit 110 may also be formed after the peelable module.

Referring to FIG. 3 , an initial peelable module 121 is formed on the first surface 101 of the second region II.

In this embodiment, the material of the initial peelable module 121 is silicon. In other embodiments, the material of the initial strippable module includes silicon carbide, silicon germanium, a multi-component semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator. Among them, the multi-component semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

In this embodiment, the initial peelable module 121 has a device layer (not shown) in it. The device layer may include device structures, eg, PMOS transistors or NMOS transistors. The device layer may also include an interconnect structure electrically connected to the device structure, and an insulating layer surrounding the device structure and the interconnect structure.

In other embodiments, the initial peelable module has a cavity for forming a microelectromechanical system therein and an inductive membrane on the cavity.

In another embodiment, before forming the initial peelable module, a first dielectric layer is formed on the first surface of the second region, the material of the first dielectric layer and the material of the peelable film same. And, forming the initial peelable module on the first surface of the second region, specifically, refers to forming the initial peelable module on the surface of the first dielectric layer.

In this embodiment, the process of forming the initial strippable module 121 includes a deposition process and an etching process.

Referring to FIG. 4 , the initial strippable module 121 is etched to form the strippable module 120 and the strippable film opening 122 surrounding the entire sidewall of the strippable module 120 .

In this embodiment, the method for forming the peelable film opening 122 includes: forming a first patterned layer (not shown) on the surface of the first functional unit 110 and part of the surface of the initial peelable module 121 ; The first patterned layer is a mask, and the initial strippable module 121 is etched until the surface of the first substrate 100 is exposed.

In this embodiment, the process of etching the initial strippable module 121 includes a wet etching process or a dry etching process.

In this embodiment, after the peelable film opening 122 is formed, the first patterned layer is removed.

In this embodiment, the peelable module 120 has one or a combination of one or more of a logic control circuit, a memory circuit and a dummy gate structure.

In other embodiments, the peelable module also has a micro-electromechanical system therein.

Referring to FIG. 5 , a peelable film 123 is formed in the peelable film opening 122 and on the surface of the peelable module 120 .

In this embodiment, the method for forming the peelable film 123 includes: forming an initial peelable film (not shown) in the peelable film opening 122 , on the surface of the first functional unit 110 and on the surface of the peelable module 120 . A second patterned layer (not shown) is formed on the peelable film opening 122 and the initial peelable film surface on the peelable module 120; using the second patterned layer as a mask, the The initial peelable film is etched until the surface of the first functional unit 110 is exposed.

The process of etching the initial strippable film includes a wet etching process or a dry etching process.

In this embodiment, after the peelable film 123 is formed, the second patterned layer is removed.

In this embodiment, the peelable module 120 has one or a combination of one or more of a logic control circuit, a memory circuit, a dummy gate structure, and a micro-motor system.

In this embodiment, the material of the peelable film 123 includes one of anti-reflection material, photoresist or glue.

In this embodiment, before the first substrate 100 and the second substrate are subsequently bonded, a first adhesive layer 111 is formed on the surface of the first functional unit 110, and the first adhesive layer is A first metal interconnect layer 112 is formed therein. The surface of the first adhesive layer 111 exposes the surface of the first metal interconnection layer 112 , and the first metal interconnection layer 112 is electrically interconnected with the circuit of the first functional unit 110 .

Therefore, after the first substrate 100 and the second substrate are subsequently bonded, the bonding strength between the first functional unit 110 and the second substrate can be increased through the first adhesive layer 111 . In addition, through the first metal interconnection layer 112 , the electrical interconnection between the circuit of the first functional unit 110 and the circuit of the second functional unit formed subsequently can be realized.

In another embodiment, before the first substrate and the second substrate are subsequently bonded, a first adhesive layer is formed on the surface of the first functional unit and the surface of the peelable film.

In other embodiments, the first adhesive layer is not formed.

Referring to FIG. 6 , a second substrate 200 is provided. The second substrate 200 includes a second chip area B, and the second chip area B has a second functional unit 210 therein.

In this embodiment, the material of the second functional unit 210 is silicon. In other embodiments, the material of the second functional unit includes silicon carbide, silicon germanium, a multi-component semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator. Among them, the multi-component semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

In this embodiment, the second functional unit 210 includes a device layer (not shown). The device layer may include device structures, eg, PMOS transistors or NMOS transistors. The device layer may also include an interconnect structure electrically connected to the device structure, and an insulating layer surrounding the device structure and the interconnect structure.

In this embodiment, the circuit of the second functional unit 210 includes a second functional circuit 211 and a second metal interconnection layer 212 , and the second functional circuit 211 and the second metal interconnection layer 212 are electrically interconnected , and the second metal layer surface 212 is exposed on the surface of the second substrate 200 .

In this embodiment, the second metal interconnection layer 212 is used for bonding with the third metal interconnection layer of the third chip provided subsequently, so as to electrically interconnect the second functional circuit 211 with the third chip .

In this embodiment, the second functional circuit 211 includes a memory circuit.

In another embodiment, the second functional circuit includes a logic control circuit.

In this embodiment, the process of forming the second functional unit 210 includes a deposition process and an etching process.

In another embodiment, the method of forming the semiconductor structure further includes: before bonding the first substrate and the second substrate, on the second chip area overlapping the first area A second adhesion layer is formed, and a fifth metal interconnect layer is formed within the second adhesion layer. The surface of the second adhesive layer exposes the surface of the fifth metal interconnection layer, and the fifth metal interconnection layer is electrically interconnected with the circuit of the second functional unit.

Therefore, after the first substrate and the second substrate are subsequently bonded, the bonding strength of the first functional unit and the second functional unit can be increased through the second adhesive layer. And, by bonding the first metal interconnection layer and the fifth metal interconnection layer, electrical interconnection between the circuit of the first functional unit and the circuit of the second functional unit can be realized.

In yet another embodiment, before bonding the first substrate and the second substrate, a second adhesive layer (not shown) is formed on the entire second chip area.

Referring to FIG. 7 , after the peelable module 120 is formed, the first surface 101 of the first substrate 100 is bonded toward the surface of the second substrate 200 in a direction perpendicular to the first surface 101 , the first chip area A and the second chip area B overlap, and the circuit of the first functional unit 110 is electrically interconnected with the circuit of the second functional unit 210 .

Referring to FIG. 8 , after the first surface 101 of the first substrate 100 is bonded toward the surface of the second substrate 200 , the first substrate 100 is removed to expose the peelable module 120 .

The adhesion between the peelable film 123 and the peelable module 120 and between the peelable film 123 and the surface of the second substrate 200 is poor. On the one hand, when it is detected that the peelable module 120 has defects in the manufacturing process, a peelable module surrounding the peelable module is formed on the side of the peelable module 120 and the surface facing away from the first surface 101 . The film 123 is removed, and the first substrate 100 is removed to expose the surface of the peelable module 120. After the first substrate 100 and the second substrate 200 are bonded, the peelable module 120 can be removed, and the original peelable module 120 can be removed. Other modules are embedded or formed at the module 120 and the peelable film 123, so that the bonded first functional unit 110 and the second functional unit 120 can be reused, so as to improve the yield of the chip and reduce the manufacturing of the chip time and cost. On the other hand, when the chip requires a variety of different functions, by forming a peelable film 123 surrounding the peelable module 120 on the side of the peelable module 120 and the surface facing away from the first surface 101, and The first substrate 100 is removed to expose the surface of the peelable module 120, and after the first substrate 100 and the second substrate 200 are bonded, the first functional unit 110 and the second functional unit 120 can be used as basic modules , embed other chips at the original strippable module 120 and the strippable film 123, thereby realizing the superimposition of different functional module designs on the same basic module design, so that the chips have different functions, reducing the overall design time and complexity of the chip degree, and, reducing the manufacturing time and cost of chips.

In this embodiment, the process of removing the first substrate 100 includes a thinning process.

Specifically, in this embodiment, after the first surface 101 of the first substrate 100 is bonded toward the surface of the second substrate 200 , a thinning process is performed on the first substrate 100 until the exposed The first functional unit 110 and the peelable module 120 .

The thinning process includes one or a combination of an etch-back process or a chemical mechanical polishing process.

In another embodiment, the first substrate is used as a carrier substrate, and the first substrate is glued with the first functional unit, the peelable module and the peelable film. Thus, the first substrate is removed by using a wet etching process.

Referring to FIG. 9 , after the first substrate 100 is removed, the peelable module 120 and the peelable film 123 are removed to form a first opening 140 .

In this embodiment, the process of removing the peelable film 123 includes a wet etching process.

In this embodiment, the etching solution used in the wet etching process includes an acidic solution.

In this embodiment, the method for removing the peelable module 120 includes: after removing the peelable film 123 , using several suction cups (not shown) to adsorb on the surface of the peelable module 120 , and pulling out the suction cups to remove the peelable module 120 .

In another embodiment, the method for removing the peelable module includes: while removing the peelable film, using a plurality of suction cups (not shown) to adsorb on the surface of the peelable module, and pulling out the peelable film. the suction cups to remove the peelable module.

In yet another embodiment, the method for removing the peelable module includes: using a plurality of suction cups to adsorb on the surface of the peelable module, and pulling the plurality of suction cups to remove the peelable module. The method of removing the peelable film includes: after removing the peelable module, etching the peelable film until the peelable film is removed.

Referring to FIG. 10 , after the first opening 140 is formed, a third chip 300 is provided; the third chip 300 is embedded in the first opening 140 ; the third chip 300 is embedded in the first opening 140 Then, the third chip 300 is bonded to the second substrate 200 , and the circuit of the third chip 300 is electrically interconnected with the circuit of the second functional unit 210 .

In this embodiment, the third chip 300 has a third functional circuit 311 and a third metal interconnection layer 312, the third functional circuit 311 is electrically interconnected with the third metal interconnection layer 312, and , the third metal interconnection layer 312 is exposed on the surface of the third chip 300 .

The method of bonding the third chip 300 to the second substrate 200 includes: after the peelable module 120 and the peelable film 123 are removed, the second surface 102 exposes the second metal interconnection The surface of the layer 212; the second metal interconnection layer 212 and the third metal interconnection layer 312 are bonded.

Thus, by bonding the second metal interconnection layer 212 and the third metal interconnection layer 312 , electrical interconnection between the second functional circuit 211 and the third functional circuit 311 is achieved.

In another embodiment, after the third chip is bonded to the second substrate, a first conductive plug is formed in the third chip, and the first conductive plug is interconnected with a second metal The layers are electrically interconnected, and the first conductive plugs are electrically interconnected with circuitry within the third chip. Thus, by electrically interconnecting the first conductive plug and the second metal interconnection layer, the second functional circuit is electrically interconnected with the circuit in the third chip.

In this embodiment, the third chip 300 includes one or a combination of a logic control circuit, a memory circuit, and a micro-motor system.

Specifically, in this embodiment, the third functional circuit 311 includes one or a combination of a logic control circuit, a memory circuit, and a micro-motor system.

In this embodiment, after the third chip 300 and the second substrate 200 are bonded, a second dielectric layer 320 is filled in the gap between the first opening 140 and the third chip 300 , so as to ensure the insulation between the circuit of the third chip 300 and other devices.

In another embodiment, after the third chip 300 is bonded to the second substrate 200 , a second dielectric layer is formed on the surface of the third chip 300 to further ensure the third chip 300 The insulation between the circuit and other devices is improved, and at the same time, the third chip 300 is protected, and the influence of the subsequent deposition, etching and other processes on the third chip 300 is reduced.

Correspondingly, an embodiment of the present invention further provides a semiconductor structure formed by the above-mentioned method for forming a semiconductor structure, please refer to FIG. 8 , comprising: a second substrate 200 , the second substrate 200 includes a second chip region B, the The second chip area B has a second functional unit 210; the first functional unit 110 located on the second chip area B, the first functional unit 110 is bonded to the second substrate 200, and the The circuit of the first functional unit 110 is electrically interconnected with the circuit of the second functional unit 210; the peelable module 120 on the second chip area B; on the side of the peelable module 120 and toward the second substrate 200 surface, and surrounds the peelable film 123 of the peelable module 120 .

11 is a schematic cross-sectional structure diagram of a method for forming a semiconductor structure according to another embodiment of the present invention. The difference between this embodiment and the embodiments shown in FIGS. 1 to 10 is that the devices formed in the first opening 140 are different 11 , on the basis of FIG. 9 , after the first opening 140 is formed, a fifth dielectric layer 400 is formed in the first opening 140 , and a fourth dielectric layer 400 located in the fifth dielectric layer 400 is formed. The metal interconnection layer 410 , the fourth metal interconnection layer 410 is electrically interconnected with the circuit of the second functional unit 210 , and the fourth metal interconnection layer 410 is exposed on the surface of the fifth dielectric layer 400 .

Therefore, through the fourth metal interconnection layer 410, the circuit of the second functional unit 210 can be electrically interconnected with other devices.

12 is a schematic cross-sectional structure diagram of a method for forming a semiconductor structure according to another embodiment of the present invention. The difference between this embodiment and the embodiments shown in FIGS. 1 to 10 is that after the first substrate 100 is removed, all parts are not removed. The peelable module 120 is described.

Referring to FIG. 12 based on FIG. 8 , after the first substrate 100 is removed, a second conductive plug 420 is formed through the peelable module 120 and the peelable film 123 . The second conductive plug 420 is electrically interconnected with the circuit of the peelable module 120 , and the second conductive plug 420 is electrically interconnected with the circuit of the second functional unit 210 .

Therefore, when the peelable module 120 is not removed, the circuit of the peelable module 120 and the circuit of the second functional unit 210 can be electrically interconnected through the second conductive plug 420 .

In this embodiment, the method for forming the second conductive plug 420 includes: after removing the first substrate 100 , forming a third patterning layer on the surface of the first functional unit 110 and the surface of the peelable module 120 , the third patterned layer exposes part of the surface of the strippable module 120; using the third patterned layer as a mask, the strippable module 120 is etched until the second functional unit 210 is exposed The surface of the second metal interconnect layer 212 in the inside to form a plug opening (not shown) through the strippable module 120 and the strippable film 123; the second conductive layer is formed in the plug opening Plug 420.

The process of forming the second conductive plug 420 in the plug opening includes a deposition process.

In this embodiment, the material of the second conductive plug 420 includes a metal material.

13 to 16 are schematic cross-sectional structural diagrams of each step of a method for forming a semiconductor structure according to another embodiment of the present invention. The difference between this embodiment and the embodiment shown in FIGS. The method of peeling off the film is different.

Referring to FIG. 13 based on FIG. 2 , a third dielectric layer 500 and a peelable groove 510 in the third dielectric layer 500 are formed on the first surface 101 of the second region II.

In this embodiment, the process of forming the third dielectric layer 500 includes a deposition process.

In this embodiment, the method for forming the third dielectric layer 500 and the peelable groove 510 includes: forming an initial third dielectric layer (not shown) on the first surface 101 of the second region II ; A fourth patterned layer (not shown) is formed on the surface of the first functional unit 110 and the surface of the initial third dielectric layer, and the fourth patterned layer exposes part of the surface of the initial third medium layer ; Using the fourth patterned layer as a mask, the initial third dielectric layer is etched until the surface of the first substrate 100 is exposed, so as to form the third dielectric layer 500 and the peelable groove 510 .

In another embodiment, after the initial third dielectric layer is etched, the surface of the first substrate is not exposed, that is, after the peelable groove is formed, in a direction perpendicular to the first surface 101 , the material of the initial third dielectric layer is provided between the peelable groove and the first substrate.

Referring to FIG. 14 , a strippable module 520 is formed in the strippable groove 510 ; a fourth dielectric layer 530 is formed on the surface of the strippable module 520 .

The third dielectric layer 500 and the fourth dielectric layer 530 constitute a peelable film 540 .

In this embodiment, the material of the peelable module 520 is silicon. In other embodiments, the material of the strippable module includes silicon carbide, silicon germanium, a multi-component semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator. Among them, the multi-component semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

In this embodiment, the peelable module 520 has a device layer (not shown) in it. The device layer may include device structures, eg, PMOS transistors or NMOS transistors. The device layer may also include an interconnect structure electrically connected to the device structure, and an insulating layer surrounding the device structure and the interconnect structure.

In this embodiment, the peelable module 520 has one or a combination of one or more of a logic control circuit, a memory circuit and a dummy gate structure.

In other embodiments, the peelable module 520 also has a cavity for forming a microelectromechanical system and an induction film on the cavity. Therefore, the peelable module 520 also has a micro-motor system.

In this embodiment, the process of forming the strippable module 520 includes a deposition process and an etching process.

In this embodiment, the method for forming the fourth dielectric layer 530 includes: depositing an initial fourth dielectric layer (not shown) on the surface of the first functional unit 110 and the surface of the peelable module 520; A fifth patterned layer (not shown) is formed on the surface of the initial fourth dielectric layer on the surface of the strippable module 520; using the fifth patterned layer as a mask, the initial fourth dielectric layer is etched until all parts are exposed. the surface of the first functional unit 110 to form the fourth dielectric layer 530 .

In this embodiment, after the fourth dielectric layer 530 is formed, the fifth patterned layer is removed.

Referring to FIG. 15 , a second substrate 200 is provided, the second substrate 200 includes a second chip area B, and the second chip area B has a second functional unit 210 ; after the peelable module 520 is formed, the The first surface 101 of the first substrate 100 is bonded toward the surface of the second substrate 200 , and in the direction perpendicular to the first surface 101 , the first chip area A and the second chip area B overlap, And, the circuit of the first functional unit 110 is electrically interconnected with the circuit of the second functional unit 210 .

In this embodiment, the second substrate 200 is the same as the second substrate in the embodiment shown in FIG. 1 to FIG. 10 , and details are not described herein again.

Referring to FIG. 16 , after the first surface 101 of the first substrate 100 is bonded toward the surface of the second substrate 200 , the first substrate 100 is removed to expose the peelable module 520 .

In this embodiment, the method for removing the first substrate 100 is the same as the method in the embodiment shown in FIG. 1 to FIG. 10 , and details are not repeated here.

Correspondingly, an embodiment of the present invention further provides a semiconductor structure formed by the above-mentioned method for forming a semiconductor structure, please refer to FIG. 16 , comprising: a second substrate 200 , the second substrate 200 includes a second chip area B, the The second chip area B has a second functional unit 210; the first functional unit 110 located on the second chip area B, the first functional unit 110 is bonded to the second substrate 200, and the The circuit of the first functional unit 110 is electrically interconnected with the circuit of the second functional unit 210; the peelable module 520 on the second chip area B; on the side of the peelable module 520 and toward the second substrate 200 surface, and surrounds the peelable film 540 of the peelable module 120 .

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be based on the scope defined by the claims.

Claims (27)

1. A method for forming a semiconductor structure, comprising: providing a first substrate, the first substrate including a first chip region, the first chip region including a first region and a second region, the first substrate having opposing first and second sides; forming a first functional unit on the first surface of the first region; A peelable module is formed on the first surface of the second area, and a side surface of the peelable module and a surface facing away from the first surface form a peelable film surrounding the peelable module; providing a second substrate, the second substrate includes a second chip region, the second chip region has a second functional unit; After the peelable module is formed, the first surface of the first substrate is bonded toward the surface of the second substrate, and in a direction perpendicular to the first surface, the first chip area and the second surface are bonded. The chip areas overlap, and the circuit of the first functional unit is electrically interconnected with the circuit of the second functional unit; After bonding the first side of the first substrate toward the second substrate surface, the first substrate is removed to expose the peelable module. 2 . The method for forming a semiconductor structure according to claim 1 , further comprising: after removing the first substrate, removing the strippable module and the strippable film to form a first opening. 3 . 3 . The method of claim 2 , wherein the process of removing the strippable film comprises a wet etching process. 4 . 4 . The method for forming a semiconductor structure according to claim 3 , wherein the method for removing the peelable module comprises: after removing the peelable film, or while removing the peelable film, using several A plurality of suction cups are adsorbed on the surface of the peelable module, and the plurality of suction cups are pulled to remove the peelable module. 5 . The method for forming a semiconductor structure according to claim 2 , wherein the method for removing the peelable module comprises: using several suction cups to adsorb on the surface of the peelable module, and pulling the several suction cup to remove the peelable module. 6 . The method for forming a semiconductor structure according to claim 5 , wherein the method for removing the peelable film comprises: after removing the peelable module, etching the peelable film until the peelable film is removed. 7 . 7. The method for forming a semiconductor structure according to claim 2, further comprising: forming a fifth dielectric layer in the first opening, and a fourth metal interconnection located in the fifth dielectric layer layer, the fourth metal interconnection layer is electrically interconnected with the circuit of the second functional unit, and the fourth metal interconnection layer is exposed on the surface of the fifth dielectric layer. 8 . The method for forming a semiconductor structure according to claim 2 , further comprising: after forming the first opening, providing a third chip; embedding the third chip into the first opening; After the third chip is embedded in the first opening, the third chip is bonded to the second substrate, and the circuit of the third chip is electrically interconnected with the circuit of the second functional unit. 9 . The method for forming a semiconductor structure according to claim 8 , wherein the circuit of the second functional unit comprises a second functional circuit and a second metal interconnection layer, the second functional circuit and the first The two metal interconnect layers are electrically interconnected, and the second substrate surface exposes the surface of the second metal interconnect layer. 10 . The method for forming a semiconductor structure according to claim 9 , wherein the third chip has a third functional circuit and a third metal interconnection layer, and the third functional circuit is connected to the third metal interconnection layer. 11 . The interconnection layer is electrically interconnected, and the third metal interconnection layer is exposed on the surface of the third chip; the method for bonding the third chip and the second substrate includes: removing the peelable module and After the peelable film, the second surface exposes the surface of the second metal interconnection layer; the second metal interconnection layer is bonded to the third metal interconnection layer. 11. The method for forming a semiconductor structure according to claim 9, further comprising: after bonding the third chip and the second substrate, forming a first conductive plug in the third chip plugs, the first conductive plugs are electrically interconnected with a second metal interconnect layer, and the first conductive plugs are electrically interconnected with circuits within the third chip. 12. The method for forming a semiconductor structure according to claim 1, further comprising: after removing the first substrate, forming a second conductive plug penetrating the strippable module and the strippable film, the The second conductive plug is electrically interconnected with the circuit of the peelable module, and the second conductive plug is electrically interconnected with the circuit of the second functional unit. 13. The method of forming a semiconductor structure of claim 1, wherein the method of forming the peelable film and the peelable module comprises: forming an initial peelable module on the first side of the second region; etching the initial strippable module to form the strippable module and a strippable film opening surrounding all sidewalls of the strippable module; forming a strippable film opening within the strippable film opening and on the surface of the strippable module membrane. 14. The method for forming a semiconductor structure according to claim 13, further comprising: forming a first dielectric layer on the first surface of the second region before forming the initial strippable module, wherein The material of the first dielectric layer is the same as the material of the peelable film; the method for forming the peelable module further includes: forming the initial peelable module on the surface of the first dielectric layer. 15 . The method for forming a semiconductor structure according to claim 1 , wherein the method for forming the peelable film comprises: forming on the first surface of the second region before forming the peelable module. 16 . A third medium layer and a peelable groove in the third medium layer; the peelable module is formed in the peelable groove; and a fourth medium layer is formed on the surface of the peelable module. 16 . The method for forming a semiconductor structure according to claim 1 , further comprising: forming a first substrate on the surface of the first functional unit before bonding the first substrate and the second substrate. 17 . adhesive layer. 17. The method for forming a semiconductor structure according to claim 1, further comprising: before bonding the first substrate and the second substrate, on the surface of the first functional unit and the A first adhesive layer is formed on the surface of the peelable film. 18. The method for forming a semiconductor structure according to claim 16 or 17, further comprising: before bonding the first substrate and the second substrate, in the first region of the first region A first metal interconnection layer is formed in an adhesive layer, the surface of the first adhesive layer exposes the surface of the first metal interconnection layer, the first metal interconnection layer and the circuit of the first functional unit electrical interconnection. 19. The method for forming a semiconductor structure according to claim 1, 16 or 17, further comprising: before bonding the first substrate and the second substrate, before bonding the first substrate and the second substrate A second adhesive layer is formed on the second chip area where the area overlaps. 20. The method of claim 1, wherein the process of removing the first substrate comprises a thinning process. 21. The method for forming a semiconductor structure according to claim 20, wherein the thinning process comprises one or a combination of an etch-back process or a chemical mechanical polishing process. 22. The method for forming a semiconductor structure according to claim 1, wherein the material of the strippable film comprises one of an anti-reflection material or a photoresist. 23. The method for forming a semiconductor structure according to claim 1, wherein the circuit of the first functional unit comprises a logic control circuit or a memory circuit. 24. The method for forming a semiconductor structure according to claim 1, wherein the circuit of the second functional unit comprises a logic control circuit or a memory circuit. 25 . The method for forming a semiconductor structure according to claim 1 , wherein the peelable module has one or a combination of one or more of a logic control circuit, a memory circuit, a dummy gate structure, and a micro-electromechanical system. 26 . 26 . The method for forming a semiconductor structure according to claim 8 , wherein the third chip has one or a combination of one or more of a logic control circuit, a memory circuit, and a micro-motor system. 27 . 27. A semiconductor structure formed by the forming method according to any one of claims 1 to 26, characterized in that, comprising: a second substrate, the second substrate includes a second chip area, and the second chip area has a second functional unit; a first functional unit located on the second chip area, the first functional unit is bonded to the second substrate, and the circuit of the first functional unit is electrically interconnected with the circuit of the second functional unit; a peelable module on the second chip area; A peelable film on the side of the peelable module and the surface facing the second substrate surface and surrounding the peelable module.

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