CN111430328B

CN111430328B - Capacitive semiconductor element

Info

Publication number: CN111430328B
Application number: CN201910340165.6A
Authority: CN
Inventors: 川村昌靖; 夏目秀隆; 藤井康博; 熊谷裕弘
Original assignee: Nexchip Semiconductor Corp
Current assignee: Nexchip Semiconductor Corp
Priority date: 2019-04-25
Filing date: 2019-04-25
Publication date: 2021-07-27
Anticipated expiration: 2039-04-25
Also published as: CN111430328A

Abstract

An object of the present invention is to provide a capacitive semiconductor element that can be designed more accurately in consideration of parasitic capacitance components. The capacitive semiconductor element includes: a MOM capacitor including a plurality of finger wirings coupled to each other to form inter-wiring capacitances, and a common wiring connecting predetermined finger wirings to each other; a gate electrode (DG), which is located on the stack On a silicon substrate with a metal layer, when viewed from the stacking direction, at least a part of the pattern overlaps with the pattern of the finger wiring, and has a first pattern that is the same as or similar to the pattern of the finger wiring; and a silicon area (DA) , located on the silicon substrate, at least a part of which overlaps with the pattern of the finger wiring when viewed from the stacking direction, and has a second pattern that is the same as or similar to the pattern of the finger wiring.

Description

Capacitive semiconductor element

Technical Field

The present invention relates to a capacitive semiconductor element.

Background

In the field of integrated circuits, a Metal-Oxide-Metal (hereinafter referred to as "MOM") capacitor using an inter-wiring capacitor is used. MOM has advantages such as higher capacitance density compared to Metal-Insulator-Metal (MIM) capacitors, for example. However, according to the structure of the conventional MOM, there is a possibility that the parasitic capacitances generated by the two electrodes are unbalanced.

The MOM structure in the prior art includes: two electrode wirings are arranged in a comb-tooth shape to form a capacitance between the wirings, a separation oxide film is arranged right under one electrode wiring, and an active region is arranged right under the other electrode wiring.

In addition, when designing MOM, it is desirable to be able to simulate the manufacturing parasitic capacitance more accurately, ensuring linearity of the MOM capacitance value.

Disclosure of Invention

The present invention has been made in view of the above circumstances, and an object thereof is to provide a capacitive semiconductor element which can be designed more precisely in consideration of a parasitic capacitance component.

A first aspect of the present invention provides a capacitive semiconductor element including: a metal-oxide-metal capacitor (MOM capacitor) including a plurality of finger-shaped wirings coupled to each other to form inter-wiring capacitances, and a common wiring connecting prescribed ones of the finger-shaped wirings to each other, wherein the metal-oxide-metal capacitor is formed of stacked metal layers; a gate electrode on the silicon substrate on which the metal layer is laminated, at least a part of which overlaps with the pattern of the finger-like wiring when viewed from the metal layer lamination direction, and which has a first pattern identical or similar to the pattern of the finger-like wiring; and a silicon region on the silicon substrate, at least a portion of which overlaps with the pattern of the finger wiring when viewed from the metal layer stacking direction, and which has a second pattern identical or similar to the pattern of the finger wiring.

According to the structure described above, it is designed as a structure as follows: the gate electrode is on the silicon substrate corresponding to the finger wiring constituting the MOM, at least a portion of which overlaps with the pattern of the finger wiring when viewed from the metal layer stacking direction, and has a first pattern identical or similar to the pattern of the finger wiring. Further, as the structure, the following is designed: the silicon region is on the silicon substrate corresponding to the finger wirings constituting the MOM, at least a portion of which overlaps with the pattern of the finger wirings when viewed from the metal layer stacking direction, and has a second pattern identical or similar to the pattern of the finger wirings. That is, the parasitic capacitance between the finger-shaped wiring and the gate electrode and the silicon region can be made uniform for each finger-shaped wiring. This reduces the imbalance of the parasitic capacitance between the electrodes of the MOM. In addition, since the parasitic capacitances of the respective finger-shaped wirings are unified, the parasitic capacitances after the manufacture can be easily estimated at the time of designing the MOM, and the linearity of the MOM capacitance value including the parasitic capacitance component can also be improved. Therefore, the parasitic capacitance component can be taken into consideration so that more accurate design can be performed.

In the above capacitive semiconductor element, when viewed from the stacking direction, a central axis in the longitudinal direction of the finger line, a central axis in the longitudinal direction of the first pattern, and a central axis in the longitudinal direction of the second pattern may be aligned.

According to the above configuration, since the center axis in the finger line longitudinal direction, the center axis in the first pattern longitudinal direction, and the center axis in the second pattern longitudinal direction coincide with each other when viewed from the lamination direction, the parasitic capacitance of each finger line can be more accurately uniformized. That is, the parasitic capacitance component can be considered to enable more accurate design.

In the above capacitive semiconductor element, the gate electrode may be formed on the silicon substrate so as to overlap at least a part thereof with the pattern of the common wiring when viewed from the stacking direction and have a third pattern identical or similar to the pattern of the common wiring, and the silicon region may be formed on the silicon substrate so as to overlap at least a part thereof with the pattern of the common wiring when viewed from the stacking direction and have a fourth pattern identical or similar to the pattern of the common wiring.

According to the structure described above, it is designed as a structure as follows: the gate electrode is on the silicon substrate corresponding to the common wiring constituting the MOM, at least a portion of which overlaps with the pattern of the common wiring when viewed from the stacking direction, and has a third pattern identical or similar to the pattern of the common wiring. Further, as the structure, the following is designed: the silicon region is on the silicon substrate, at least a portion of which overlaps with a pattern of the common wiring when viewed from the stacking direction, and has a fourth pattern that is the same as or similar to the pattern of the common wiring, corresponding to the common wiring constituting the MOM. That is, the parasitic capacitance between the common wiring and the gate electrode and the silicon region can be made uniform. Therefore, the parasitic capacitance component can be taken into consideration so that more accurate design can be performed.

In the above capacitive semiconductor element, a central axis in the longitudinal direction of the common line, a central axis in the longitudinal direction of the third pattern, and a central axis in the longitudinal direction of the fourth pattern may be aligned when viewed from the stacking direction.

According to the above configuration, since the central axis in the common wiring longitudinal direction, the central axis in the third pattern longitudinal direction, and the central axis in the fourth pattern longitudinal direction coincide with each other when viewed from the stacking direction, it is possible to design more accurately in consideration of the parasitic capacitance component.

In the above capacitive semiconductor element, the silicon region may be a conductive region.

According to the above configuration, although the silicon region is a conductive region and thus generates a parasitic capacitance with respect to the finger lines, the silicon region is provided so as to correspond to the finger lines, and thus the parasitic capacitances of the finger lines can be made uniform.

In the above capacitive semiconductor element, the silicon region may include a diffusion layer.

According to the above configuration, although the silicon region includes the diffusion layer, parasitic capacitance occurs in the finger lines, the silicon region is provided in correspondence with the finger lines, and therefore the parasitic capacitance of the finger lines can be made uniform.

In the capacitive semiconductor device, a shallow trench isolation STI may be formed in a region between the silicon regions.

According to the structure as described above, parasitic capacitance between the region including the STI and the finger wiring can be reduced.

According to the present invention, the parasitic capacitance component can be taken into consideration, thereby enabling more accurate design.

Drawings

Fig. 1 is a cross-sectional view of a capacitive semiconductor element according to an embodiment of the present invention.

Fig. 2 is a diagram of a wiring pattern of the MOM according to the embodiment of the present invention.

Fig. 3 is a cross-sectional view of a capacitive semiconductor element according to an embodiment of the present invention.

Fig. 4 is a diagram of an equivalent circuit of a capacitive semiconductor element according to an embodiment of the present invention.

Fig. 5 is a plan view of a pattern of a gate electrode of the MOM according to the embodiment of the present invention.

Fig. 6 is a plan view of a pattern of a silicon region of an MOM according to an embodiment of the present invention.

Fig. 7 is a diagram illustrating an STI trench forming process of the capacitive semiconductor device according to the embodiment of the present invention.

Fig. 8 is a diagram illustrating an STI trench burying step of the capacitive semiconductor device according to the embodiment of the present invention.

Fig. 9 is a diagram showing an STI-CMP planarization process of the capacitive semiconductor device according to the embodiment of the present invention.

Fig. 10 is a diagram illustrating a WELL formation step of a capacitive semiconductor element according to an embodiment of the present invention.

Fig. 11 is a diagram illustrating a gate pattern forming process of a capacitive semiconductor element according to an embodiment of the present invention.

Fig. 12 is a diagram illustrating an ion implantation process of the capacitive semiconductor element according to the embodiment of the present invention.

Fig. 13 is a diagram illustrating an insulating film forming process of a capacitive semiconductor element according to an embodiment of the present invention.

Fig. 14 is a diagram showing a CMP planarization process for a capacitive semiconductor element according to an embodiment of the present invention.

Fig. 15 is a diagram illustrating a contact portion forming step of a capacitive semiconductor element according to an embodiment of the present invention.

Fig. 16 is a diagram illustrating a 1 st metal forming step of a capacitive semiconductor element according to an embodiment of the present invention.

Fig. 17 is a diagram illustrating a 2 nd metal forming step of a capacitive semiconductor element according to an embodiment of the present invention.

Fig. 18 is a plan view of a pattern of a gate electrode and a silicon region of a capacitive semiconductor element according to an embodiment of the present invention.

Description of the reference numerals

1 capacitive semiconductor element

A. B electrode

CL common wiring

Cap MOM formation region

Parasitic capacitance of Cep

DA silicon region

DG gate electrode

FL finger wiring

G grid

IF silicon oxide film

LA wiring area

LP photoresist layer pattern

P1 first Pattern

P2 second Pattern

P3 third Pattern

P4 fourth Pattern

Sub silicon substrate

Tr transistor formation region

Detailed Description

Hereinafter, an embodiment of a capacitive semiconductor element according to the present invention will be described with reference to the drawings.

Fig. 1 is a cross-sectional view of a capacitive semiconductor element 1 according to an embodiment of the present invention. As shown in fig. 1, the capacitive semiconductor element 1 according to the present embodiment includes a wiring area LA and a silicon substrate Sub on which the wiring area LA is stacked.

An MOM capacitor having a metal layer formed in a wiring area LA, the MOM capacitor including: a plurality of finger-shaped wirings (metal wirings) FL coupled to each other to form inter-wiring capacitance, and a common wiring (metal wiring) CL connecting predetermined finger-shaped wirings FL to each other, wherein the metal-oxide-metal capacitor is formed by laminated metal layers. Specifically, in the wiring area LA, a plane (layer) parallel to the surface of the silicon substrate Sub is formed at a position spaced apart from the surface of the silicon substrate Sub by a predetermined distance. That is, in the wiring area LA, a plurality of planes (layers) are provided along the stacking direction with respect to the surface of the silicon substrate Sub. The stacking direction is a direction in which the layers of the wiring region LA are stacked with respect to the silicon substrate Sub, and is also a direction (perpendicular direction) perpendicular to the surface of the silicon substrate Sub.

As shown in fig. 1, the planar layers are an M1 layer (metal layer) and an M2 layer (metal layer) in order from the near side to the far side from the surface of the silicon substrate Sub, a CT (contact) layer is provided between the surface of the silicon substrate Sub and the M1 layer, and a V (via) layer is provided between the M1 layer and the M2 layer. The number of metal layers is not limited to the above.

As shown in fig. 1, the M1 layer and the M2 layer may be metal layers, and may be layers in which metal wirings can be formed using metal such as copper (Cu) or aluminum (Al), or polysilicon. Further, an insulator may be embedded between the wirings. Examples of the insulator include TEOS (Tetra ethyl Ortho Silicate), BPTEOS (boro phosphorus Ortho Silicate), FSG (F-doped Silicate Glass), and a silicon oxide film or a silicon nitride film obtained by doping phosphorus or Boron at a specific concentration.

As shown in fig. 1, metal wirings for constituting MOM (MOM capacitor) are formed on the M1 layer and the M2 layer. In the present embodiment, a case where wirings having the same pattern are laid on the M1 layer and the M2 layer will be described as an example. The same applies to the case where the wiring of the M1 layer is different from the wiring of the M2 layer, for example, the finger wirings FL corresponding to the respective electrodes are alternately laid.

As shown in fig. 2, a wiring pattern constituting the MOM was formed on the M1 layer. The wirings constituting the MOM include finger wirings FL and common wirings CL. The finger lines FL may be lines coupled to each other to form inter-line capacitance. The common line CL is a line connecting the predetermined finger lines FL to each other. In the case of configuring the MOM, a plurality of finger lines FL arranged in parallel at equal intervals are alternately connected to the common line CL, and the finger line FL connected to the common line CL (electrode a side) and the finger line FL connected to the common line CL (electrode B side) are capacitively coupled to each other. That is, an inter-wiring capacitance is formed between the electrode a side and the electrode B side, thereby forming a capacitor element of an MOM structure.

Since MOM is obtained by using capacitive coupling between wirings, the capacitance value can be adjusted using the length Lf of the finger wirings FL, the distance Sf between the finger wirings FL, and the number Nf of the finger wirings FL as parameters. For example, the longer the length Lf of the finger wiring FL, the larger the area for performing capacitive coupling and the larger the capacitance. The shorter the distance Sf between the finger wirings FL, the stronger the capacitive coupling and the larger the capacitance. The larger the number Nf of finger lines FL, the larger the area for capacitive coupling and the larger the capacitance.

Further, the same wiring as the metal pattern of the M1 layer was formed on the M2 layer. The same pattern means that the metal pattern of the M1 layer coincides with (or substantially coincides with) the metal pattern of the M2 layer when viewed from the stacking direction.

The V layer is a layer that connects metal wirings of metal layers on both sides adjacent to each other in the stacking direction. The wiring of the M1 layer and the metal wiring of the M2 layer are connected to each other through a via hole of the V layer disposed in the middle. That is, the wirings of the metal layers are connected to constitute the electrode a and the electrode B.

The CT layer is a contact layer that connects the surface of the silicon substrate Sub adjacent in the stacking direction and the metal wiring of the metal layer to each other.

Dummy devices (dummy) such as gate electrodes DG corresponding to the wiring pattern of the MOM are disposed on the surface of the silicon substrate Sub. Although a MOS transistor or the like is formed on the surface of the silicon substrate Sub, if a transistor for operation is disposed directly below the MOM, the capacitance of the MOM may change. Therefore, the transistor is not arranged directly below the MOM, which requires accuracy for the capacitance value. In addition, if a capacitive element such as a decoupling capacitor, which does not require accuracy in capacitance value, is used, a transistor which operates can be formed immediately below the capacitive element. However, when a transistor or the like is formed in a region other than the region directly below the MOM, wiring (flat wiring) is more accurately performed on the M1 layer or the like in order to form the CT layer flat, and dummy devices such as gate electrodes DG may be arranged so as to satisfy a predetermined density in the region directly below the MOM. The accuracy of the MOM capacitance value can be improved by ensuring the flatness of the wiring layer of the MOM.

However, there is a possibility that: depending on the positional relationship between the dummy devices disposed on the silicon substrate Sub directly below the MOM and the finger lines FL, etc., the parasitic capacitances of the respective electrodes of the MOM are unbalanced, or the parasitic capacitances of the respective finger lines FL are different from each other. For example, as a reference example, as shown in fig. 3, in the case where a dummy gate electrode DGe and a silicon region DAe are formed on a substrate with respect to a wiring of an MOM, parasitic capacitances Cep of a wiring L1 corresponding to an electrode E1 and a wiring L2 corresponding to an electrode E2 are different from each other. Specifically, since the distance between the line L1 and the gate electrode DGe is shorter than the distance between the line L2 and the gate electrode DGe, the parasitic capacitance Cep between the line L1 and the gate electrode DGe increases. Fig. 4 is a diagram showing an equivalent circuit of the MOM of the reference example of fig. 3. As shown in fig. 4, in the structure of the reference example of fig. 3, a parasitic capacitance Cep1 and a parasitic capacitance Cep2 are generated between the capacitance Ce and the dummy device, and the parasitic capacitances are unbalanced (Cep1 ≠ Cep2), and the capacitance Ce is generated by the inter-wire capacitive coupling of the wiring between the electrode E1 and the electrode E2. The parasitic capacitance of each finger FL is different from each other. Therefore, even if the parasitic capacitance with respect to the specific electrode can be designed to be small, imbalance occurs, and it is difficult to design the MOM more accurately in consideration of the parasitic capacitance component.

Therefore, in the structure of the capacitive semiconductor element 1 according to the present embodiment, a dummy gate electrode DG and the like are designed on the silicon substrate Sub in correspondence with the wiring constituting the MOM. Specifically, as shown in fig. 1, a gate electrode (dummy gate) DG and a silicon region (dummy active region) DA are formed on a silicon substrate Sub. By configuring the dummy gate electrode DG and the like corresponding to the lines of the MOM, the parasitic capacitance values generated in the lines can be made uniform as shown by the parasitic capacitance Cp in fig. 1.

The gate electrode DG is a dummy pattern disposed just below the MOM for planarizing the CT layer, and is provided with an insulator made of a silicon oxide film and a gate electrode DG made of a metal or polysilicon on the silicon substrate Sub, as in the MOS transistor.

The gate electrode DG is located on the silicon substrate Sub on which the metal layer is laminated, at least a portion of which overlaps the pattern of the finger wiring FL when viewed from the metal layer lamination direction, and has a first pattern P1 identical or similar to the pattern of the finger wiring FL. Specifically, when viewed from the stacking direction, the center axis of the finger wiring FL in the longitudinal direction and the center axis of the first pattern P1 in the longitudinal direction are aligned. In particular, the first pattern P1 is preferably a pattern of the finger wiring FL closest to the metal layer (M1 layer) on the silicon substrate Sub.

Note that the gate electrode DG may be formed so that the parasitic capacitances generated in the finger lines FL are equal to each other, and the center axes in the longitudinal direction of the finger lines FL and the center axes in the longitudinal direction of the first pattern P1 may be offset when viewed from the stacking direction. In the present embodiment, a case where the center axis in the longitudinal direction of the finger wiring FL and the center axis in the longitudinal direction of the first pattern P1 are aligned when viewed from the lamination direction, and the first pattern P1 is similar to the pattern of the finger wiring FL will be described as an example. The same applies to the case where the first pattern P1 is the same as the pattern of the finger wiring FL.

Further, the gate electrode DG is on the silicon substrate Sub, at least a part of which overlaps with the pattern of the common wiring CL when viewed from the metal layer stacking direction, and has a third pattern P3 that is the same as or similar to the pattern of the common wiring CL. Specifically, when viewed from the stacking direction, the center axis of the common line CL in the longitudinal direction and the center axis of the third pattern P3 in the longitudinal direction are aligned. In particular, the third pattern P3 may be corresponding to the shared wiring CL of the metal layer (M1 layer) closest to the silicon substrate Sub.

Note that the gate electrode DG may be formed so that the parasitic capacitances generated in the common lines CL are equal to each other, and the central axis of the common line CL in the longitudinal direction and the central axis of the third pattern P3 in the longitudinal direction may be offset when viewed from the stacking direction. In the present embodiment, the description will be given of a case where the common wiring CL is arranged so that the longitudinal central axis thereof coincides with the longitudinal central axis of the third pattern P3 when viewed from the stacking direction, and the third pattern P3 is similar to the pattern of the common wiring CL. The same applies to the case where the third pattern P3 matches the pattern of the common wiring CL.

Fig. 5 shows a plan view of a wiring pattern of the gate electrode DG formed on the silicon substrate Sub (a view obtained by viewing from the stacking direction, i.e., a first pattern P1 and a third pattern P3). Fig. 5 shows a wiring pattern of the M1 layer (finger wiring FL (M1) and common wiring CL (M1)) in an overlapping manner. In the present embodiment, a case is shown where the similarity ratio of the first pattern P1 with respect to the finger wiring FL is larger than 1, and the similarity ratio of the third pattern P3 with respect to the common wiring CL is larger than 1. In this way, since the dummy gate electrodes DG are formed equally to the respective finger lines FL, the parasitic capacitances to the respective finger lines FL can be made equal. In addition, the parasitic capacitances generated in the common lines CL can be equalized.

Even when the first pattern P1 is the same as the finger lines FL or is similar to the finger lines FL and has a similarity ratio smaller than 1, the dummy gate electrodes DG are equally formed with respect to the finger lines FL, so that the parasitic capacitances can be equally equalized. Note that the same may be true for the third pattern P3 in the same case as the common wiring CL or in a similar case where the similarity ratio is smaller than 1. Further, the first pattern P1 and the third pattern P3 can be independently designed.

The silicon region DA is a conductive region (active region) and is, for example, a diffusion layer. STI (Shallow Trench Isolation) formed of a silicon oxide film is formed in a region sandwiched between the silicon regions DA. In other words, STI is generated on the portion of the non-silicon region DA on the silicon substrate Sub.

The silicon region DA is located on the silicon substrate Sub where the metal layers are laminated, at least a part of which overlaps with the pattern of the finger wirings FL when viewed from the metal layer lamination direction, and has a second pattern P2 identical or similar to the pattern of the finger wirings FL. Specifically, when viewed from the stacking direction, the center axis of the finger wiring FL in the longitudinal direction and the center axis of the second pattern P2 in the longitudinal direction are aligned. In particular, the second pattern P2 is preferably a pattern of the finger wiring FL of the metal layer (M1 layer) closest to the silicon substrate Sub.

In addition, if the silicon region DA is formed so that the parasitic capacitances generated in the finger lines FL are equal to each other, the center axes in the longitudinal direction of the finger lines FL and the center axes in the longitudinal direction of the second pattern P2 may be offset when viewed from the stacking direction. In the present embodiment, a case where the center axis in the longitudinal direction of the finger wiring FL and the center axis in the longitudinal direction of the second pattern P2 are aligned when viewed from the lamination direction, and the second pattern P2 is similar to the pattern of the finger wiring FL will be described as an example. The same applies to the case where the second pattern P2 is the same as the pattern of the finger wiring FL.

Further, the silicon region DA is provided on the silicon substrate Sub, at least a part of which overlaps with the pattern of the common wiring CL when viewed from the metal layer stacking direction, and has a fourth pattern P4 that is the same as or similar to the pattern of the common wiring CL. Specifically, when viewed from the stacking direction, the center axis of the common line CL in the longitudinal direction and the center axis of the fourth pattern P4 in the longitudinal direction are aligned. In particular, the fourth pattern P4 is preferably a pattern of the common wiring CL of the metal layer (M1 layer) closest to the silicon substrate Sub.

In addition, if the silicon region DA is formed so that the parasitic capacitances are equal to each other in the common lines CL, the center axis of the common line CL in the longitudinal direction and the center axis of the fourth pattern P4 in the longitudinal direction may be offset when viewed from the stacking direction. In the present embodiment, the description will be given of a case where the central axis in the longitudinal direction of the common wiring CL and the central axis in the longitudinal direction of the fourth pattern P4 are arranged so as to coincide with each other when viewed from the stacking direction, and the fourth pattern P4 is similar to the pattern of the common wiring CL. The same applies to the case where the fourth pattern P4 is the same as the pattern of the common wiring CL.

Fig. 6 shows an example of a plan view (a view obtained when viewed from the stacking direction, that is, the second pattern P2 and the fourth pattern P4) of the wiring pattern of the silicon region DA generated on the surface of the silicon substrate Sub. Fig. 6 shows the wiring patterns of the M1 layer (finger wiring FL (M1) and common wiring CL (M1)) superimposed on each other. In the present embodiment, a case is shown where the similarity ratio of the second pattern P2 with respect to the finger wiring FL is larger than 1 and the similarity ratio of the fourth pattern P4 with respect to the common wiring CL is larger than 1. In this way, since the dummy gate electrodes DG are formed equally to the respective finger lines FL, the parasitic capacitances to the respective finger lines FL can be made equal. In addition, the parasitic capacitances generated in the common lines CL can be equalized.

Further, even in the case where the second pattern P2 is the same as the finger wirings FL or is similar and the similarity ratio is less than 1, since the dummy gate electrodes DG are equally configured with respect to the respective finger wirings FL, the parasitic capacitances can be equally equalized. Note that the same case or a similar case where the similarity ratio is less than 1 may be applied to the fourth pattern P4. Further, the second pattern P2 and the fourth pattern P4 can be independently designed.

That is, the first pattern P1 of the gate electrode DG, the third pattern P3 of the gate electrode DG, the second pattern P2 of the silicon region DA, and the fourth pattern P4 of the silicon region DA can be independently designed in the same or similar shape, respectively.

Next, an example of a method (process flow) for manufacturing the capacitive semiconductor element 1 according to the present embodiment will be described with reference to fig. 7 to 17.

Fig. 7 to 17 are diagrams illustrating respective manufacturing steps of the capacitive semiconductor element 1. In each drawing, a case where MOM (MOM formation region Cap) is formed on the left side and a transistor (transistor formation region Tr) is formed on the right side is shown. Fig. 7 is a diagram showing an STI trench forming process. Fig. 8 is a diagram illustrating an STI trench burying step. FIG. 9 is a view showing an STI-CMP planarization step. Fig. 10 shows a WELL forming process. Fig. 11 is a diagram showing a gate pattern forming step. Fig. 12 is a view showing an ion implantation step. Fig. 13 is a diagram showing an insulating film forming step. Fig. 14 is a diagram showing a CMP planarization step. Fig. 15 is a view showing a contact portion forming step. Fig. 16 is a view showing a 1 st metal forming step. Fig. 17 is a view showing a 2 nd metal forming step.

First, as shown in fig. 7, an STI trench formation process is performed. In the STI Trench forming step, a photoresist layer pattern LP is formed on a portion of the silicon substrate Sub where STI is not formed, and etching is performed, thereby forming a Trench (Trench) in the portion where the photoresist layer pattern LP is not formed. When the trench formation is completed, the photoresist layer pattern LP is removed. Further, the ratio of STI to the active region (region where STI is not formed) is set so that the flatness of the silicon substrate Sub is not deteriorated. Further, since the trench STI is formed, the trench is formed to have the second pattern P2 and the fourth pattern P4.

In the STI trench burying process of fig. 8, a silicon oxide film is formed and the formed trench is buried. The silicon oxide film formed on the trench becomes STI. In the STI trench embedding step, a CVD method or the like can be used.

In the STI-CMP planarization step of fig. 9, the surface of the silicon substrate Sub is polished to leave only the silicon oxide film in the trench, and the other silicon oxide film is removed.

In the WELL formation process of fig. 10, the silicon substrate Sub is doped to form a WELL. The P-well is formed, for example, by doping with impurities such as boron. Further, the N well is formed by doping with an impurity such as phosphorus. The case where the silicon substrate Sub forming the MOM is doped with phosphorus to form an N well is shown in fig. 10.

In the gate pattern forming step of fig. 11, a gate electrode DG is formed on the surface of the silicon substrate Sub. The gate electrode DG is a dummy gate electrode DG in the MOM formation region Cap, and is a gate electrode G used for transistor control in the transistor formation region Tr. The gate electrode DG includes a laminated insulator (silicon oxide film) and a laminated electrode (metal or polysilicon) on the silicon substrate Sub. In the MOM formation region Cap, the gate electrode DG is formed to have the first pattern P1 and the third pattern P3.

Further, an epitaxy (low-concentration doped drain) is formed in the transistor formation region Tr, for example. In FIG. 11, an impurity (n-LDD) such as phosphorus is implanted into D1, and an impurity (p-LDD) such as boron is implanted into D2.

In the ion implantation step of fig. 12, ion doping is performed to form source/drain electrodes. Specifically, the n-source/drain is doped with an impurity such as phosphorus, and the p-source/drain is doped with an impurity such as boron.

In the insulating film formation step of fig. 13, a thick silicon oxide film IF is formed on the silicon substrate Sub by a CVD method or the like. Since the silicon substrate Sub has a minute uneven structure due to the gate electrode DG, the surface of the silicon oxide film IF is not flat as shown in fig. 13.

In the CMP planarization step of fig. 14, the surface of the formed silicon oxide film is polished and planarized. I.e. a flat CT layer is formed. Further, if the dummy gate electrodes DG or the silicon regions (active regions) DA are not formed at an appropriate density, the dummy gate electrodes DG or the silicon regions (active regions) DA adversely affect the planarization in the CMP planarization step, and the finger lines FL of the same layer formed in the subsequent step cannot be planarized, which also affects the accuracy of the MOM. In the present embodiment, since the dummy device is also provided in the MOM formation region Cap, a flat CT layer can be formed.

In the contact portion forming step of fig. 15, a contact portion is formed at a predetermined position of the CT layer. The contact portion is formed by forming a contact hole in an insulating film and burying tungsten or the like. The contact portion is formed, for example, to electrically connect the gate electrode, the source electrode, and the drain electrode of the transistor to the outside.

In the first metal forming step of fig. 16, metal wirings of M1 layer are formed. In the M1 layer, finger-like wirings FL and common wirings CL are formed in the MOM formation region Cap in the pattern shown in fig. 2. In the transistor region, a wiring line having a previously designed pattern is also formed in the M1 layer. An insulating film is formed in a region other than the wiring of the M1 layer. In addition, the upper surface of the M1 layer is planarized by an (insulating film) film for forming the subsequent wiring.

In the second metal forming step of fig. 17, a wiring of M2 layer is formed. In the M2 layer, finger-like wirings FL and common wirings CL are formed in the MOM formation region Cap in the same pattern as shown in fig. 2. In the transistor region, a wiring line having a previously designed pattern is also formed in the M2 layer. An insulating film is formed in a region other than the wiring of the M2 layer. In addition, the upper surface of the M2 layer is planarized by an (insulating film) film for forming the subsequent wiring.

In the V layer between the M1 layer and the M2 layer, a through hole is provided to connect the wiring defined by the M1 layer and the wiring defined by the M2 layer. In the MOM formation region Cap, the finger lines FL and the common lines CL of the metal layers constituting the electrode a are connected to each other through via holes, and the finger lines FL and the common lines CL of the metal layers constituting the electrode B are connected to each other through via holes. Thus, the wiring of the MOM of the M1 layer and the wiring of the MOM of the M2 layer are connected for each electrode, and the MOM is configured. The MOM is configured by coupling the wirings of the plurality of metal layers, and thus a MOM having a large capacitance value can be configured.

Thus, the capacitive semiconductor element 1 is manufactured. The above-described steps are merely exemplary, and are not limited to the case of manufacturing through the steps.

The pattern of the finger lines FL and the common lines CL, the pattern of the dummy gate electrodes DG, and the pattern of the dummy silicon regions DA in the present embodiment are designed in advance in shape and arrangement position. Therefore, by performing the manufacturing in each step, the pattern of the finger lines FL and the common lines CL, the pattern of the dummy gate electrodes DG, and the pattern of the dummy silicon regions DA are formed so as to correspond to each other as shown in fig. 1. Therefore, since the parasitic capacitance can be equally configured for each finger wiring FL (particularly, the finger wiring FL of the metal layer (M1 layer) closest to the silicon substrate Sub), the accuracy of the MOM design can be improved, and the reproducibility of the design can be further improved.

In the MOM, the capacitive coupling is mainly provided by the finger wiring FL, and the finger wiring FL occupies a larger area. Therefore, the dummy gate electrode DG or the silicon region DA may be provided so as to correspond to at least the finger wiring FL. That is, at least the gate electrode DG has the first pattern P1 and the silicon area DA has the second pattern P2.

Fig. 18 is a diagram illustrating an example in which dummy gate electrodes DG are provided only with respect to finger lines FL. As shown in fig. 18, the gate electrode DG has a first pattern P1 corresponding to the finger wiring FL. In the same manner as in fig. 18, dummy silicon regions DA may be provided only for the finger lines FL. In this case, the silicon region DA has the second pattern P2 corresponding to the finger wiring FL.

As described above, the capacitive semiconductor element according to the present embodiment is designed as follows: the gate electrode DG overlaps, on the silicon substrate Sub, at least a part thereof with the pattern of the finger wiring FL when viewed from the stacking direction, corresponding to the finger wiring FL constituting the MOM, and has a first pattern P1 identical or similar to the pattern of the finger wiring FL. Further, as the structure, the following is designed: the silicon region DA overlaps at least a part of the pattern of the finger wirings FL on the silicon substrate Sub when viewed from the lamination direction, corresponding to the finger wirings FL constituting the MOM, and has a second pattern P2 identical or similar to the pattern of the finger wirings FL. That is, the parasitic capacitance between the finger wiring FL, the gate electrode DG, and the silicon region DA can be made uniform for each finger wiring FL. This reduces the imbalance of the parasitic capacitance between the MOM electrodes. Further, since the parasitic capacitance of each finger wiring FL is unified, the parasitic capacitance after manufacturing can be easily estimated at the time of designing the MOM, and the linearity of the MOM capacitance value including the parasitic capacitance component can also be improved. Therefore, the parasitic capacitance component can be taken into consideration so that more accurate design can be performed.

Further, when viewed from the stacking direction, the center axis of the finger lines FL in the longitudinal direction, the center axis of the first pattern P1 in the longitudinal direction, and the center axis of the second pattern P2 in the longitudinal direction coincide with each other, and therefore, the parasitic capacitance of each finger line FL can be more accurately uniformized. That is, the parasitic capacitance component can be considered to enable more accurate design.

Further, as the structure, the following is designed: the gate electrode DG overlaps at least a part of the pattern of the common wiring CL on the silicon substrate Sub when viewed from the stacking direction, corresponding to the common wiring CL constituting the MOM, and has a third pattern P3 identical or similar to the pattern of the common wiring CL. Further, as the structure, the following is designed: the silicon region DA overlaps at least a part of the pattern of the common wiring CL on the silicon substrate Sub when viewed from the lamination direction, corresponding to the common wiring CL constituting the MOM, and has a fourth pattern P4 identical or similar to the pattern of the common wiring CL. That is, the parasitic capacitance between the common line CL and the gate electrode DG and the silicon region DA can be made uniform. Thereby, the parasitic capacitance component can be taken into consideration so that more accurate design can be performed.

Further, when viewed from the stacking direction, the center axis of the finger wiring FL in the longitudinal direction, the center axis of the third pattern P3 in the longitudinal direction, and the center axis of the third pattern P3 in the longitudinal direction coincide with each other, and therefore, it is possible to design more accurately in consideration of the parasitic capacitance component.

The present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention.

Claims

1. A capacitive semiconductor element, comprising:

a metal-oxide-metal capacitor including a plurality of finger-shaped wirings coupled to each other to form inter-wiring capacitances, and a common wiring connecting prescribed ones of the finger-shaped wirings to each other, wherein the metal-oxide-metal capacitor is formed of laminated metal layers;

a gate electrode on the silicon substrate on which the metal layer is laminated, at least a part of which overlaps with the pattern of the finger-like wiring when viewed from the metal layer lamination direction, and which has a first pattern identical or similar to the pattern of the finger-like wiring; and

and a silicon region on the silicon substrate, at least a portion of which overlaps with the pattern of the finger wiring when viewed from the metal layer stacking direction, and which has a second pattern identical or similar to the pattern of the finger wiring.

2. The capacitive semiconductor element according to claim 1, characterized in that:

when viewed from the stacking direction, a central axis in the longitudinal direction of the finger-like wiring, a central axis in the longitudinal direction of the first pattern, and a central axis in the longitudinal direction of the second pattern are aligned.

3. The capacitive semiconductor element according to claim 1 or 2, characterized in that:

the gate electrode is on the silicon substrate, at least a part of which overlaps with the pattern of the common wiring when viewed from the metal layer stacking direction, and has a third pattern that is the same as or similar to the pattern of the common wiring;

the silicon region is on the silicon substrate, at least a part of which overlaps with the pattern of the common wiring when viewed from the metal layer stacking direction, and has a fourth pattern that is the same as or similar to the pattern of the common wiring.

4. The capacitive semiconductor element according to claim 3, characterized in that:

a central axis in the longitudinal direction of the common wiring, a central axis in the longitudinal direction of the third pattern, and a central axis in the longitudinal direction of the fourth pattern are aligned when viewed from the stacking direction.

5. The capacitive semiconductor element according to claim 1, characterized in that:

the silicon region is a conductive region.

6. The capacitive semiconductor element according to claim 5, characterized in that:

the silicon region includes a diffusion layer.

7. The capacitive semiconductor element according to claim 5, characterized in that:

and forming shallow trench isolation in the region sandwiched by the silicon regions.