CN111430452B - Cell structure of multi-time programmable memory and manufacturing method thereof - Google Patents
Cell structure of multi-time programmable memory and manufacturing method thereof Download PDFInfo
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/68—Floating-gate IGFETs
- H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/512—Disposition of the gate electrodes, e.g. buried gates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
本发明提供一种多次可编程存储器的单元结构及其制作方法，包括衬底，位于衬底上的浮栅，位于浮栅侧壁的第一侧墙及依次位于浮栅上的SAB薄膜和控制栅，且控制栅和SAB薄膜沿垂直于浮栅厚度方向延伸覆盖部分所述第一侧墙。本发明提供的多次可编程存储器的单元结构中所述控制栅通过耦合控制浮栅进行数据的存储与擦除，无需额外的隧穿区域(Tunneling area)，使多次可编程存储器的单元结构的尺寸减小，满足MTP器件的小尺寸化需求。进一步的，所述SAB薄膜和所述控制栅沿垂直于浮栅厚度方向延伸覆盖部分第一侧墙，以减弱或避免刻蚀SAB薄膜时对第一侧墙的破坏，提高多次可编程存储器的性能。
The present invention provides a cell structure of a multi-time programmable memory and a manufacturing method thereof, comprising a substrate, a floating gate located on the substrate, a first sidewall located on the sidewall of the floating gate, and a SAB film and a control gate located on the floating gate in sequence, wherein the control gate and the SAB film extend in a direction perpendicular to the thickness of the floating gate to cover part of the first sidewall. In the cell structure of the multi-time programmable memory provided by the present invention, the control gate stores and erases data by coupling with the floating gate, without the need for an additional tunneling area, so that the size of the cell structure of the multi-time programmable memory is reduced, meeting the small size requirements of the MTP device. Furthermore, the SAB film and the control gate extend in a direction perpendicular to the thickness of the floating gate to cover part of the first sidewall, so as to reduce or avoid damage to the first sidewall when etching the SAB film, thereby improving the performance of the multi-time programmable memory.
Description
Technical Field
The present invention relates to the field of integrated circuit fabrication, and more particularly, to a cell structure of a Multiple Time Programmable (MTP) memory and a method for fabricating the same.
Background
Memory is an important component of digital integrated circuits, which is an integral part of the construction of microprocessor-based application systems. In recent years, various memories have been embedded inside processors to improve the integration and the working efficiency of the processors.
Compared with a single time programmable (One time Program Memory, OTP) memory, the Multi-time programmable (Multi-Time Program Memory, MTP) memory has the advantages that the memory can store, read, erase and the like data for a plurality of times, and the stored data cannot disappear after power failure, and the memory device is widely used in the fields of personal computers, electronic equipment, mobile storage and the like.
However, the cell structure of the multi-time programmable memory formed by the conventional method is large in size and has not been ideal.
Disclosure of Invention
The invention aims to provide a cell structure of a multi-time programmable memory and a manufacturing method thereof, which reduce the size of the cell structure of the multi-time programmable memory and improve the performance of the multi-time programmable memory.
To achieve the above object, the present invention provides a cell structure of a multiple-time programmable memory, comprising:
The substrate is provided with a plurality of holes,
A floating gate on the substrate, a first sidewall on the sidewall of the floating gate, and
And the SAB film and the control gate are sequentially positioned on the floating gate, and extend along the direction perpendicular to the thickness direction of the floating gate to cover part of the first side wall.
Optionally, the semiconductor device further comprises a selection gate located on the substrate, and a second side wall is formed on the side wall of the selection gate.
Optionally, an active region is formed in the substrate, and an active doped region and a drain doped region are formed in the active region.
Optionally, the floating gate and the select gate are located between the source doped region and the drain doped region.
Optionally, the semiconductor device further comprises a self-aligned silicide layer, wherein the self-aligned silicide layer covers the selection gate, the control gate, the source doped region and the drain doped region.
Optionally, the device further comprises an interlayer dielectric layer which is positioned on the self-aligned silicide layer and covers the substrate, a conductive plug which is positioned in the interlayer dielectric layer and connected with the self-aligned silicide layer, and an electrode structure which is positioned on the interlayer dielectric layer and connected with the conductive plug.
Optionally, a gate oxide layer is formed between the floating gate and the substrate.
Optionally, the SAB film comprises an oxide layer and a nitride layer which are sequentially overlapped on the surface of the floating gate.
Optionally, the first side wall and the second side wall have an ONO structure.
Correspondingly, the invention also provides a manufacturing method of the cell structure of the multi-time programmable memory, which comprises the following steps:
Providing a substrate;
Forming a floating gate on the substrate, forming a first side wall on the side wall of the floating gate, and
And sequentially forming an SAB film and a control gate on the floating gate, wherein the SAB film and the control gate extend along the direction perpendicular to the thickness direction of the floating gate to cover part of the first side wall.
Optionally, the method further comprises the steps of forming a floating gate on the substrate, forming a selection gate on the substrate, and forming a first side wall on the side wall of the floating gate, and forming a second side wall on the side wall of the selection gate.
Optionally, forming a gate oxide layer on the substrate is further included before forming the floating gate on the substrate.
Optionally, after forming the first side wall on the side wall of the floating gate, before sequentially forming the SAB film layer and the control gate layer on the substrate, the method further comprises the step of performing ion implantation on the substrate to form a source doping region and a drain doping region.
Optionally, the SAB film includes an oxide layer and a nitride layer sequentially stacked on the surface of the floating gate, and the first side wall and the second side wall both have ONO structures.
Optionally, sequentially forming the SAB thin film and the control gate on the floating gate includes the following steps:
Forming an SAB thin film material layer and a control gate material layer on the substrate;
Forming a patterned photoresist layer on the control gate material layer using an SAB mask;
And etching the control gate material layer and the SAB film material layer in sequence to form the SAB film and the control gate on the floating gate in sequence.
Optionally, after forming the SAB thin film and the control gate on the floating gate, the method further includes:
Forming a self-aligned silicide layer on the substrate, wherein the self-aligned silicide layer covers the selection gate, the control gate, the source doping region and the drain doping region;
Forming an interlayer dielectric layer on the substrate;
Forming contact holes exposing the selection gate, the control gate, the source doping region and the drain doping region in the interlayer dielectric layer;
filling conductive material into the inner wall of the contact hole to form a conductive plug;
And forming a metal layer on the interlayer dielectric layer, and patterning the metal layer to form an electrode structure.
In summary, the invention provides a cell structure of a multiple programmable memory and a method for manufacturing the same, comprising a substrate, a floating gate on the substrate, a first sidewall on the sidewall of the floating gate, and a SAB film and a control gate on the floating gate in sequence, wherein the control gate and the SAB film extend along a direction perpendicular to the thickness direction of the floating gate to cover part of the first sidewall. In the cell structure of the multi-time programmable memory, the control gate is used for storing and erasing data by coupling control floating gate, and an additional Tunneling area (Tunneling area) is not needed, so that the size of the cell structure of the multi-time programmable memory is reduced, and the miniaturization requirement of an MTP device is met. Furthermore, the SAB film and the control gate extend along the direction perpendicular to the thickness direction of the floating gate to cover part of the first side wall, so that damage to the first side wall during etching of the SAB film is reduced or avoided, and the performance of the multi-time programmable memory is improved.
Drawings
FIG. 1A is a schematic top view of a multi-time programmable memory cell structure, and FIG. 1B is a schematic cross-sectional view of the multi-time programmable memory cell structure along line aa' in FIG. 1A;
FIG. 2 is a flowchart of a method for fabricating a cell structure of a multi-time programmable memory according to an embodiment of the present invention;
Fig. 3 to fig. 7B are schematic structural diagrams corresponding to corresponding steps of a method for fabricating a cell structure of a multi-time programmable memory according to an embodiment of the present invention;
FIG. 7C is a schematic top view of a cell structure of a multi-time programmable memory according to another embodiment of the present invention;
Fig. 8A to 8B are schematic diagrams illustrating a cell structure of a multi-time programmable memory according to an embodiment of the invention for writing and erasing data.
Wherein, the reference numerals are as follows:
10. cell structure of 20-multiple time programmable memory;
103. 104, 105, 203, 204, 205-n+ doped regions;
100. 200-substrate;
110. 210-floating gate;
120. 220-select gates;
130-tunneling region;
211-a first side wall;
221-a second side wall;
230' -SAB thin film material layer;
230-SAB film;
231', 231-oxide layer;
232', 232-nitride layer;
240' -a control gate material layer;
240-control gate;
250-patterned photoresist;
101. 201-P well;
202-gate oxide;
206-a self-aligned metal silicide layer;
207-an interlayer dielectric layer;
108. 208-conductive plugs;
113. 213-source electrode;
114. 214-select signal electrode;
115. 215-drain electrode;
116. 216-programming signal electrode.
Detailed Description
FIG. 1A is a schematic top view of a multi-time programmable memory cell structure, and FIG. 1B is a schematic cross-sectional view of the multi-time programmable memory cell structure along line aa' in FIG. 1A. As shown in fig. 1A and 1B, the cell structure 10 of the multi-time programmable memory includes a P-Well (P-Well) 101 formed in a substrate 100, a floating gate 110 (FG) and a select gate 120 (SG) formed on the P-Well 101, n+ doped regions 103, 104, 105 on both sides of the floating gate 110 and the select gate 120, and a program signal electrode 116, a select signal electrode 114, a source electrode 113, and a drain electrode 115 electrically connected to the floating gate 110, the select gate 120, the n+ doped region 103, and the n+ doped region 105, respectively, through conductive plugs 108. For a single poly gate (floating gate) structure, the Programming (PGM) and Erasing (ERS) operations of the MTP cell are achieved by injecting electrons or holes into the floating gate 110 or erasing electrons or holes, requiring an additional Tunneling area (Tunneling area) 130 to achieve the above-described functions, which results in an increase in the size of the cell structure 10 (1 Bit-cell) of the multi-time programmable memory (about 10-90um 2), which is disadvantageous for the realization of the miniaturization of the MTP device.
The invention provides a cell structure of a multiple programmable memory and a manufacturing method thereof, and the cell structure comprises a substrate, a floating gate arranged on the substrate, a first side wall arranged on the side wall of the floating gate, and an SAB film and a control gate which are sequentially arranged on the floating gate, wherein the SAB film and the control gate extend along the direction perpendicular to the thickness direction of the floating gate to cover part of the first side wall. In the cell structure of the multi-time programmable memory, the control gate is used for controlling the floating gate to store and erase data through coupling, and an additional Tunneling area (Tunneling area) is not needed, so that the size of the cell structure of the multi-time programmable memory is reduced, and the miniaturization requirement of an MTP device is met. Furthermore, the SAB film and the control gate extend along the direction perpendicular to the thickness direction of the floating gate to cover part of the first side wall, so that damage to the first side wall during etching of the SAB film is reduced or avoided, and the performance of the multi-time programmable memory is improved.
The following describes the cell structure of the multi-time programmable memory and the manufacturing method thereof in further detail with reference to the accompanying drawings and the specific embodiments. The advantages and features of the present invention will become more apparent from the following description and drawings, however, it should be understood that the inventive concept may be embodied in many different forms and is not limited to the specific embodiments set forth herein. The drawings are in a very simplified form and are to non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention. Furthermore, it should be readily understood that the meanings of "on" and "on" herein should be interpreted in the broadest sense such that the meaning of "on" and "on" is not only "directly on" without intermediate features or intermediate layers, but also includes the meaning of "on" with intermediate features or intermediate layers. For the sake of clarity of description, the present invention provides a cell structure of the multiple-time programmable memory, in which the interlayer dielectric layer is omitted in the schematic top view of the cell structure of the multiple-time programmable memory shown in fig. 7A and 7C, and the floating gate covered by the control gate is shown with a dotted line.
The terms "first," "second," and the like in the description are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other sequences than described or illustrated herein. Similarly, if a method described herein comprises a series of steps, and the order of the steps presented herein is not necessarily the only order in which the steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method. If a component in one drawing is identical to a component in another drawing, the component will be easily recognized in all drawings, but in order to make the description of the drawings clearer, the specification does not refer to all the identical components in each drawing.
Fig. 7A is a schematic top view of a cell structure of a multi-time programmable memory according to the present embodiment, and fig. 7B is a schematic cross-sectional view of the cell structure of the multi-time programmable memory along the bb' line in fig. 7A. As shown in fig. 7A and 7B, the cell structure 20 of the multi-time programmable memory provided in this embodiment includes a substrate 200, a floating gate 210 and a select gate 220 on the substrate 200, a first sidewall 211 on a sidewall of the floating gate 210, a second sidewall 221 on a sidewall of the select gate 220, and a SAB film 230 and a control gate 240 on the floating gate 210, where the SAB film 230 and the control gate 240 extend along a direction perpendicular to a thickness direction of the floating gate 210 to cover a portion of the first sidewall 211.
The substrate 200 may be made of single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon On Insulator (SOI), germanium On Insulator (GOI), or other materials, such as gallium arsenide, or other III-V compounds. The substrate 200 in this embodiment is a silicon substrate, which is only an example, and the present invention is not limited thereto. Preferably, the substrate 200 has a deep well therein, for example, the deep well has a P-type doping (P-well 201), and a shallow trench isolation structure (not shown) is formed in the substrate 200, and the active region (ACTIVE AREA, AA) is defined by the shallow trench isolation structure. The floating gate 210 and the select gate 220 are located on the active region AA, and n+ doped regions 203, 204, 205 are formed in the active region AA on both sides of the floating gate 210 and the select gate 220. The floating gate 210 and the select gate 220 share the n+ doped region 204, and the n+ doped region 203 is illustratively defined as a source doped region and the n+ doped region 205 is a drain doped region for convenience of description.
The substrate 200 includes a memory cell region in which the floating gate 210 and the select gate 220 are located, and a peripheral circuit region on which a structure such as a capacitor is formed for forming a memory transistor and a high voltage transistor for controlling the memory transistor. Since the present invention is mainly described in terms of the structural features of the multiple-time programmable memory cell area, in order to clearly illustrate the core idea of the present invention, only the device and structure of a part of the multiple-time programmable memory cell area are shown in the drawings by the schematic drawing, but this does not represent that the present invention relates to the multiple-time programmable memory cell structure including only these parts, and the known multiple-time programmable memory cell structure may be also included therein. The structure and the forming method in the peripheral circuit region are the same as those in the prior art, and are not described herein.
The interface between the floating gate 210 and the select gate 220 in contact with the substrate 200 is typically formed with a gate oxide layer 202, the gate oxide layer 202 being, for example, silicon dioxide (SiO 2). The first sidewall (Spacer) 211 and the second sidewall 221 are made of silicon dioxide or silicon nitride, and have a thickness of 3nm to 100nm. For example, the first sidewall 211 and the second sidewall 221 each have an ONO (Oxide-Nitride-Oxide) structure, that is, an isolation Oxide layer, a sidewall Nitride layer and a sidewall Oxide layer are sequentially formed on the sides of the floating gate 210 and the select gate 220 in a stacked manner, where the isolation Oxide layer is, for example, silicon dioxide (SiO 2), the sidewall Nitride layer is, for example, silicon Nitride (Si x N), and the sidewall Oxide layer is, for example, silicon oxynitride (SiO xNy) or silicon dioxide (SiO 2).
A salicide Block (SAB) film 230 is disposed between the floating gate 210 and the control gate 240, and as an inter-gate dielectric layer between the floating gate 210 and the control gate 240, the SAB film 230 may have a single layer structure composed of a single oxide or nitride or a multi-layer structure composed of an oxide or nitride, for example, the SAB film 230 may have a three-layer structure composed of an oxide layer-nitride layer-oxide layer sequentially stacked on the surface of the floating gate 210, or the SAB film 230 may have a two-layer structure composed of an oxide layer-nitride layer sequentially stacked on the surface of the floating gate 210. The oxide layer in the SAB film 230 is made of silicon dioxide (SiO 2), and the nitride layer is made of silicon nitride (Si x N). The SAB film 230 may be formed using the same or similar materials and processes as the ONO triple layer structure in the first sidewall 211 and the second sidewall 221 (but not including etching the portion forming the sidewall). In this embodiment, the SAB film 230 has a two-layer structure, and includes an oxide layer 231 and a nitride layer 232 sequentially stacked on the surface of the floating gate 210.
As shown in fig. 7B, when the SAB thin film 230 and the control gate 240 cover a portion of the first sidewall 211 near the side of the floating gate 210 and the SAB thin film 230 and the control gate 240 are etched, etching is stopped at the side of the first sidewall 211 near the floating gate 210 (Landing on Spacer). Since the structure compositions of the SAB film 230 and the first sidewall 211 are similar, the ONO structure of the first sidewall 211 is damaged during the etching process of forming the SAB film 230 and the control gate 240, and when the isolation oxide layer on the inner side of the first sidewall 211 is etched laterally, the floating gate 210 may contact with the source/drain doped region, resulting in a short circuit. Therefore, when the SAB film 230 and the control gate 240 are formed by etching, the surface of the floating gate 210 is covered by the control gate and extends along the direction perpendicular to the thickness direction of the floating gate to cover part of the first side wall 211, so as to weaken or avoid damaging the first side wall 211 when the SAB film 230 is etched, further avoid the loss of the isolation oxide layer of the inner layer of the first side wall 211 due to side etching, and improve the performance of the multiple-time programmable memory.
As shown in fig. 7A and 7B, the cell structure 20 of the multi-time programmable memory provided in this embodiment further includes a salicide layer 206, where the salicide layer 206 covers the select gate 220, the control gate 240, and the n+ doped regions 203, 204, 205. The salicide layer 206 is, for example, a metal silicide such as cobalt silicide (Cobalt Silicide), titanium silicide (Titanium Silicide) or nickel silicide (NICKEL SILICIDE) that has low resistance and good adhesion to silicon material. The salicide layer 206 may be used as a Contact structure (Contact) for a transistor to pull out the source, drain, and gate of the transistor.
The cell structure 20 of the otp memory provided in this embodiment further includes an interlayer dielectric layer 207 on the salicide layer 206 and covering the substrate 200, a conductive plug 208 in the interlayer dielectric layer 207 and connected to the salicide layer 206, and an electrode structure on the interlayer dielectric layer 207 and connected to the conductive plug 208. The electrode structure includes a source electrode 213 (S/L), a drain electrode 215 (B/L), a selection signal electrode 214, and a program signal electrode 216, wherein the source electrode 213 (S/L), the drain electrode 215 (B/L), the selection signal electrode 214, and the program signal electrode 216 are respectively connected to the n+ doped region 203, the n+ doped region 205, the selection gate 220, and the self-aligned metal silicide layer 206 on the control gate 240 through the conductive plugs 208.
The memory cell region of the otp memory of this embodiment includes a plurality of the cell structures 20 (dashed boxes in the figure), and the floating gate 210 and the control gate 240 in the cell structures 20 may be formed on an active area AA independently. As shown in fig. 7A. In other embodiments of the present invention, the control gates 240 of adjacent cell structures 20 in the memory cell region of the multiple-time programmable memory may be shared, i.e., the floating gate 210 Segments (SEGMENTED) are located below the control gates 240, as shown in fig. 7C.
In the cell structure of the multi-time programmable memory provided in this embodiment, the floating gate 210 is used as an electron storage layer, and by programming, when the voltage difference between the control gate 240 and the substrate 200 is sufficiently large, electrons collected in a channel can enter the floating gate 210 through a tunneling effect, and the gate dielectric layer (SAB film 230) between the control gate 240 and the floating gate 210 prevents electrons from being lost through the control gate 240, so that electrons are stored in the floating gate 210. Specifically, referring to fig. 8A, a high positive bias is applied to the control gate 240 so that electrons are injected from the n+ doped region 203 through the gate dielectric layer 202 into the floating gate 210 when performing a data writing (PGM) operation, and referring to fig. 8B, a high negative bias is applied to the control gate 240 when performing a data Erasing (ERS) operation, the control gate 240 controls the release of electrons in the floating gate 210 by coupling so that electrons stored in the floating gate 210 are removed from the floating gate 210 by Fowler-Nordheim (FN) tunneling effect, thereby completing the erasing of the cell structure memory data of the MTP device.
The cell structure 20 (dashed line box in the figure) of the multi-time programmable memory provided in this embodiment includes the select gate 220, the floating gate 210, the SAB thin film 230 and the control gate 240 on the substrate 200, and the SAB thin film 230 and the control gate 240 on the floating gate 210, where the control gate 240 controls the floating gate 210 to store and erase data through coupling, and no additional Tunneling area (Tunneling area) is needed, so that the size of the cell structure 20 (1 Bit-cell) of the multi-time programmable memory is reduced (about 1-10um 2), and the miniaturization requirement of the MTP device is satisfied. Further, the control gate 240 and the SAB film 230 extend along a direction perpendicular to the thickness direction of the floating gate to cover a portion of the first sidewall 211, so as to weaken or avoid damage to the first sidewall 211 when etching the SAB film, and improve performance of the multi-time programmable memory.
Correspondingly, the invention also provides a method for manufacturing a cell structure of the multi-time programmable memory, fig. 2 is a flowchart of the method for manufacturing the cell structure of the multi-time programmable memory provided by the embodiment, and as shown in fig. 2, the method for manufacturing the cell structure of the multi-time programmable memory provided by the embodiment comprises the following steps:
s01, providing a substrate;
s02, forming a floating gate on the substrate, forming a first side wall on the side wall of the floating gate, and
S03, sequentially forming an SAB film and a control gate on the floating gate, wherein the SAB film and the control gate extend along the direction perpendicular to the thickness direction of the floating gate to cover part of the first side wall.
Fig. 3 to fig. 7B are schematic structural diagrams corresponding to respective steps of a method for manufacturing a cell structure of a multi-time programmable memory according to the present embodiment. The method for manufacturing the cell structure of the otp memory according to the present embodiment will be described in detail below with reference to fig. 2 and fig. 3 to 7B.
First, as shown in fig. 3, step S01 is performed to provide a substrate 200. The material of the substrate 200 may be single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon On Insulator (SOI), germanium On Insulator (GOI), or other materials, such as gallium arsenide, or other III-V compounds. The substrate 200 in this embodiment is only exemplified by a silicon substrate, and the present invention is not limited thereto. In performing step S01, it is considered that the process steps including, but not limited to, forming isolation trenches (e.g., shallow trench isolation structures, STI) on the substrate 200 and performing well implants (e.g., P-well 201), other ion implants, and annealing on the substrate 200 may also be performed on the substrate 200.
Next, with continued reference to fig. 3, step S02 is performed to form a floating gate 210 on the substrate 200, and to form a first sidewall 211 on the sidewall of the floating gate 210. Before forming the floating gate 210, a gate oxide 202 is formed on the substrate 200, and a thermal oxidation (wet oxidation or dry oxidation) process, an in-situ steam generation process (ISSG), a Chemical Vapor Deposition (CVD) process, an atomic layer deposition process, or the like may be used to form the gate oxide 202 on the global surface of the substrate 200, where the gate oxide 202 may be made of silicon dioxide (SiO 2), silicon oxynitride (SiO xNy), silicon nitride (Si x N), or the like, and may have a thickness of 2nm to 30nm.
It should be noted that the materials of the layers, the thicknesses of the layers and the forming manners of the layers, which are described above and will be mentioned below, are merely examples of the embodiments of the present invention, and different materials, different thicknesses and different forming manners may be used in different cases, which should not limit the present invention.
After forming the gate oxide 202 on the substrate 200, a floating gate 210 and a select gate 220 are formed on the gate oxide 202. Specifically, a gate material layer is first formed on the substrate 200, where the material of the gate material layer may be polysilicon, a metal material compound or other suitable materials, then a patterned photoresist layer is formed on the gate material layer, and then the patterned photoresist layer is used as a mask to etch the gate material layer to form the floating gate 210 and the select gate 220. In this embodiment, the materials of the floating gate 210 and the select gate 220 are polysilicon, for example, dry etching may be used to form the floating gate 210 and the select gate 220. In other embodiments of the present invention, the materials of the floating gate 210 and the select gate 220 may be different, or the floating gate 210 and the select gate 220 may be formed by different methods, which is not limited herein.
After forming the floating gate 210 and the select gate 220 on the gate oxide 202, a first sidewall 211 and a second sidewall 221 are formed on sidewalls of the floating gate 210 and the select gate 220, respectively. The first side wall 211 and the second side wall 221 are made of silicon oxide or silicon nitride or a combination thereof, and the thickness is 3nm to 100nm. For example, the first sidewall 211 and the second sidewall 221 each have an ONO (Oxide-Nitride-Oxide) structure, that is, an isolation Oxide layer, a sidewall Nitride layer and a sidewall Oxide layer (not shown in the drawing) formed by sequentially stacking the sides of the floating gate 210 and the select gate 220, where the isolation Oxide layer is close to the floating gate 210 and the select gate 220, and is an inner layer of the first sidewall 211 and the second sidewall 221, and the isolation Oxide layer is, for example, silicon dioxide (SiO 2), the sidewall Nitride layer is, for example, silicon Nitride (Si x N), and the sidewall Oxide layer is, for example, silicon oxynitride (SiO xNy) or silicon dioxide (SiO 2). Illustratively, the isolation oxide layer may be deposited by a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, the sidewall nitride layer may be deposited by a Low Pressure Chemical Vapor Deposition (LPCVD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, or the like, and the sidewall oxide layer may be deposited by an Atmospheric Pressure Chemical Vapor Deposition (APCVD) process, a Low Pressure Chemical Vapor Deposition (LPCVD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, or the like. The forming of the first sidewall 211 and the second sidewall 221 further includes anisotropically etching the isolation oxide layer, the sidewall nitride layer, and the sidewall oxide layer.
After the first sidewall 211 and the second sidewall 221 are formed, ion implantation is performed on the substrate 200, and n+ doped regions 203, 204, 205 are formed on both sides of the floating gate 210 and the select gate 220. For example, at least one of phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions, for example, may be implanted using an existing source drain implantation process, and a high temperature anneal may be performed after the implantation. The floating gate 210 and the select gate 220 share the n+ doped region 204, and the n+ doped region 203 is illustratively defined as a source doped region and the n+ doped region 205 is a drain doped region for convenience of description.
Next, as shown in fig. 4 to 6, step S03 is performed, in which a SAB thin film 230 and a control gate 240 are sequentially formed on the floating gate 210, and the SAB thin film 230 and the control gate 240 cover a portion of the first sidewall 211 near one side of the floating gate 230. Specifically, first, as shown in fig. 4, a SAB thin film material layer 230 'and a control gate material layer 240' are sequentially formed on the substrate 200. In this embodiment, the SAB thin film material layer 230 'is a dual-layer structure composed of an oxide layer 231' and a nitride layer 232', for example, the oxide layer 231' is made of silicon dioxide (SiO 2), the nitride layer 232 'is made of silicon nitride (Si x N), the oxide layer 231' may be formed by Low Pressure Chemical Vapor Deposition (LPCVD), and then the nitride layer 232 'may be formed on the oxide layer 231' by low pressure chemical vapor deposition. The SAB thin film material layer 230' may also have a three-layer structure comprising an oxide layer, a nitride layer and an oxide layer in other embodiments of the present invention. Next, a control gate material layer 240' is formed on the SAB thin film material layer 230', and the material of the control gate material layer 240' may be polysilicon, a metal material compound, or other suitable materials. In this embodiment, the floating gate 210 and the control gate 240 are made of polysilicon.
Then, as shown in fig. 5, a patterned photoresist layer 250 is formed on the surface of the control gate material layer 240 'by using an SAB mask (SAB Photo), wherein the patterned photoresist layer 250 covers the control gate material layer 240' on the floating gate 210 and extends toward the first side walls 210 on both sides of the floating gate 210, so as to avoid damaging the ONO structure of the first side walls 211 during subsequent etching of the SAB film material layer, and particularly avoid damaging the isolation oxide layer located on the inner side of the first side walls 211 by side etching. Next, the control gate material layer 240 'and the SAB film material layer 230' are etched in sequence using the patterned photoresist layer 250 as a mask, the SAB film 230 and the control gate 240 are formed on the floating gate 210, and the SAB film 230 and the control gate 240 extend along a direction perpendicular to the thickness direction of the floating gate 210 to cover a portion of the first sidewall 211, as shown in fig. 6. For example, the control gate material layer 240 'may be removed by dry etching, so as to form the control gate 240, and then the nitride layer 232' and the oxide layer 231 'in the SAB thin film material layer 230' may be sequentially removed by wet etching. If the nitride layer 232 'may be removed by a phosphoric acid solution wet method, and then the oxide layer 231' may be removed by a hydrofluoric acid solution wet method, the wet etching is stopped at the first sidewall 211, so that the SAB film 230 and the control gate 240 formed after etching cover part of the first sidewall 211, and the isolation oxide layer in the first sidewall 211 near the floating gate 210 is protected. In this embodiment, the thickness of the nitride layer 232 in the SAB thin film layer 230 is 5nm-10nm, the oxide layer 231 is a silicon oxide layer, and the thickness is 5nm-10nm. As shown in fig. 6, the thickness d of the SAB film 230 and the control gate 240 covering the first sidewall 210 is 20nm-30nm, and the thickness d of the SAB film 230 and the control gate 240 covering portions are different according to the structure of the first sidewall 211.
The method for fabricating the cell structure of the multi-time programmable memory further includes forming a salicide layer 206, wherein the salicide layer 206 is a metal silicide (METAL SILICIDE), such as cobalt silicide (Cobalt Silicide), titanium silicide (Titanium Silicide) and nickel silicide (NICKEL SILICIDE). With continued reference to fig. 7B, a salicide process may be used to form a salicide 206 on the select gate 220, the control gate 240, and the n+ doped regions 203, 204, 205, including forming a metal layer (e.g., at least one metal selected from the group consisting of nickel Ni, cobalt Co, tungsten W, platinum Pt, manganese Mn, titanium Ti, tantalum Ta, etc.) on the substrate 200, the metal layer covering the surfaces of the select gate 220, the control gate 240, and the n+ doped regions 203, 204, 205, and then performing a thermal annealing process to react the metal particles (M) in the metal layer with the silicon (Si) on the surfaces of the select gate 220, the control gate 240, and the n+ doped regions 203, 204, 205 to form a salicide (MSi x) layer 206. The salicide layer 206 may reduce the Contact resistance between the select gate 220, the control gate 240, and the n+ doped regions 203, 204, 205 and subsequently formed conductive plugs (contacts), and improve device performance. It should be noted that the patterning of the gate oxide layer 202 is further included before the forming of the salicide layer 206, exposing the n+ doped regions 203, 204, 205.
Thereafter, as shown in fig. 7A and 7B, the method for fabricating a cell structure of a multiple-time programmable memory further includes forming an interlayer dielectric layer 207 on the substrate 200, wherein the interlayer dielectric layer 207 is, for example, a silicon dioxide layer, forming a contact hole in the interlayer dielectric layer 207, for example, etching the interlayer dielectric layer 207 by dry etching to form a contact hole exposing the n+ doped region 203, the n+ doped region 205, the selection gate 220 and the control gate 240, filling conductive material, for example, tungsten metal, into an inner wall of the contact hole to form a conductive plug 208, forming a metal layer on the interlayer dielectric layer 207, and patterning the metal layer to form an electrode structure. The electrode structure includes a source electrode 213 (S/L), a drain electrode 215 (B/L), a selection signal electrode 214, and a program signal electrode 216, wherein the source electrode 213 (S/L), the drain electrode 215 (B/L), the selection signal electrode 214, and the program signal electrode 216 are respectively connected to the n+ doped region 203, the n+ doped region 205, the selection gate 220, and the self-aligned metal silicide layer 206 on the control gate 240 through the conductive plugs 208.
In the method for manufacturing the cell structure of the multiple programmable memory provided by the invention, the SAB film is adopted as the inter-gate dielectric layer between the control gate and the floating gate, and when the control gate 240 and the SAB film 230 are formed by etching, the pattern for defining the control gate 240 can be embedded into the SAB mask for defining the SAB film, and the control gate 240 and the SAB film 230 can be simultaneously defined by using one SAB mask. And the SAB film and the control gate extend along the direction perpendicular to the thickness direction of the floating gate to cover part of the first side wall, so that damage to the first side wall when the SAB film is etched is weakened or avoided, and the performance of the multi-time programmable memory is improved.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (14)
1. A method for fabricating a cell structure of a multiple-time programmable memory, comprising:
Providing a substrate;
Forming a floating gate on the substrate, forming a first side wall on the side wall of the floating gate, and
Sequentially forming an SAB film material layer and a control gate material layer on the substrate;
Forming a patterned photoresist layer on the control gate material layer by adopting an SAB mask, wherein the patterned photoresist layer covers the control gate material layer on the floating gate and extends to first side walls on two sides of the floating gate;
And sequentially etching the control gate material layer and the SAB film material layer by taking the patterned photoresist layer as a mask, sequentially forming a control gate and an SAB film on the floating gate, and enabling the SAB film and the control gate to extend along the direction perpendicular to the thickness direction of the floating gate to cover part of the first side wall so as to weaken or avoid damaging the first side wall when etching the SAB film.
2. The method for manufacturing the cell structure of the multi-time programmable memory according to claim 1, further comprising forming a selection gate on the substrate while forming a floating gate on the substrate, and forming a first side wall on the side wall of the floating gate while forming a second side wall on the side wall of the selection gate.
3. The method of claim 1, further comprising forming a gate oxide layer on the substrate before forming the floating gate on the substrate.
4. The method of claim 2, further comprising implanting ions into the substrate to form a source doped region and a drain doped region after forming the first sidewall on the sidewall of the floating gate and before sequentially forming the SAB thin film layer and the control gate layer on the substrate.
5. The method for manufacturing the cell structure of the multiple-time programmable memory according to claim 2, wherein the SAB film comprises an oxide layer and a nitride layer which are sequentially overlapped on the surface of the floating gate, and the first side wall and the second side wall are both provided with an ONO structure.
6. The method of fabricating a cell structure of a multiple-time programmable memory of claim 4, further comprising, after forming the SAB thin film and the control gate on the floating gate:
Forming a self-aligned metal silicide layer on the substrate, wherein the self-aligned metal silicide layer covers the selection gate, the control gate, the source doping region and the drain doping region;
Forming an interlayer dielectric layer on the substrate;
Forming contact holes exposing the selection gate, the control gate, the source doping region and the drain doping region in the interlayer dielectric layer;
filling conductive material into the inner wall of the contact hole to form a conductive plug;
And forming a metal layer on the interlayer dielectric layer, and patterning the metal layer to form an electrode structure.
7. A cell structure of a multiple-time programmable memory, characterized in that it is manufactured by a manufacturing method of a cell structure of a multiple-time programmable memory according to any one of claims 1 to 6, comprising:
The substrate is provided with a plurality of holes,
A floating gate on the substrate, a first sidewall on the sidewall of the floating gate, a gate oxide layer formed between the floating gate and the substrate, the gate oxide layer comprising silicon dioxide, and
The SAB film and the control gate are sequentially arranged on the floating gate, and extend to cover part of the first side wall along the direction perpendicular to the thickness direction of the floating gate, so that damage to the first side wall when the SAB film is etched is weakened or avoided.
8. The cell structure of claim 7, further comprising a select gate on the substrate, a sidewall of the select gate being formed with a second sidewall.
9. The cell structure of claim 8, wherein an active region is formed in the substrate, and an active doping region and a drain doping region are formed in the active region.
10. The cell structure of the multiple-time programmable memory of claim 9, wherein the floating gate and the select gate are located between the source doped region and the drain doped region.
11. The cell structure of claim 9, further comprising a self-aligned metal silicide layer covering the select gate, the control gate, and the source and drain doped regions.
12. The multi-time programmable memory cell structure of claim 11, further comprising an interlayer dielectric layer on said salicide layer and covering said substrate,
A conductive plug in the interlayer dielectric layer and connected with the self-aligned metal silicide layer,
And an electrode structure on the interlayer dielectric layer and connected with the conductive plug.
13. The cell structure of claim 7, wherein the SAB film comprises an oxide layer and a nitride layer sequentially stacked on the floating gate surface.
14. The cell structure of claim 8, wherein the first sidewall and the second sidewall each have an ONO structure.
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| CN113921528A (en) * | 2021-09-29 | 2022-01-11 | 上海华力微电子有限公司 | SONOS memory and preparation method thereof |
| CN114050157B (en) * | 2021-09-29 | 2024-11-12 | 上海华虹宏力半导体制造有限公司 | OTP storage unit manufacturing method and OTP storage unit structure |
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| CN114843278A (en) * | 2022-04-14 | 2022-08-02 | 上海华力集成电路制造有限公司 | A process method of embedded SONOS flash memory |
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|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
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Address after: 230012 No.88, xifeihe Road, comprehensive bonded zone, Xinzhan District, Hefei City, Anhui Province Applicant after: Nexchip Semiconductor Corporation Address before: 230012 No.88, xifeihe Road, comprehensive bonded zone, Xinzhan District, Hefei City, Anhui Province Applicant before: HEFEI JINGHE INTEGRATED CIRCUIT Co.,Ltd. |
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| CB02 | Change of applicant information | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |