CN111431592B - Power amplifier protection method, power amplifier protection device and computer storage medium - Google Patents

Abstract

The present application provides a power amplifier protection method, device and computer storage medium. The method includes: a programmable logic device monitors an operating state of a communication device; when the operating state is abnormal, the programmable logic device turns off baseband signals and turns off power amplifiers in the communication device The pre-push stage is enabled, and the baseband signal is the baseband signal output to the transceiver of the communication device. When the above method is in an abnormal operation state, it indicates that stray phenomena are likely to occur in the communication equipment. At this time, the baseband signal is turned off through the programmable logic device in time, and the enabling of the pre-propulsion stage of the power amplifier is turned off to stop the power input to the power amplifier circuit. To prevent the power amplifier circuit from being burnt, the effect of protecting the power amplifier circuit is achieved; and the response time of the programmable logic device is short, so the operation status of the communication equipment is monitored very quickly, and the baseband signal output to the transceiver and the pre-push stage of the power amplifier are turned off in time. Enable, can quickly avoid large stray and effectively protect the power amplifier circuit.

Description

Power amplifier protection method, power amplifier protection device and computer storage medium

technical field

The present application relates to the technical field of power amplifier protection, and in particular, to a power amplifier protection method, a power amplifier protection device, and a computer storage medium.

Background technique

At present, for power amplifier (power amplifier) circuit protection, it mainly focuses on circuit design and optimization to achieve power amplifier protection.

However, communication equipment is easily affected by factors such as interface timing, plugging and unplugging optical fibers, power-on and power-off, temperature changes, etc., and large spurs will occur in a very short period of time. When the spurious signal is not detected and exceeds the tolerance range of the power amplifier, it will cause the power amplifier to burn out. Therefore, for the influence of stray factors on the power amplifier, how to avoid the stray factors for the power amplifier has become one of the many problems faced by the current power amplifier protection.

SUMMARY OF THE INVENTION

The primary purpose of the present invention is a power amplifier protection method, a power amplifier protection device and a computer storage medium.

A power amplifier protection method, comprising the following steps:

The programmable logic device monitors the operating status of the communication equipment;

When the running state is abnormal, the programmable logic device turns off the baseband signal and turns off the enabling of the pre-push stage of the power amplifier in the communication device, where the baseband signal is the baseband signal output to the transceiver of the communication device .

In one embodiment, after the step of monitoring the operating state of the communication device by the programmable logic device, the method further includes:

When the operating state is abnormal, the monitoring processor turns off the gate voltages of the booster stage and the last stage of the power amplifier.

In one embodiment, the operating state includes an optical port state;

The step of the programmable logic device monitoring the running state of the communication equipment includes:

acquiring a plurality of optical indication information of the optical signal of the communication device;

When any one of the optical indication information indicates abnormality, it is determined that the state of the optical port is abnormal;

When the multiple indication information of the optical signal all belong to the normal range, it is determined that the state of the optical port is normal.

In one embodiment, the operating state includes a link establishment state of a communication link between the programmable logic device and the transceiver;

The step of the programmable logic device monitoring the running state of the communication equipment includes:

Monitoring synchronous port status, valid port status and ready port status, wherein the ready port status is used to indicate whether the link is ready for information sending and receiving;

When the level signals corresponding to the synchronous port state, the valid port state and the ready port state are all normal level signals, it is determined that the link establishment state is normal; otherwise, it is determined that the link establishment state is abnormal.

In one embodiment, the operating state includes a power state;

The step of detecting the operating state of the communication device by the programmable logic device includes:

When it is detected that the signal output by the comparison circuit belongs to the power abnormality alarm indication signal, it is determined that the power supply state is abnormal, wherein the comparison circuit is used for judging that the power supply voltage is not within the predetermined range to output the power supply abnormality alarm indication signal.

In one embodiment, before the step of detecting the operating state of the communication device by the programmable logic device, the method further includes:

Before the power supply is normally turned on, continuously monitor whether the power supply voltage is greater than a predetermined value within a first time period, and if so, determine that the state of the power supply is normal, wherein the first time period is far greater than the programmable logic device minimum response time.

In one embodiment, the first period of time is greater than or equal to 5 seconds.

In one embodiment, the operating state includes an alarm detection state;

The step of the programmable logic device monitoring the running state of the communication equipment includes:

The programmable logic device monitors the variables of PLL clock lock, optical synchronization and ring network alarms, and receives information from the supervisory processor of the synthesized alarms of the transceiver;

When any one of the variables indicates an abnormality or when the information of the synthesized alarm indicates an abnormality, it is determined that the alarm detection state is abnormal;

When the variables all belong to the normal range and the information of the synthesized alarm indicates normal, it is determined that the alarm detection state is normal.

In one embodiment, the operating state includes a power detection state;

The step of the programmable logic device monitoring the running state of the communication equipment includes:

The programmable logic device counts forward average power according to the first statistical point, and calculates the current forward peak power according to the second statistical point;

When the forward average power is greater than the first preset threshold or the current forward peak power is greater than the second preset threshold, it is determined that the power detection state is abnormal; otherwise, the power detection state is determined to be normal.

In one embodiment, after the step of monitoring the operating state of the communication device by the programmable logic device, the method further includes:

The monitoring processor reads the running state monitored by the programmable logic device;

The monitoring processor controls the operating state of register latches in the programmable logic device according to the operating state.

In one embodiment, before the step of monitoring the operating state of the communication device by the programmable logic device, the method further includes:

The programmable logic device is powered on and configured by a supervisory processor.

A power amplifier protection device, comprising:

The monitoring module is used for the programmable logic device to monitor the running state of the communication equipment;

The protection module is configured to, when the operating state is abnormal, the programmable logic device to turn off the baseband signal output to the transceiver of the communication device and to turn off the enabling of the pre-push stage of the power amplifier in the communication device.

A computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, implements the steps of the power amplifier protection method described in any of the foregoing embodiments.

A power amplifier protection method, comprising the following steps:

The programmable logic device monitors whether the power state remains normal for a second time period, wherein the second time period is far greater than the shortest response time of the programmable logic device;

When the power state remains normal within the second time period, the programmable logic device turns on the pre-push stage enable, and the monitoring processor turns on the gate voltage of the push stage and the last stage to turn on the power amplifier.

In one embodiment, the second period of time is greater than or equal to 5 seconds.

In one embodiment, the power amplifier protection method further includes:

When the power state remains normal for the second time period, the monitoring processor clears the operating state of the register latch in the programmable logic device.

In one embodiment, the power amplifier protection method further includes:

When there is an abnormality in the power state during the second time period, the operation state of the register latch in the programmable logic device is retained, the pre-push stage enable of the power amplifier is kept invalid, and the push stage of the power amplifier is kept and the last stage gate voltage is off.

In one embodiment, after the power state remains normal within the second time period, the method further includes:

The programmable logic device monitors whether the optical port status is normal, and monitors whether the link establishment status is normal; the link establishment status is the status of the communication link between the programmable logic device and the transceiver;

When the optical port state and the link establishment state are normal, the programmable logic device turns on the pre-push stage enable, and the monitoring processor turns on the push stage and the last stage gate voltage to turn on the power amplifier.

In one embodiment, the step of monitoring whether the state of the optical port is normal includes:

Acquiring a plurality of optical indication information of the optical signal in the communication device;

When any one of the optical indication information indicates abnormality, it is determined that the state of the optical port is abnormal;

When the plurality of indication information of the optical signal all belong to the normal range, it is determined that the state of the optical port is normal.

In one embodiment, the step of monitoring whether the link establishment status is normal includes:

Monitoring synchronous port status, valid port status and ready port status, wherein the ready port status is used to indicate whether the link is ready for information sending and receiving;

When the level signals corresponding to the synchronous port state, the valid port state and the ready port state are all normal level signals, it is determined that the link establishment state is normal; otherwise, it is determined that the link establishment state is abnormal.

In one embodiment, the step of monitoring whether the power state remains normal within the second time period includes:

When the comparison circuit detects that the power supply voltage is within the predetermined range, continuously monitor whether the power supply voltage is within the predetermined range in the second time period, and if so, determine that the power supply state is normal, wherein all the The comparison circuit is used for judging whether the supply voltage is within a predetermined range.

In one embodiment, before the step of monitoring whether the power supply state remains normal for the second time period, the programmable logic device further comprises:

The monitoring processor turns off the booster stage and the last stage gate voltage of the power amplifier;

And the programmable logic device to turn off the pre-push stage of the power amplifier.

In one embodiment, after the monitoring processor turns off the step of turning off the push stage and the final gate voltage of the power amplifier and the programmable logic device turns off the enabling of the pre-push stage of the power amplifier, the method further includes:

The monitoring processor loads the file containing the run configuration;

Registers of the programmable logic device are initialized according to the operating configuration.

In an embodiment, after the optical port state and the link establishment state are normal, the method further includes:

Monitor the alarm information of PLL clock lock, optical synchronization and ring network alarms, and synthesized alarms of transceivers;

When the alarm information is normal, the programmable logic device turns on the pre-push stage enable, and the monitoring processor turns on the gate voltage of the push stage and the last stage, so as to turn on the power amplifier.

A power amplifier protection device, comprising:

a state monitoring module for the programmable logic device to monitor whether the power state remains normal within a second time period, wherein the second time period is far greater than the shortest response time of the programmable logic device;

A power amplifier turn-on module, configured to turn on the pre-push stage enable by the programmable logic device and monitor the processor to turn on the gate voltage of the push stage and the last stage to turn on the power amplifier when the power state remains normal within the second time period.

When the above-mentioned power amplifier protection method, power amplifier protection device and computer storage medium are abnormal, it indicates that stray phenomena are likely to occur in the communication equipment. Enable to stop the power input to the power amplifier circuit, prevent the power amplifier circuit from being burned, and achieve the effect of protecting the power amplifier circuit; and the response time of the programmable logic device is short, so it can monitor the operation status of the communication equipment very quickly, and the programmable logic The device can respond to large spurs generated in a very short period of time, or can prevent large spurs that are about to occur, turn off the baseband signal output to the transceiver in time, and turn off the enablement of the pre-propulsion stage of the power amplifier, which can quickly avoid large spurs. Spurs protect the power amplifier circuit in a timely and effective manner.

Monitoring the processor to turn off the gate voltage of the booster stage and the last stage of the power amplifier can prevent the signal isolation of the pre-push stage from being insufficient, thereby preventing the signal from radiating to the booster stage and the last stage of the power amplifier, so as to completely turn off the power amplifier and protect the power amplifier more thoroughly.

By continuously monitoring whether the power supply voltage is greater than the predetermined value in the second time period, if yes, it is determined that the power supply is in a normal state, and the normal power supply can be monitored for a continuous period of time to ensure that the power supply remains stable, and avoid the problem of normal power supply and turning on the power amplifier. Instantaneous power abnormality, thus avoiding damage to the power amplifier.

Additional aspects and advantages of the present application will be set forth in part in the following description, which will be apparent from the following description, or learned by practice.

Description of drawings

The above and/or additional aspects and advantages will become apparent and readily understood from the following description of embodiments taken in conjunction with the accompanying drawings, wherein:

1 is an implementation environment diagram of a power amplifier protection method provided in an embodiment;

2 is a flowchart of a power amplifier protection method in one embodiment;

3 is a flowchart of a power-on configuration process in one embodiment;

4 is a schematic diagram of optical port state monitoring in one embodiment;

FIG. 5 is a schematic diagram of state monitoring of chain establishment in one embodiment;

6 is a schematic diagram of alarm detection state monitoring in one embodiment;

7 is a schematic diagram of power detection state monitoring in one embodiment;

8 is a schematic structural diagram of a power amplifier protection device in an embodiment;

9 is a flowchart of a power amplifier protection method in yet another embodiment;

FIG. 10 is a schematic structural diagram of a power amplifier protection device in yet another embodiment.

Detailed ways

The following describes in detail the embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, but not to be construed as a limitation on the present application.

It will be understood by those skilled in the art that the singular forms "a", "an", "the" and "the" as used herein can include the plural forms as well, unless expressly stated otherwise. It should be further understood that the word "comprising" used in this specification refers to the presence of the stated features, integers, steps, operations, elements and/or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof. It will be understood that when we refer to an element as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Furthermore, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. As used herein, the term "and/or" includes all or any element and all combination of one or more of the associated listed items.

It will be understood by those of ordinary skill in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It should also be understood that terms, such as those defined in a general dictionary, should be understood to have meanings consistent with their meanings in the context of the prior art and, unless specifically defined as herein, should not be interpreted in idealistic or overly formal meaning to explain.

As shown in FIG. 1 , FIG. 1 is an implementation environment diagram of a power amplifier protection method provided in an embodiment. In this implementation environment, a programmable logic device 10 , a monitoring processor 20 , a transceiver 30 , and a power amplifier circuit (power amplifier) are included. circuit) 40, wherein the power amplifier circuit includes a pre-push stage 41, a push stage 42 and a final stage 43.

The programmable logic device 10 is a general-purpose integrated circuit, and its logic function is determined according to user programming of the device. For example, the programmable logic device 10 may be a field programmable gate array FPGA (Field Programmable Gate Array), or other programmable logic array devices PLA (Programmable Logic Array), programmable array logic PAL (Programmable Array Logic), general-purpose array logic GAL (Generic Array Logic), Field Programmable Gate Array FPGA (Field Programmable Gate Array), Programmable Logic Device EPLD (Erase Programmable Logic Device), Programmable Large Scale Integration Device ispLSI, etc.

The supervisory processor 20 may be an ARM processor, but is not limited thereto. The transceiver 30 is an ADC/DAC (Analog to Digital Converter/Digital to Analog Converter) transceiver, and the power amplifier 40 is a power amplifier. The programmable logic device 10, the monitoring processor 20, and the transceiver 30 are connected in pairs. A communication link is established between the programmable logic device 10 and the transceiver 30. The transceiver 30 is connected to the power amplifier 40. The programmable logic device 10 And the monitoring processor 20 can control the power amplifier 40 through the transceiver 30 .

In one embodiment, as shown in FIG. 2 , FIG. 2 is a flowchart of a power amplifier protection method in an embodiment. In this embodiment, a power amplifier protection method is proposed, and the power amplifier protection method can be applied in the above-mentioned implementation environment , which can include the following steps:

Step S210: The programmable logic device monitors the running state of the communication device.

The operational state to be monitored may be a source of factors that may characterize the generation of spurs within the communication device. Communication equipment is affected by factors such as interface timing, plugging and unplugging optical fibers, power-on and power-off, temperature changes, etc., and large spurious phenomena of signals will occur in a very short period of time. The stray signal is not detected and exceeds the tolerance range of the power amplifier circuit. If the power amplifier circuit is not protected in time, it will cause the power amplifier circuit to burn out.

The monitored operating status may include one or more of the optical port status, link establishment status, power status, alarm detection status, and power detection status.

Step S220: when the operating state is abnormal, the programmable logic device turns off the baseband signal and turns off the enabling of the pre-push stage of the power amplifier in the communication device, and the baseband signal is output to the transceiver of the communication device baseband signal.

The baseband signal is the baseband signal output to the transceiver of the communication device. When the baseband signal is turned off, the DAC in the transceiver can be turned off to input the signal to the power amplifier circuit.

The above-mentioned power amplifier protection method, when the operating state is abnormal, indicates that stray phenomena are likely to occur in the communication equipment. At this time, the baseband signal is turned off through the programmable logic device in time, and the pre-propulsion stage of the power amplifier is turned off to stop the input power amplifier circuit. The power of the power amplifier can prevent the power amplifier circuit from being burned, and achieve the effect of protecting the power amplifier circuit; and the response time of the programmable logic device is short, so the operation status of the communication equipment can be monitored very quickly, so the programmable logic device can be generated for a very short time. It can respond to the large spurs, or prevent the impending large spurs, turn off the baseband signal output to the transceiver in time, and turn off the enabling of the pre-propulsion stage of the power amplifier, which can quickly avoid large spurs and protect the power amplifier in a timely and effective manner. circuit.

In one embodiment, after the step of monitoring the operating state of the communication device by the programmable logic device in step S210, the method further includes:

Step S230: when the operating state is abnormal, the monitoring processor turns off the boost stage and the final gate voltage of the power amplifier.

When the operating state is abnormal, the monitoring processor closes the gate voltage of the booster stage and the last stage of the power amplifier, which can prevent the signal isolation of the pre-push stage from being insufficient, thereby preventing the signal from radiating to the booster stage and the last stage of the power amplifier, and completely turning off the power amplifier.

In the above-mentioned power amplifier protection method, when the running state is abnormal, the power amplifier can be protected more thoroughly by monitoring the processor to turn off the gate voltage of the push stage and the last stage of the power amplifier.

In one embodiment, the operating state includes an optical port state;

The step of monitoring the operating state of the communication device by the programmable logic device in step S210 includes:

Step S211a: acquiring a plurality of optical indication information of the optical signal of the communication device;

Step S212a: when any one of the optical indication information indicates abnormality, it is determined that the state of the optical port is abnormal;

Step S213a: when the multiple indication information of the optical signal belongs to the normal range, it is determined that the state of the optical port is normal.

The power amplifier protection in the optical port state can mainly monitor the optical indication information such as optical presence, optical synchronization, optical loss, superframe indication, error indication, etc., so that the optical indication information can detect abnormality. If any light indication information indicates an abnormality, the programmable logic device will turn off the baseband signal and turn off the enabling of the pre-push stage of the power amplifier in the communication device, and/or the monitoring processor will turn off the power amplifier's push stage and final gate voltage .

The above-mentioned power amplifier protection method can determine that the state of the optical port is abnormal when any optical indication information indicates abnormality, so that the programmable logic device can turn off the baseband signal and turn off the enabling of the pre-push stage of the power amplifier, and can further make the monitoring processor turn off the power amplifier. The gate voltage of the booster stage and the last stage is used to protect the power amplifier against the large stray that may occur due to abnormal optical ports.

Further, if the multiple indication information of the optical signal belongs to the normal range and can be kept without abnormality within the second time period, it is determined that the state of the optical port is normal, and the power amplifier pre-push stage can be enabled. For example, the second time period may be 4.36s.

In one embodiment, the operating state includes a link establishment state of a communication link between the programmable logic device and the transceiver.

Taking the connection between FPGA and ADC/DAC transceiver as an example, JESD204B can be established between FPGA and ADC/DAC transceiver. JESD204B is a serial digital link between FPGA and ADC/DAC transceiver. The link establishment state of the communication link between the programmable logic device and the transceiver may be the link establishment state of JESD204B between the FPGA and the ADC/DAC transceiver.

The step of monitoring the operating state of the communication device by the programmable logic device in step S210 includes:

Step S211b: Monitor the synchronous port status, the valid port status, and the ready port status, where the ready port status is used to indicate whether the link is ready for information transmission and reception.

The programmable logic device can receive (RX) sync port status, receive (RX) valid port status, feedback (FB) sync port status, feedback (FB) valid port status, transmit (TX) sync port status and (TX)ready port status. Taking a high level to represent a normal level signal as an example, the sync port state can be the sync port state, and the sync port state is pulled high to represent synchronization; the valid port state is the valid port state, and the valid port state is pulled high to indicate that the data is valid; the Ready port state is pulled high. The high representative is ready to send and receive information.

Step S212b: when the level signals corresponding to the synchronous port state, the valid port state and the ready port state are all normal level signals, it is determined that the link establishment state is normal; otherwise, it is determined that the link establishment state is abnormal.

When the level signals corresponding to the synchronous port state, the valid port state, and the ready port state are all normal level signals, the link establishment state is normal. When any one of the synchronous port status, the valid port status, and the ready port status is in an abnormal level signal, the link establishment status is abnormal.

Take a high level representing a normal level signal as an example, that is, the port state being pulled high represents a normal level signal. When the status of the sync port is pulled high, the status of the valid port is pulled high, and the status of the Ready port is pulled high, the link establishment status is normal. When any one of the synchronous port state, the valid port state and the ready port state is pulled low, the link establishment state is abnormal. At this time, the programmable logic device turns off the baseband signal and turns off the pre-push stage of the power amplifier in the communication device. is enabled, the baseband signal is the baseband signal output to the transceiver of the communication device, and further, the monitoring processor can also turn off the booster stage and the last stage gate voltage of the power amplifier.

In one embodiment, the operating state includes a power state.

The step of detecting the operating state of the communication device by the programmable logic device in step S210 includes:

Step S211c: When monitoring that the signal output by the comparison circuit belongs to a power abnormality alarm indication signal, determine that the power supply state is abnormal, wherein the comparison circuit is configured to output the power supply abnormality alarm indication signal when the power supply voltage is not within a predetermined range.

When the power supply voltage is lower than the first preset value, the comparison circuit may output the power abnormality alarm indication signal. And/or, when the power supply voltage is higher than the second preset value, the comparison circuit may also output the power supply abnormality alarm indication signal.

Taking power failure as an example, on the one hand, the leakage voltage of the power amplifier tube gradually decreases, which will lead to a decrease in reliability at lower voltages; on the other hand, the power supply is converted from the voltage inside the power supply or on the digital board, and when it drops to a certain voltage It will cause the digital chip to work abnormally, resulting in spurious. Therefore, the input signal of the power amplifier can be cut off before the voltage of the power amplifier is reduced to a tolerable level and the digital board is abnormal, so as to achieve a protective effect. For example, when the power supply voltage of the booster stage and the final stage drain of a normal power amplifier is 28V, when the power supply voltage is lower than 24V, the power supply is abnormal, and a power supply abnormality alarm indication signal is output to the programmable logic device through the comparison circuit.

In one embodiment, before the step of detecting the operating state of the communication device by the programmable logic device in step S210, the method further includes:

Step S200: Before the power supply is normally turned on, continuously monitor whether the power supply voltage is greater than a predetermined value within a first time period, and if so, determine that the state of the power supply is normal, wherein the first time period is far greater than the possible Minimum response time for programming logic devices.

The above-mentioned power amplifier protection method detects that the power supply is normal for a continuous period of time, ensures that the power supply remains stable, and avoids the power supply being normal and facing an abnormal power supply immediately after the power amplifier is turned on, thereby preventing the power amplifier from being damaged. For example, if the first time period is greater than or equal to 5 seconds, and the power supply voltage is greater than the predetermined value for 5 seconds, it is determined that the power supply state is normal.

In one embodiment, the operational state includes an alarm detection state.

The step of monitoring the running state of the communication device by the programmable logic device in step S210 includes:

Step S211d: The programmable logic device monitors the variables of PLL clock lock, optical synchronization and ring network alarm, and receives information of the synthesized alarm of the transceiver from the monitoring processor.

The information of the synthesized alarms includes link alarms, local oscillator alarms, and clock chip alarms. The link alarms may be JESD alarms.

Step S212d: when any one of the variables indicates an abnormality or when the information of the synthesized alarm indicates an abnormality, it is determined that the alarm detection state is abnormal.

After determining that the alarm detection state is abnormal, the programmable logic device turns off the baseband signal and turns off the enabling of the pre-push stage of the power amplifier in the communication device, the baseband signal is the baseband signal output to the transceiver of the communication device, and further The booster and final gate voltages of the power amplifier can also be turned off by the supervisory processor.

Step S213d: when the variables all belong to the normal range and the information of the synthesized alarm indicates normal, it is determined that the alarm detection state is normal.

According to the characteristics of the power amplifier, to ensure the long-term stable and normal operation of the power amplifier, the input and output conditions should be within the reasonable working range of the power amplifier. In terms of limiting the input power of the input power amplifier, the AGC (Automatic Generation Control, automatic gain control) module limits the input power of the ADC module from being too large; the PLAGC (limit maximum power output) module limits the downlink average power, and the power protection limits the average and peak power.

In one embodiment, the operating state includes a power detection state.

The step of monitoring the operating state of the communication device by the programmable logic device in step S210 includes:

Step S211e: The programmable logic device counts the forward average power according to the first statistical point, and calculates the current forward peak power according to the second statistical point.

For example, the statistical duration of forward mean power T1=N1*(1/fclk), where N1 is the first statistical point, N1=2048 (N1 can also be parameterized, and can take values 5us, 10us, 20us), 1 /fclk is the clock cycle. The statistical duration of the forward mean power T2=N2*(1/fclk), where N2 is the second statistical point, and N2=16 (N2 can also be parameterized, and can take values of 8, 16, and 32).

Step S212e: when the forward average power is greater than the first preset threshold or the current forward peak power is greater than the second preset threshold, determine that the power detection state is abnormal; otherwise, determine that the power detection state is normal.

Mean power protection: Compare the statistical forward mean power with the mean threshold. If the mean power is greater than the mean threshold, the baseband signal is turned off, otherwise the baseband signal is turned on.

Peak power protection: Compare the statistical forward peak power with the peak threshold, and turn off the baseband signal if the peak power is greater than the peak threshold. In addition, the forward peak power at time t1 is greater than the peak threshold, if the peak power is always less than the peak threshold in the T period (T>=T2) thereafter, the baseband signal is turned on, otherwise the baseband signal is turned off.

In the above power amplifier protection method, the mean power protection can continuously monitor the overall power to protect the power amplifier from excessive power, and the peak power protection can monitor the power at each moment to avoid excessive instantaneous power to protect the power amplifier.

In one embodiment, after the step of monitoring the operating state of the communication device by the programmable logic device in step S210, the method further includes:

Step S241 : the monitoring processor reads the running state monitored by the programmable logic device.

The monitoring processor reads the operating state through the programmable logic device, so that the monitoring processor shuts down the gate voltage of the power amplifier and the final stage according to the operating state.

In one embodiment, after the step of monitoring the operating state of the communication device by the programmable logic device in step S210, the method further includes:

Step S242: the monitoring processor controls the operating state of the register latch in the programmable logic device according to the operating state.

The supervisory processor can set the operational state of the register latches in the programmable logic device.

For example, after the power state, the optical port state and the link establishment state are all normal, the monitoring processor can clear the abnormal latch state of the programmable logic device.

In one embodiment, before the step of monitoring the operating state of the communication device by the programmable logic device in step S210, the method further includes:

Step S201: Power-on configuration of the programmable logic device is performed by a monitoring processor.

During the initial power-on configuration process, monitor the processor off pre-push stage enable and power amplifier gate voltage at all levels. Wait for the power-on configuration to end, and monitor the processor to read the power status of the power amplifier. If the power supply of the power amplifier is detected abnormally, continue to detect the power supply of the power amplifier. If the power supply of the power amplifier is always abnormal or the power supply returns to normal and continues to detect abnormality for 5s, the power supply of the power amplifier is faulty and the power amplifier is turned off. If the power supply of the power amplifier is normal, it is judged whether the link establishment status and the optical port status are normal. If they are normal, the abnormal latch status of the register is cleared, the pre-push stage of the power amplifier is enabled, the grid voltage of the power amplifier is turned on, and the power amplifier is turned on. The operation state controls the operation state of the register latch in the programmable logic device; if the link establishment state or the optical port state is abnormal, the power amplifier is in the off state, and the link establishment state and the optical port protection state are continuously inquired.

The basic principle of turning off and turning on the power amplifier is fast turning off and slow turning on. "Quick shutdown" means that when the power supply is abnormal, the optical port is abnormal, and the link is abnormal, the programmable logic device immediately turns off the power amplifier pre-push stage and enables, and the monitoring processor queries the running status to turn off the power amplifier pre-push stage gate voltage. The monitoring processor can also inquire about the power status, optical port status, and link establishment status, and continue to traverse the alarm information of other systems. After confirming that all the alarm information meets the normal conditions for enabling the power amplifier, the programmable logic device clears the power amplifier enable status. , the programmable logic device turns on the power amplifier enable and the monitoring processor turns on the power amplifier gate voltage. "Slow open" means that after the power amplifier power supply is abnormal, if the power amplifier power supply remains normal within 5s, the programmable logic device will turn on the pre-push stage enable, and the monitoring processor will turn on the power amplifier gate voltage.

In one application example, the programmable logic device is powered on and configured by a supervisory processor. The initial power-on configuration process is shown in FIG. 3 . FIG. 3 is a flowchart of the power-on configuration process in one embodiment. Wait for the power-on configuration to end, and monitor the processor to read the power status of the power amplifier. If the power supply of the power amplifier is detected to be abnormal, continue to detect the power supply of the power amplifier. If the power supply of the power amplifier is always abnormal or an abnormality occurs within 5s after the power supply returns to normal, the power supply of the power amplifier is faulty and the power amplifier is turned off. If the power supply of the power amplifier is normal, judge whether the link establishment status and optical port status are normal. If they are normal, the abnormal latch status of the register is cleared, the power amplifier pre-push stage is enabled, the power amplifier grid voltage is turned on, and the power amplifier is turned on; if the link establishment status or the optical port status If the status is abnormal, the power amplifier is turned off. Continue to query the link establishment status and optical port protection status.

The programmable logic device monitors the operational status of the communication equipment. The operational state to be monitored may be a source of factors that may characterize the generation of spurs within the communication device. Communication equipment is affected by factors such as interface timing, plugging and unplugging optical fibers, power-on and power-off, temperature changes, etc., and large spurious phenomena of signals will occur in a very short period of time. The stray signal is not detected and exceeds the tolerance range of the power amplifier circuit. If the power amplifier circuit is not protected in time, it will cause the power amplifier circuit to burn out. The monitored operating status may include one or more of the optical port status, link establishment status, power status, alarm detection status, and power detection status.

When monitoring the state of the optical port, obtain a plurality of optical indication information of the optical signal of the communication device; when any one of the optical indication information indicates abnormality, it is determined that the state of the optical port is abnormal; when the plurality of indication information of the optical signal are all abnormal When it is within the normal range, it is determined that the optical port is in a normal state. As shown in FIG. 4, FIG. 4 is a schematic diagram of optical port state monitoring in an embodiment. The power amplifier protection in the optical port state can mainly provide optical indications such as optical presence, optical synchronization, optical loss, superframe indication, and bit error indication. information is monitored, whereby light indicating information can detect anomalies.

When monitoring the link establishment status, monitor the synchronous port status, the valid port status and the ready port status, wherein the ready port status is used to indicate whether the link is ready for information sending and receiving; as shown in FIG. 5 , FIG. 5 is a The schematic diagram of link establishment status monitoring in the embodiment, when the level signals corresponding to the synchronous port status, the active port status and the ready port status are all at normal level signals, it is determined that the link establishment status is normal; otherwise, it is determined that the link establishment status is normal. Abnormal status. The programmable logic device can control the received synchronization port status (RX_sync), the received valid port status (RX_valid), the feedback synchronization port status (FB_sync), the feedback valid port status (FB_valid), and the transmitted synchronization port status (TX_sync). and the ready port status for transmit (TX_ready). Taking the high level to represent the normal level signal as an example, the synchronization port state can be the sync port state, the synchronization port state is pulled high to represent synchronization; the valid port state is respectively the valid port state, and the valid port state is pulled high to indicate that the data is valid; Ready port state Pulling high indicates that the information is ready to be sent and received.

When monitoring the power supply state, when it is detected that the signal output by the comparison circuit belongs to the power supply abnormality alarm indication signal, it is determined that the power supply state is abnormal. Before the power supply is normally turned on, continuously monitor whether the power supply voltage is greater than a predetermined value within a first time period, and if so, determine that the power supply state is normal, wherein the first time period is far greater than the programmable logic device. Minimum response time. For example, if the first time period is greater than or equal to 5 seconds, and the power supply voltage is greater than the predetermined value for 5 seconds, it is determined that the power supply state is normal. The normal power supply is monitored for a continuous period of time, to ensure that the power supply remains stable, and to avoid the instantaneous power supply abnormality after the power supply is normal and the power amplifier is turned on, so as to avoid damage to the power amplifier.

When monitoring the alarm detection state, the programmable logic device monitors the variables of PLL clock lock, optical synchronization and ring network alarm, and receives the synthesized alarm information of the transceiver from the monitoring processor. The information of the synthesized alarm includes link alarm and local oscillator alarm. , the clock chip alarm, the link alarm can be a JESD alarm; as shown in FIG. 6, FIG. 6 is a schematic diagram of alarm detection state monitoring in an embodiment, when any one of the variables indicates abnormality or the information of the synthesized alarm indicates When abnormal, it is determined that the alarm detection state is abnormal; when the variables all belong to a normal range and the information of the synthesized alarm indicates normal, it is determined that the alarm detection state is normal.

When detecting the power detection state, the programmable logic device counts the forward average power according to the first statistical point, and calculates the current forward peak power according to the second statistical point; as shown in FIG. The schematic diagram of power detection state monitoring, when the forward average power is greater than the first preset threshold or the current forward peak power is greater than the second preset threshold, it is determined that the power detection state is abnormal; otherwise, the power detection state is determined to be normal.

Mean power protection: Compare the statistical forward mean power with the mean threshold. If the mean power is greater than the mean threshold, the baseband signal is turned off, otherwise the baseband signal is turned on. The statistical duration of the forward mean power T1=N1*(1/fclk), where N1 is the first statistical point, N1=2048 (N1 can also be parameterized, and the values can be 5us, 10us, 20us), 1/fclk is the clock cycle.

Peak power protection: Compare the statistical forward peak power with the peak threshold, and turn off the baseband signal if the peak power is greater than the peak threshold. The statistical duration of the forward peak power T2=N2*(1/fclk), where N2 is the second statistical point number, and N2=16 (N2 can also be parameterized, and can take values of 8, 16, and 32). In addition, the forward peak power at time t1 is greater than the peak threshold, if the peak power is always less than the peak threshold in the T period (T>=T2) thereafter, the baseband signal is turned on, otherwise the baseband signal is turned off.

When the running state is abnormal, the programmable logic device turns off the baseband signal and turns off the enabling of the pre-push stage of the power amplifier in the communication device, where the baseband signal is the baseband signal output to the transceiver of the communication device . The baseband signal is the baseband signal output to the transceiver of the communication device. When the baseband signal is turned off, the DAC in the transceiver can be turned off to input the signal to the power amplifier circuit.

The monitoring processor reads the operating state monitored by the programmable logic device. When the operating state is abnormal, the monitoring processor turns off the gate voltages of the booster stage and the last stage of the power amplifier. When the operating state is abnormal, the monitoring processor closes the gate voltage of the booster stage and the last stage of the power amplifier, which can prevent the signal isolation of the pre-push stage from being insufficient, thereby preventing the signal from radiating to the booster stage and the last stage of the power amplifier, and completely turning off the power amplifier.

The above-mentioned power amplifier protection method, when the operating state is abnormal, indicates that stray phenomena are likely to occur in the communication equipment. At this time, the baseband signal is turned off through the programmable logic device in time, and the pre-propulsion stage of the power amplifier is turned off to stop the input power amplifier circuit. The power of the power amplifier can prevent the power amplifier circuit from being burned, and achieve the effect of protecting the power amplifier circuit; and the response time of the programmable logic device is short, so the operation status of the communication equipment can be monitored very quickly, so the programmable logic device can be generated for a very short time. It can respond to the large spurs, or prevent the impending large spurs, turn off the baseband signal output to the transceiver in time, and turn off the enabling of the pre-propulsion stage of the power amplifier, which can quickly avoid large spurs and protect the power amplifier in a timely and effective manner. circuit. And when the running state is abnormal, the power amplifier can be further protected by monitoring the processor to turn off the gate voltage of the boost stage and the last stage of the power amplifier.

In one embodiment, as shown in FIG. 8 , which is a schematic structural diagram of a power amplifier protection device in an embodiment, this embodiment provides a power amplifier protection device, which can be applied to the implementation environment described in FIG. 1 . In particular, it may include a monitoring module 310 and a protection module 320, wherein:

The monitoring module 310 is used for the programmable logic device to monitor the running state of the communication device.

The operational state to be monitored may be a source of factors that may characterize the generation of spurs within the communication device. Communication equipment is affected by factors such as interface timing, plugging and unplugging optical fibers, power-on and power-off, temperature changes, etc., and large spurious phenomena of signals will occur in a very short period of time. The stray signal is not detected and exceeds the tolerance range of the power amplifier circuit. If the power amplifier circuit is not protected in time, it will cause the power amplifier circuit to burn out.

The monitored operating status may include one or more of the optical port status, link establishment status, power status, alarm detection status, and power detection status.

The protection module 320 is configured to, when the running state is abnormal, the programmable logic device to turn off the baseband signal output to the transceiver of the communication device and to turn off the enabling of the pre-push stage of the power amplifier in the communication device.

The baseband signal is the baseband signal output to the transceiver of the communication device. When the baseband signal is turned off, the DAC in the transceiver can be turned off to input the signal to the power amplifier circuit.

When the above-mentioned power amplifier protection device is in an abnormal operating state, it indicates that stray phenomena are likely to occur in the communication equipment. At this time, the baseband signal is turned off through the programmable logic device in time, and the pre-propulsion stage of the power amplifier is turned off to stop the input power amplifier circuit. The power of the power amplifier can prevent the power amplifier circuit from being burned, and achieve the effect of protecting the power amplifier circuit; and the response time of the programmable logic device is short, so the operation status of the communication equipment can be monitored very quickly, so the programmable logic device can be generated for a very short time. It can respond to the large spurs, or prevent the impending large spurs, turn off the baseband signal output to the transceiver in time, and turn off the enabling of the pre-propulsion stage of the power amplifier, which can quickly avoid large spurs and protect the power amplifier in a timely and effective manner. circuit.

In one embodiment, the protection module is further configured to monitor the processor to turn off the gate voltage of the boost stage and the final stage of the power amplifier when the operating state is abnormal.

When the operating state is abnormal, the monitoring processor closes the gate voltage of the booster stage and the last stage of the power amplifier, which can prevent the signal isolation of the pre-push stage from being insufficient, thereby preventing the signal from radiating to the booster stage and the last stage of the power amplifier, and completely turning off the power amplifier.

In the above-mentioned power amplifier protection device, when the operating state is abnormal, the power amplifier can be further protected by monitoring the processor to turn off the gate voltage of the push stage and the last stage of the power amplifier.

For specific limitations on the power amplifier protection device, reference may be made to the limitations on the power amplifier protection method above, which will not be repeated here. Each module in the above-mentioned power amplifier protection device may be implemented in whole or in part by software, hardware and combinations thereof. The above modules can be embedded in or independent of the processor in the computer device in the form of hardware, or stored in the memory in the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, implements the steps of the power amplifier protection method according to any of the foregoing embodiments.

In one embodiment, as shown in FIG. 9 , which is a flowchart of a power amplifier protection method in another embodiment, a power amplifier protection method is proposed in this embodiment, and the power amplifier protection method can be applied to the above-mentioned implementation environment , which may include the following steps:

Step S410: The programmable logic device monitors whether the power state remains normal within a second time period, wherein the second time period is far greater than the shortest response time of the programmable logic device.

The second time period is far longer than the response time of the monitoring device, so the monitoring device can perform multiple monitoring in the second time period. When the second time period is far greater than the shortest response time of the programmable logic device, the programmable logic device performs continuous monitoring for a longer time during the second time period.

Step S420 : when the power state remains normal within the second time period, the programmable logic device turns on the pre-push stage enable, and the monitoring processor turns on the gate voltage of the push stage and the final stage to turn on the power amplifier.

If the power state remains normal for the second time period, it can indicate that the power supply is stable.

The above-mentioned power amplifier protection method monitors that the power supply is normal for a continuous period of time to ensure that the power supply remains stable, and avoids the instantaneous power supply abnormality after turning on the power amplifier after the power supply is normal. The processor turns on the booster and final gate voltages to protect the power amplifier when it is turned on.

For example, the second time period may be greater than or equal to 5 seconds, the supply voltage remains normal for 5 seconds, the pre-push stage is enabled by the programmable logic device, and the monitoring processor turns on the push and final stages Grid voltage, turn on the power amplifier.

In one embodiment, the power amplifier protection method further includes:

Step S431 : when the power state remains normal within the second time period, the monitoring processor clears the operating state of the register latch in the programmable logic device.

The supervisory processor can set the operational state of the register latches in the programmable logic device. When the power state continues to be normal within the second time period, the monitoring processor can clear the abnormal latch state in the register, so as to turn on the power amplifier in a non-abnormal operating state subsequently.

In one embodiment, the power amplifier protection method further includes:

Step S432: when the power supply state is abnormal in the second time period, keep the operation state of the register latch in the programmable logic device, keep the pre-push stage enable of the power amplifier invalid, and keep the power amplifier The booster and final gate voltages are turned off.

When there is an abnormality in the power state, the operation state latched in the register is retained, the pre-push stage enablement of the power amplifier is kept invalid, and the gate voltage of the push stage and the final stage of the power amplifier are kept off, and the power amplifier is turned off at this time. , to protect the amplifier.

Among them, the monitoring processor turns off the gate voltage of the booster stage and the last stage of the power amplifier, which can prevent the signal isolation of the pre-push stage from being insufficient, thereby preventing the signal from radiating to the booster stage and the last stage of the power amplifier. At this time, the power amplifier can be completely turned off.

In one embodiment, after the power state remains normal within the second time period, the method further includes:

Step S440: The programmable logic device monitors whether the optical port status is normal, and monitors whether the link establishment status is normal; the link establishment status is the status of the communication link between the programmable logic device and the transceiver.

The link establishment state is the state of the communication link between the programmable logic device and the transceiver. Taking the connection between FPGA and ADC/DAC transceiver as an example, JESD204B can be established between FPGA and ADC/DAC transceiver. JESD204B is a serial digital link between FPGA and ADC/DAC transceiver. The link establishment state of the communication link between the programmable logic device and the transceiver may be the link establishment state of JESD204B between the FPGA and the ADC/DAC transceiver.

Step S450 : when the optical port state and the link establishment state are normal, the programmable logic device turns on the pre-push stage enable, and the monitoring processor turns on the push stage and the last stage gate voltage to turn on the power amplifier.

Communication equipment is affected by factors such as interface timing, plugging and unplugging optical fibers, power-on and power-off, temperature changes, etc., and large spurious phenomena of signals will occur in a very short period of time. The stray signal is not detected and exceeds the tolerance range of the power amplifier circuit. If the power amplifier circuit is not protected in time, it will cause the power amplifier circuit to burn out. In this embodiment, after the power state is normal, the power amplifier needs to be turned on only after the optical port state and the link establishment state are normal, so as to avoid large signal stray phenomenon when the power amplifier is turned on, so as to protect the power amplifier.

When the state of the optical port or the state of the link establishment is abnormal, it indicates that the operating state of the communication device is abnormal. The enabling of the pre-push stage of the power amplifier is invalid, and the gate voltages of the push stage and the final stage of the power amplifier are kept off, and the power amplifier is kept off, so as to protect the power amplifier.

Specifically, the step of monitoring whether the state of the optical port is normal in step S440 includes:

Step S441: Acquire a plurality of optical indication information of the optical signal in the communication device;

Step S442: when any one of the optical indication information indicates abnormality, it is determined that the state of the optical port is abnormal;

Step S443: When the multiple indication information of the optical signal all belong to the normal range, it is determined that the state of the optical port is normal.

The power amplifier protection in the optical port state can mainly monitor the optical indication information such as optical presence, optical synchronization, optical loss, superframe indication, error indication, etc., so that the optical indication information can detect abnormality. If any light indication information indicates an abnormality, the programmable logic device will turn off the baseband signal and turn off the enabling of the pre-push stage of the power amplifier in the communication device, and/or the monitoring processor will turn off the power amplifier's push stage and final gate voltage .

Specifically, the step of monitoring whether the link establishment status is normal described in step S440 includes:

Step S444: Monitor the synchronous port status, the valid port status, and the ready port status, where the ready port status is used to indicate whether the link is ready for information sending and receiving.

The programmable logic device can receive (RX) sync port status, receive (RX) valid port status, feedback (FB) sync port status, feedback (FB) valid port status, transmit (TX) sync port status and (TX)ready port status. Taking a high level to represent a normal level signal as an example, the sync port state can be the sync port state, and the sync port state is pulled high to represent synchronization; the valid port state is the valid port state, and the valid port state is pulled high to indicate that the data is valid; the Ready port state is pulled high. The high representative is ready to send and receive information.

Step S445: When the level signals corresponding to the synchronous port state, the valid port state, and the ready port state are all normal level signals, it is determined that the link establishment state is normal; otherwise, the link establishment state is determined to be abnormal.

When the level signals corresponding to the synchronous port state, the valid port state, and the ready port state are all normal level signals, the link establishment state is normal. When any one of the synchronous port status, the valid port status, and the ready port status is in an abnormal level signal, the link establishment status is abnormal.

Take a high level representing a normal level signal as an example, that is, the port state being pulled high represents a normal level signal. When the synchronization port status is pulled high, the valid port status is pulled high, and the ready port status is pulled high, the link establishment status is normal. When any one of the synchronous port status, the valid port status, and the ready port status is pulled low, the link establishment status is abnormal.

In one embodiment, the step of monitoring whether the power state remains normal within the second time period in step S410 includes:

When the comparison circuit detects that the power supply voltage is within the predetermined range, continuously monitor whether the power supply voltage is within the predetermined range within the second time period, and if so, determine that the power supply state is normal, wherein all the The comparison circuit is used for judging whether the supply voltage is within the predetermined range.

For example, when the power supply voltage is lower than the second preset value within the second time period, it is determined that the power supply state is abnormal. And/or, when the power supply voltage is excessively higher than the second preset value within the second time period, it is determined that the power supply state is abnormal.

In one embodiment, before the step S410, the programmable logic device monitoring whether the power supply state remains normal within the second time period further includes:

Step S450: the monitoring processor turns off the boost stage and the gate voltage of the final stage of the power amplifier; and the programmable logic device turns off the enabling of the pre-drive stage of the power amplifier.

During the power-on process, the signal is abnormal and the abnormality cannot be recovered. When the signal is abnormal, the power amplifier will be burned. Before turning on the power amplifier, turn off the pre-propulsion stage enable and the gate voltage of the power amplifier to protect the power amplifier.

In one embodiment, after the step S450, the monitoring processor turns off the push stage and the final gate voltage of the power amplifier and the programmable logic device turns off the enabling of the pre-push stage of the power amplifier, further comprising:

Step S451: the monitoring processor loads the file containing the running configuration;

Step S452: Initialize the registers of the programmable logic device according to the running configuration.

After the pre-propulsion stage is enabled and the gate voltages of the power amplifier stages are turned off, the monitoring processor loads the file containing the running configuration, and initializes the registers of the programmable logic device according to the running configuration to perform an initial power-on configuration process.

After the power-on configuration is completed, the monitoring processor reads the power status of the power amplifier. If the power of the power amplifier is detected abnormal, continue to detect the power of the power amplifier. If the power of the power amplifier is always abnormal or the power supply returns to normal and continues to detect the abnormality for 5s, the power amplifier power failure will turn off the power amplifier. If the power supply of the power amplifier is normal, judge whether the link establishment status and the optical port status are normal. If the normal register is abnormal, the latch status is cleared, the power amplifier pre-push stage is enabled, and the power amplifier grid voltage is turned on to turn on the power amplifier; if the link establishment status and the optical port status are abnormal, The power amplifier is turned off. Continue to query the link establishment status and optical port status.

Among them, the power-on configuration mainly includes file loading, clock configuration, link (JESD) configuration and related test operations. After the loading of the monitoring processor is completed, the clock chip is configured, and the clock chip provides a clock for the programmable logic device, and the monitoring processor judges whether the programmable logic device is loaded successfully according to the pin level of the programmable logic device. After the loading is successful, reset the programmable logic device and initialize the relevant registers of the programmable logic device to ensure the normality of the signal.

In an embodiment, after the optical port state and the link establishment state are normal, the method further includes:

Step S461: Monitor the alarm information of PLL clock lock, optical synchronization and ring network alarm, and synthesized alarm of the transceiver.

The information of the synthesized alarms includes link alarms, local oscillator alarms, and clock chip alarms. The link alarms may be JESD alarms.

Step S462 : when the alarm information indicates normal, the programmable logic device enables the pre-push stage, and the monitoring processor turns on the push stage and the last stage gate voltage to turn on the power amplifier.

When the alarm information is normal, it means that the alarm detection state is normal. At this time, the programmable logic device can turn on the pre-push stage enable, and the monitoring processor can turn on the push stage and the last stage gate voltage to turn on the power amplifier.

When any one of the synthesized alarm information indicates abnormality, it is determined that the alarm detection state is abnormal, which indicates that the operating state of the communication equipment is abnormal at this time. In order to prevent the power amplifier from being burned, the programmable logic device can be reserved at this time. The operating state latched by the middle register keeps the enable of the pre-push stage of the power amplifier invalid, and the gate voltage of the push stage and the final stage of the power amplifier are kept off, and the power amplifier is kept off, so as to protect the power amplifier.

In one application example, this example will protect the amplifier during power-up configuration. As shown in FIG. 3 , FIG. 3 is a flowchart of a power amplifier protection method in a power-on configuration process in an embodiment. First, perform the initial power-on configuration process, and turn off the pre-push stage enable and power amplifier gate voltages. In the power-on configuration, the monitoring processor loads a file containing an operating configuration; initializes the registers of the programmable logic device according to the operating configuration, and establishes a link between the programmable logic device and the transceiver. Wherein, according to the synchronous port state, the valid port state and the ready port state, it is judged whether the link between the programmable logic device and the transceiver is successfully established, and after the link is established successfully, the clock that provides the link for the link is released. reference signal.

After the power-on configuration is complete, the programmable logic device monitors the power status. If it is detected that the power supply of the power amplifier is abnormal, continue to monitor the power supply of the power amplifier. If the power supply of the power amplifier is always abnormal or an abnormality occurs within 5s after the power supply returns to normal, the power supply of the power amplifier is faulty, and the operation state of the register latch in the programmable logic device is retained. The pre-push stage enablement of the power amplifier is disabled, and the push stage and the final stage gate voltage of the power amplifier are kept off to turn off the power amplifier.

If the power supply status remains normal within the second time period, the second time period is far greater than the shortest response time of the programmable logic device, that is, the power supply of the power amplifier is normal, continue to judge whether the link establishment status and the optical port status are normal. If it is normal, the abnormal latch state of the register is cleared, the pre-push stage of the power amplifier is enabled, the grid voltage of the power amplifier is turned on, and the power amplifier is turned on; if the link establishment state or the optical port status is abnormal, the power amplifier is in the off state, and the link establishment status and the optical port protection status are continuously inquired. .

Wherein, the monitoring of the power supply state can be performed by the comparison circuit to detect the power supply voltage. When the comparison circuit detects that the power supply voltage is within the predetermined range, it continuously monitors whether the power supply voltage is within the predetermined range within 5s, and if so, it is determined that the power supply state is normal, wherein the comparison circuit Used to determine whether the power supply voltage is within a predetermined range.

After the power amplifier is turned on, the programmable logic device can monitor the operating status of the communication equipment. The operational state to be monitored may be a source of factors that may characterize the generation of spurs within the communication device. Communication equipment is affected by factors such as interface timing, plugging and unplugging optical fibers, power-on and power-off, temperature changes, etc., and large spurious phenomena of signals will occur in a very short period of time. The stray signal is not detected and exceeds the tolerance range of the power amplifier circuit. If the power amplifier circuit is not protected in time, it will cause the power amplifier circuit to burn out. The monitored operating status may include one or more of the optical port status, link establishment status, power status, alarm detection status, and power detection status.

When monitoring the state of the optical port, obtain a plurality of optical indication information of the optical signal of the communication device; when any one of the optical indication information indicates abnormality, it is determined that the state of the optical port is abnormal; when the plurality of indication information of the optical signal are all abnormal When it is within the normal range, it is determined that the optical port is in a normal state. As shown in FIG. 4, FIG. 4 is a schematic diagram of optical port state monitoring in an embodiment. The power amplifier protection in the optical port state can mainly provide optical indications such as optical presence, optical synchronization, optical loss, superframe indication, and bit error indication. The information is monitored, and the optical indication information can detect whether the optical port is abnormal.

When monitoring the link establishment status, monitor the synchronous port status, the valid port status and the ready port status, wherein the ready port status is used to indicate whether the link is ready for information sending and receiving; as shown in FIG. 5 , FIG. 5 is a The schematic diagram of link establishment status monitoring in the embodiment, when the level signals corresponding to the synchronous port status, the active port status and the ready port status are all at normal level signals, it is determined that the link establishment status is normal; otherwise, it is determined that the link establishment status is normal. Abnormal status. The programmable logic device can control the received synchronization port status (RX_sync), the received valid port status (RX_valid), the feedback synchronization port status (FB_sync), the feedback valid port status (FB_valid), and the transmitted synchronization port status (TX_sync). and the ready port status for transmit (TX_ready). Taking the high level to represent the normal level signal as an example, the synchronization port state can be the sync port state, the synchronization port state is pulled high to represent synchronization; the valid port state is respectively the valid port state, and the valid port state is pulled high to indicate that the data is valid; Ready port state Pulling high indicates that the information is ready to be sent and received.

The programmable logic device monitors the variables of PLL clock lock, optical synchronization and ring network alarm, and receives the synthesized alarm information of the transceiver from the monitoring processor. The information of the synthesized alarm includes link alarm, local oscillator alarm, clock chip alarm, chain alarm The channel alarm may be a JESD alarm; as shown in FIG. 6 , which is a schematic diagram of alarm detection state monitoring in an embodiment, when any one of the variables indicates an abnormality or the information of the synthesized alarm indicates an abnormality, it is determined that the The alarm detection state is abnormal; when the variables all belong to the normal range and the information of the synthesized alarm indicates that the alarm detection state is normal, it is determined that the alarm detection state is normal.

After the power amplifier is turned on, if the power supply status, link establishment status, optical port status or alarm detection status is abnormal, the operation status of the register latch in the programmable logic device is retained, and the pre-push stage enablement of the power amplifier is kept invalid. and keeping the gate voltage of the power amplifier and the final stage closed; if the above states are normal, turn on the pre-push stage enable through the programmable logic device, and the monitoring processor turns on the gate voltage of the push stage and the final stage, to turn on the amplifier.

In one embodiment, as shown in FIG. 10 , which is a schematic structural diagram of a power amplifier protection device in another embodiment, this embodiment provides a power amplifier protection device, which may include a state monitoring module 510 and a power amplifier opening module 520 , wherein :

The state monitoring module 510 is used for the programmable logic device to monitor whether the power supply state remains normal within a second time period, wherein the second time period is far greater than the shortest response time of the programmable logic device.

The second time period is far longer than the response time of the monitoring device, so the monitoring device can perform multiple monitoring in the second time period. When the second time period is far greater than the shortest response time of the programmable logic device, the programmable logic device performs continuous monitoring for a longer time during the second time period.

A power amplifier turn-on module 520, configured to turn on the pre-push stage enable of the programmable logic device when the power state remains normal within the second time period, and monitor the processor to turn on the gate voltage of the push stage and the final stage, so as to turn on the power amplifier .

If the power state remains normal for the second time period, it can indicate that the power supply is stable.

The above-mentioned power amplifier protection device monitors that the power supply is normal for a continuous period of time to ensure that the power supply remains stable, and avoids the instantaneous power supply abnormality after turning on the power amplifier after the power supply is normal. The processor turns on the booster and final gate voltages to protect the power amplifier when it is turned on.

For example, the second time period may be greater than or equal to 5 seconds, the supply voltage remains normal for 5 seconds, the pre-push stage is enabled by the programmable logic device, and the monitoring processor turns on the push and final stages Grid voltage, turn on the power amplifier.

For specific limitations on the power amplifier protection device, reference may be made to the limitations on the power amplifier protection method above, which will not be repeated here. Each module in the above-mentioned power amplifier protection device may be implemented in whole or in part by software, hardware and combinations thereof. The above modules can be embedded in or independent of the processor in the computer device in the form of hardware, or stored in the memory in the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

It should be understood that although the various steps in the flowchart of the accompanying drawings are sequentially shown in the order indicated by the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless explicitly stated herein, the execution of these steps is not strictly limited to the order and may be performed in other orders. Moreover, at least a part of the steps in the flowchart of the accompanying drawings may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but may be executed at different times, and the execution sequence is also It does not have to be performed sequentially, but may be performed alternately or alternately with other steps or at least a portion of sub-steps or stages of other steps.

The above are only part of the embodiments of the present application. It should be pointed out that for those skilled in the art, without departing from the principles of the present application, several improvements and modifications can also be made. It should be regarded as the protection scope of this application.

Claims (10)

1. a power amplifier protection method, is characterized in that, comprises the steps: Before the power supply is normally turned on, when the continuously monitored supply voltage is greater than a predetermined value within a first time period, it is determined that the state of the power supply is normal; wherein the first time period is far greater than the shortest response of the programmable logic device time; The programmable logic device monitors the operation state of the communication equipment; the operation state includes the optical port state; When the running state is abnormal, the programmable logic device turns off the baseband signal and turns off the enabling of the pre-push stage of the power amplifier in the communication device, where the baseband signal is the baseband signal output to the transceiver of the communication device ; The monitoring processor reads the operating state monitored by the programmable logic device, and when the operating state is abnormal, the monitoring processor turns off the booster stage and the final gate voltage of the power amplifier; Wherein, the determination of the state of the optical port includes: when any one of the optical indication information of the optical signal of the communication device indicates abnormality, judging that the state of the optical port is abnormal; when multiple optical indication information of the optical signal of the communication device belongs to When the state of the optical port is normal and there is no abnormality within the second time period, it is determined that the state of the optical port is normal, and the enabling of the pre-push stage of the power amplifier is turned on. 2. The power amplifier protection method according to claim 1, wherein the operating state comprises a link establishment state of a communication link between the programmable logic device and the transceiver; The step of monitoring the operating state of the communication device by the programmable logic device includes: Monitoring synchronous port status, valid port status and ready port status, wherein the ready port status is used to indicate whether the link is ready for information sending and receiving; When the level signals corresponding to the synchronous port state, the valid port state and the ready port state are all normal level signals, it is determined that the link establishment state is normal; otherwise, it is determined that the link establishment state is abnormal. 3. The power amplifier protection method according to claim 1, wherein the operating state comprises a power state; The step of detecting the operating state of the communication device by the programmable logic device includes: When it is detected that the signal output by the comparison circuit belongs to the power abnormality alarm indication signal, it is determined that the power supply state is abnormal, wherein the comparison circuit is used for judging that the power supply voltage is not within the predetermined range to output the power supply abnormality alarm indication signal. 4. The power amplifier protection method according to claim 1, wherein the first time period is greater than or equal to 5 seconds. 5. The power amplifier protection method according to claim 1, wherein the operating state comprises an alarm detection state; The step of monitoring the operating state of the communication device by the programmable logic device includes: The programmable logic device monitors the variables of PLL clock lock, optical synchronization and ring network alarms, and receives information from the supervisory processor of the synthesized alarms of the transceiver; When any one of the variables indicates an abnormality or when the information of the synthesized alarm indicates an abnormality, it is determined that the alarm detection state is abnormal; When the variables all belong to the normal range and the information of the synthesized alarm indicates normal, it is determined that the alarm detection state is normal. 6. The power amplifier protection method according to claim 1, wherein the operating state comprises a power detection state; The step of monitoring the operating state of the communication device by the programmable logic device includes: The programmable logic device counts forward average power according to the first statistical point, and calculates the current forward peak power according to the second statistical point; When the forward average power is greater than the first preset threshold or the current forward peak power is greater than the second preset threshold, it is determined that the power detection state is abnormal; otherwise, the power detection state is determined to be normal. 7. The power amplifier protection method according to claim 1, characterized in that, after the step of monitoring the operation state of the communication device by the programmable logic device, further comprising: The monitoring processor reads the running state monitored by the programmable logic device; The monitoring processor controls the operating state of register latches in the programmable logic device according to the operating state. 8. The power amplifier protection method according to claim 1, wherein before the step of monitoring the operation state of the communication device by the programmable logic device, further comprising: The programmable logic device is powered on and configured by a supervisory processor. 9. A power amplifier protection device, comprising: The monitoring module is used to determine that the state of the power supply is normal when the continuous monitoring power supply voltage is greater than a predetermined value within a first period of time before the power supply is normally turned on; the programmable logic device monitors the operating state of the communication equipment; wherein, The first time period is far greater than the shortest response time of the programmable logic device; the operating state includes an optical port state; a protection module, used for turning off the baseband signal output to the transceiver of the communication device by the programmable logic device when the running state is abnormal, and turning off the enabling of the pre-push stage of the power amplifier in the communication device; the monitoring processor reads Take the operating state monitored by the programmable logic device, and when the operating state is abnormal, monitor the processor to turn off the push stage and the final gate voltage of the power amplifier; wherein, the determination of the state of the optical port includes: when the When any one of the optical indication information of the optical signal of the communication equipment indicates abnormality, it is determined that the state of the optical port is abnormal; when multiple optical indication information of the optical signal of the communication equipment belongs to the normal range and remains normal within the second time period, Then it is determined that the optical port is in a normal state, and the enabling of the pre-push stage of the power amplifier is turned on. 10 . A computer-readable storage medium on which a computer program is stored, wherein when the computer program is executed by a processor, the steps of the power amplifier protection method according to any one of claims 1 to 8 are implemented.

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