CN111444127B - Data external memory expansion interface - Google Patents
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- CN111444127B CN111444127B CN202010120836.0A CN202010120836A CN111444127B CN 111444127 B CN111444127 B CN 111444127B CN 202010120836 A CN202010120836 A CN 202010120836A CN 111444127 B CN111444127 B CN 111444127B
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- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
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Abstract
本发明公开了一种数据外存扩展接口，其中，MCU的数据线连接I/O扩展芯片的输入端；地址线连接第一译码器的输入端，译码器的输出端和MCU的控制线连接与门的输入端，与门的输出端连接延时的输入端，延时的输出端连接加法器的输入端，并连接存储器的控制线；第一译码器的输出端同时连接非门的输入端，非门的输出端连接加法器的复位端；加法器的输出端连接第二译码器，该译码器的输出端连接I/O扩展芯片的片选线，第一至第N‑1个I/O扩展芯片的输出端连接存储器的地址线，第N个I/O扩展芯片的输出端连接存储器的数据线；MCU的控制线与I/O扩展芯片的控制线相连。本发明突破了MCU的地址线限制，以及传统数据存储扩展方法的容量限制，满足了超大容量的实时存取需求。
The invention discloses a data external memory expansion interface, wherein a data line of an MCU is connected to an input end of an I/O expansion chip; an address line is connected to an input end of a first decoder, the output end of the decoder and the control of the MCU The line is connected to the input end of the AND gate, the output end of the AND gate is connected to the input end of the delay, the output end of the delay is connected to the input end of the adder, and is connected to the control line of the memory; the output end of the first decoder is connected to the non- The input end of the gate and the output end of the NOT gate are connected to the reset end of the adder; the output end of the adder is connected to the second decoder, and the output end of the decoder is connected to the chip select line of the I/O expansion chip. The output end of the N-1 I/O expansion chip is connected to the address line of the memory, and the output end of the Nth I/O expansion chip is connected to the data line of the memory; the control line of the MCU is connected to the control line of the I/O expansion chip . The invention breaks through the address line limitation of the MCU and the capacity limitation of the traditional data storage expansion method, and meets the real-time access requirement of super-large capacity.
Description
Technical Field
The invention relates to the technical field of storage, in particular to a data external storage expansion interface.
Background
With the increasing popularity of computer network communication, the construction of computer data storage capacity is more and more important. The number of address pins of a Micro Control Unit (MCU) limits the access capacity of the memory, and the use of external memory involves complicated protocols and drives. Therefore, how to further expand the memory of the MCU to meet the requirement of ultra-large capacity storage becomes a problem to be solved in the field of storage technology.
The existing MCU storage expansion methods are roughly divided into two types: firstly, the access capacity is expanded by the way of P1 and P3 pins of the single chip microcomputer, but the method is limited by the quantity of P1 and P3 ports, and the expanded capacity is very limited, for example, a common MCS51 single chip microcomputer can only expand 256 × 256 memories at most in a full decoding mode; but also occupies the pins of the I/O ports P1 and P3. Secondly, the access capacity is expanded in a serial port expansion mode, for example, serial port data is converted into parallel port data by using a serial parallel Chip 74LS164, and Chip Select (CS) pins of each memory are connected, so that expansion is realized. In addition, there are other ways to obtain more address space by using a sacrifice of a very small part of memory space as secondary decoding.
Therefore, the MCU storage expansion method in the prior art has the problems of limited expansion capacity, poor real-time performance, high expansion difficulty and high expansion cost.
Disclosure of Invention
The invention provides a data external memory expansion interface, which solves the problems that the expansion capacity is very limited or the real-time performance is poor, and the expansion difficulty and the cost are high due to the fact that the expansion of an existing MCU storage expansion method is realized through P1 and P3 pins of a single chip microcomputer or through a serial-parallel chip.
A data external memory expansion interface, comprising:
the system comprises a micro control unit, a first decoder, a second decoder, an adder, an AND gate, a NOT gate, a delayer, a data memory and two or more I/O expansion chips;
the data line of the micro control unit is connected with the data input end of each I/O expansion chip;
the address line of the micro control unit is connected with the input end of a first decoder, the output end of the first decoder and the control line of the micro control unit are connected with the input end of an AND gate, the output end of the AND gate is connected with the input end of a delayer, and the output end of the delayer is connected with the input end of an adder and is connected with the control line of a data memory;
the output end of the first decoder is also connected with the input end of a NOT gate, and the output end of the NOT gate is connected with the reset end of the adder;
the output end of the adder is connected with a second decoder, the output end of the second decoder is connected with a chip selection pin of each I/O expansion chip, the output ends of the I/O expansion chips 1 to N-1 are connected with an address pin of the data memory, and the output end of the I/O expansion chip N is connected with a data pin of the data memory;
and the control line of the micro control unit is also connected with the control line of each I/O expansion chip.
Further, in one implementation: the I/O expansion chip is a 74LS373 chip.
Further, in one implementation: the first decoder and the second decoder are both 74LS138 chips.
Further, in one implementation: the data memory is a read-only memory or a random access memory.
Further, in an implementation manner, the method for controlling the data external memory expansion interface includes the following steps:
step 101, a micro control unit writes data information into an I/O expansion chip with the same address;
step 102, after the micro control unit selects an address, counting the number of times of writing through the adder to obtain a count value, and selecting an I/O expansion chip corresponding to a decoded signal after the count value passes through a second decoder;
103, writing the data information into I/O expansion chips with the same number and the same writing sequence respectively according to the writing sequence as the address information of the data memory;
writing first written data information into a first I/O expansion chip, writing second written data information into a second I/O expansion chip until writing Nth written data information into an Nth I/O expansion chip, wherein the first to Nth written data information is the address of a storage unit in a selected data memory, the Nth written data information is the data information written into the storage unit in the data memory, and the data memory comprises address information and data information;
104, transmitting a control signal of the micro control unit to a data memory through a delay unit, and performing AND operation on the control signal of the micro control unit, gating of a second decoder and an Nth I/O expansion chip, wherein the control signal is connected to a control line of the data memory, and the data information is stored in a storage unit corresponding to address information in the data memory;
105, when the address line signal of the micro control unit does not select the I/O expansion chip, the signal of the first decoder is connected to the reset end of the adder through the NOT gate, the reset signal is transmitted to the adder to reset the adder, and the second decoder selects the first I/O expansion chip;
and 106, repeating the steps 101 to 105 when the micro control unit writes data into the data memory again.
According to the technical scheme, the embodiment of the invention provides the data external memory expansion interface. The data external memory expansion interface comprises: the system comprises a micro control unit, a first decoder, a second decoder, an adder, an AND gate, a NOT gate, a delayer, a data memory and two or more I/O expansion chips; the data line of the micro control unit is connected with the data input end of each I/O expansion chip; the address line of the micro control unit is connected with the input end of a first decoder, the output end of the first decoder and the control line of the micro control unit are connected with the input end of an AND gate, the output end of the AND gate is connected with the input end of a delayer, and the output end of the delayer is connected with the input end of an adder and is connected with the control line of a data memory; the output end of the first decoder is also connected with the input end of a NOT gate, and the output end of the NOT gate is connected with the reset end of the adder; the output end of the adder is connected with a second decoder, the output end of the second decoder is connected with a chip selection pin of each I/O expansion chip, the output ends of the I/O expansion chips 1 to N-1 are connected with an address pin of the data memory, and the output end of the I/O expansion chip N is connected with a data pin of the data memory; and the control line of the micro control unit is also connected with the control line of each I/O expansion chip.
In the prior art, the existing micro-control unit storage expansion method realizes expansion through P1 and P3 pins of a single chip microcomputer or through a serial-parallel chip, so that the problems of limited expansion capacity, poor real-time performance, high expansion difficulty and high cost are caused. The data external memory expansion interface only occupies one I/O port of the micro control unit, and a huge storage space is obtained; the control is realized by a simple circuit, a CPU chip is not used, and programming is not needed; and the effect of expanding the data external memory is achieved by using a protocol development kit when the external memory is not required to be stored, so that the capacity limit is simply and effectively broken through and the real-time access of the ultra-large capacity is realized compared with the prior art.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious to those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
Fig. 1 is a schematic diagram of a data external memory expansion interface according to an embodiment of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
The embodiment of the invention discloses a data external memory expansion interface, which is applied to an interface circuit of an external memory.
Referring to fig. 1, which is a schematic diagram of a data external memory expansion interface provided in an embodiment of the present invention, the data external memory expansion interface includes:
the system comprises a Micro Control Unit (MCU), a first decoder, a second decoder, an adder, an AND gate, a NOT gate, a delayer, a data memory and two or more I/O expansion chips;
the data line of the micro control unit is connected with the data input end of each I/O expansion chip;
the address line of the micro control unit is connected with the input end of a first decoder, the output end of the first decoder and the control line of the micro control unit are connected with the input end of an AND gate, the output end of the AND gate is connected with the input end of a delayer, and the output end of the delayer is connected with the input end of an adder and is connected with the control line of a data memory;
the output end of the first decoder is also connected with the input end of a NOT gate, and the output end of the NOT gate is connected with the reset end of the adder;
the output end of the adder is connected with a second decoder, the output end of the second decoder is connected with a chip selection pin of each I/O expansion chip, the output ends of the I/O expansion chips 1 to N-1 are connected with an address pin of the data memory, and the output end of the I/O expansion chip N is connected with a data pin of the data memory;
and the control line of the micro control unit is also connected with the control line of each I/O expansion chip.
In the data external memory expansion interface described in this embodiment, the I/O expansion chip is a 74LS373 chip.
In the data external memory expansion interface described in this embodiment, both the first decoder and the second decoder employ 74LS138 chips.
In the data external memory expansion interface described in this embodiment, the memory is a read only memory or a random access memory.
In addition, on the basis of the data external memory expansion interface disclosed in this embodiment, this embodiment also discloses a method for controlling the data external memory expansion interface, where the method includes the following steps:
step 101, a micro control unit writes data information into an I/O expansion chip with the same address;
step 102, after the micro control unit selects an address, counting the number of times of writing through the adder to obtain a count value, and selecting an I/O expansion chip corresponding to a decoded signal after the count value passes through a second decoder;
103, writing the data information into I/O expansion chips with the same number and the same writing sequence respectively according to the writing sequence as the address information of the data memory;
writing first written data information into a first I/O expansion chip, writing second written data information into a second I/O expansion chip until writing Nth written data information into an Nth I/O expansion chip, wherein the first to Nth written data information is the address of a storage unit in a selected data memory, the Nth written data information is the data information written into the storage unit in the data memory, and the data memory comprises address information and data information;
104, transmitting a control signal of the micro control unit to a data memory through a delay unit, and performing AND operation on the control signal of the micro control unit, gating of a second decoder and an Nth I/O expansion chip, wherein the control signal is connected to a control line of the data memory, and the data information is stored in a storage unit corresponding to address information in the data memory;
105, when the address line signal of the micro control unit does not select the I/O expansion chip, the signal of the first decoder is connected to the reset end of the adder through the NOT gate, the reset signal is transmitted to the adder to reset the adder, and the second decoder selects the first I/O expansion chip;
and 106, repeating the steps 101 to 105 when the micro control unit writes data into the data memory again.
According to the technical scheme, the embodiment of the invention provides the data external memory expansion interface. The data external memory expansion interface comprises: the system comprises a micro control unit, a first decoder, a second decoder, an adder, an AND gate, a NOT gate, a delayer, a data memory and two or more I/O expansion chips; the data line of the micro control unit is connected with the data input end of each I/O expansion chip; the address line of the micro control unit is connected with the input end of a first decoder, the output end of the first decoder and the control line of the micro control unit are connected with the input end of an AND gate, the output end of the AND gate is connected with the input end of a delayer, and the output end of the delayer is connected with the input end of an adder and is connected with the control line of a data memory; the output end of the first decoder is also connected with the input end of a NOT gate, and the output end of the NOT gate is connected with the reset end of the adder; the output end of the adder is connected with a second decoder, the output end of the second decoder is connected with a chip selection pin of each I/O expansion chip, the output ends of the I/O expansion chips 1 to N-1 are connected with an address pin of the data memory, and the output end of the I/O expansion chip N is connected with a data pin of the data memory; and the control line of the micro control unit is also connected with the control line of each I/O expansion chip.
In the prior art, the existing micro-control unit storage expansion method realizes expansion through P1 and P3 pins of a single chip microcomputer or through a serial-parallel chip, so that the problems of limited expansion capacity, poor real-time performance, high expansion difficulty and high cost are caused. The data external memory expansion interface only occupies one I/O port of the micro control unit, and a huge storage space is obtained; the control is realized by a simple circuit, a CPU chip is not used, and programming is not needed; and the effect of expanding the data external memory is achieved by using a protocol development kit when the external memory is not required to be stored, so that the capacity limit is simply and effectively broken through and the real-time access of the ultra-large capacity is realized compared with the prior art.
In specific implementation, the present invention further provides a computer storage medium, where the computer storage medium may store a program, and the program may include some or all of the steps in the embodiments of a data external storage expansion interface provided by the present invention when executed. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM) or a Random Access Memory (RAM).
Those skilled in the art will readily appreciate that the techniques of the embodiments of the present invention may be implemented as software plus a required general purpose hardware platform. Based on such understanding, the technical solutions in the embodiments of the present invention may be essentially or partially implemented in the form of a software product, which may be stored in a storage medium, such as ROM/RAM, magnetic disk, optical disk, etc., and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method according to the embodiments or some parts of the embodiments.
The same and similar parts in the various embodiments in this specification may be referred to each other. The above-described embodiments of the present invention should not be construed as limiting the scope of the present invention.
Claims (4)
1. A data flash expansion interface, comprising:
the system comprises a micro control unit, a first decoder, a second decoder, an adder, an AND gate, a NOT gate, a delayer, a data memory and two or more I/O expansion chips;
the data line of the micro control unit is connected with the data input end of each I/O expansion chip;
the address line of the micro control unit is connected with the input end of a first decoder, the output end of the first decoder and the control line of the micro control unit are connected with the input end of an AND gate, the output end of the AND gate is connected with the input end of a delayer, and the output end of the delayer is connected with the input end of an adder and is connected with the control line of a data memory;
the output end of the first decoder is also connected with the input end of a NOT gate, and the output end of the NOT gate is connected with the reset end of the adder;
the output end of the adder is connected with a second decoder, the output end of the second decoder is connected with a chip selection pin of each I/O expansion chip, the output ends of the I/O expansion chips 1 to N-1 are connected with an address pin of the data memory, and the output end of the I/O expansion chip N is connected with a data pin of the data memory;
the control line of the micro control unit is also connected with the control line of each I/O expansion chip;
the control method of the data external memory expansion interface comprises the following steps:
step 101, the micro control unit writes data information into an I/O expansion chip with the same address;
step 102, after the micro control unit selects an address, counting the number of times of writing through the adder to obtain a count value, and selecting an I/O expansion chip corresponding to a decoded signal after the count value passes through a second decoder;
103, writing the data information into I/O expansion chips with the same number and the same writing sequence respectively according to the writing sequence as the address information of the data memory;
writing first written data information into a first I/O expansion chip, writing second written data information into a second I/O expansion chip until writing Nth written data information into an Nth I/O expansion chip, wherein the first to Nth written data information is the address of a storage unit in a selected data memory, the Nth written data information is the data information written into the storage unit in the data memory, and the data memory comprises address information and data information;
104, transmitting a control signal of the micro control unit to a data memory through a delay unit, and performing AND operation on the control signal of the micro control unit, gating of a second decoder and an Nth I/O expansion chip, wherein the control signal is connected to a control line of the data memory, and the data information is stored in a storage unit corresponding to address information in the data memory;
105, when the address line signal of the micro control unit does not select the I/O expansion chip, the signal of the first decoder is connected to the reset end of the adder through the NOT gate, the reset signal is transmitted to the adder to reset the adder, and the second decoder selects the first I/O expansion chip;
and 106, repeating the steps 101 to 105 when the micro control unit writes data into the data memory again.
2. The data external memory expansion interface of claim 1, wherein: the I/O expansion chip is a 74LS373 chip.
3. The data external memory expansion interface of claim 2, wherein: the first decoder and the second decoder are both 74LS138 chips.
4. The data export expansion interface of claim 3, wherein: the data memory is a read-only memory or a random access memory.
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