CN111446290A - A power semiconductor device and its edge termination region structure and processing method - Google Patents

Abstract

The present invention provides a power semiconductor device and its edge termination area structure and processing method, and relates to the field of power semiconductors. The edge termination region includes: a backside metal electrode layer; an N ⁺ substrate adjacent to above the backside metal electrode layer; an N-type epitaxial layer adjacent to the N ⁺ substrate; a p-doped field ring disposed on the the upper surface of the N-type epitaxial layer; the floating p-layer ring, arranged in the N-type epitaxial layer, and extending longitudinally in the N-type epitaxial layer to extend the longitudinal depth of the space charge layer and reduce the applied electric field strength; the insulating field plate, set above the p-doped field ring; a surface metal electrode layer is disposed above the insulating field plate and the p-doped field ring. The floating p-layer ring is added, which extends longitudinally in the N-type epitaxial layer, so that the boundary of the space charge layer extends longitudinally when it expands to the outer periphery. It does not need to increase the area of the edge termination region, but can improve the withstand voltage capability of the edge termination region. Conducive to the miniaturization of power semiconductor devices.

Description

A power semiconductor device and its edge termination region structure and processing method

technical field

The present invention relates to the field of power semiconductors, in particular to a power semiconductor device and an edge termination area structure and a processing method thereof.

Background technique

Many functional devices in automotive, consumer electronics, and industrial applications, such as power conversion devices and motor drives, rely on power semiconductor devices. For example, power semiconductor devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), and diodes have been used in various applications such as power supplies in traction applications and switches in power converters .

Power semiconductor devices typically include edge termination regions surrounding the active region in addition to the active region responsible for conducting current. A common example of an edge termination region structure for a power semiconductor device is the combination of a p-doped polysilicon field ring and a field plate, where the field plate can be configured to provide effective shielding of external charges. For example, the field plate may comprise a metal, such as aluminum. Alternatively, such field plates may be formed from polysilicon, for example, to make the edge termination structures less susceptible to corrosion when exposed to moisture and electric fields. For example, in an edge termination structure combining a p-doped field ring with an n-doped polysilicon field plate, a metal layer may still be present to provide electrical contact between the field plate and the field ring, thereby reducing the effect of the electric field on the outer edges of the metal layer. influence and improve the stability of the device.

A reliable edge termination area is to ensure that the active area of the device is not affected by the outside world and can work normally even in harsh working environments, such as high temperature, high humidity, and external strong electric fields.

In order to ensure a sufficiently high withstand voltage capability of the edge termination region, the edge termination region needs a long insulating field plate to disperse the electric field, which leads to a larger area of the edge termination region of the traditional structure, which is not conducive to the miniaturization of the chip.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a power semiconductor device and its edge termination region structure and processing method, which can improve the withstand voltage capability of the edge termination region without enlarging the size of the power semiconductor device, so as to fully protect the power semiconductor active area of the device. To this end, the present invention adopts the following solutions to achieve the object.

The present invention provides an edge termination area structure of a power semiconductor device, and the edge termination area includes:

(1) back metal electrode layer;

(2) N ⁺ substrate, adjacent to above the back metal electrode layer;

(3) an N-type epitaxial layer adjacent to the N ⁺ substrate;

(4) a p-doped field ring, disposed on the upper surface of the N-type epitaxial layer;

(5) The floating p-layer ring is arranged in the N-type epitaxial layer and extends longitudinally in the N-type epitaxial layer to extend the longitudinal depth of the space charge layer;

(6) an insulating field plate, arranged above the p-doped field ring;

(7) A surface metal electrode layer, disposed above the insulating field plate and the p-doped field ring.

Preferably, the floating p-layer ring is disposed below the p-doped field ring of the outermost region.

Preferably, the floating p-layer ring is disposed outside the p-doped field ring of the outermost region.

Preferably, the floating p-layer ring is disconnected from the p-doped field ring.

Preferably, the insulating field plate is made of silicon dioxide.

Preferably, the material of the N ⁺ substrate is a silicon wafer doped with phosphorus atoms.

The present invention also provides a power semiconductor device, including the edge termination region structure described in any one of the above.

The present invention also provides a method for processing the edge termination area structure of a power semiconductor device as described in any of the above, comprising the following steps:

(1) growing an N-type epitaxial layer on an N ⁺ substrate;

(2) Implanting ions into the N-type epitaxial layer;

(3) repeating steps (1) and (2), carrying out multiple epitaxy and ion implantation;

(4) annealing, the ions diffuse to form a floating p-layer ring;

(5) Implanting ions on the upper surface of the N-type epitaxial layer to form a p-doped field ring, and then depositing and growing an insulating field plate on the p-doped field ring;

(6) A surface metal electrode layer is formed on the insulating field plate and p-doped field ring, and a back metal electrode layer is formed on the lower surface of the N ⁺ substrate.

Preferably, the ions implanted in step (2) and step (5) are all boron.

Preferably, in step (6), the surface metal electrode layer and the back metal electrode layer are formed by metal evaporation and deposition.

The beneficial effect of the present invention is that a floating p-layer ring is added to the p-doped field ring in the outermost region, and the floating p-layer ring extends longitudinally in the N-type epitaxial layer, so that the boundary of the space charge layer extends longitudinally when expanding to the outer periphery. , reducing the intensity of the applied electric field, and greatly improving the withstand voltage capability of the edge terminal area of the power semiconductor device. Compared with the traditional edge termination area structure, the present invention does not need to increase the area of the edge termination area to improve its peripheral withstand voltage capability, which is beneficial to the miniaturization of the power semiconductor device.

Description of drawings

In order to illustrate the technical solutions of the present invention more clearly, the accompanying drawings required in the specification will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention, which are not relevant to ordinary skills in the field. As far as personnel are concerned, other drawings can also be obtained from these drawings on the premise of no creative work.

Fig. 1 is the structure diagram of the edge termination area of the conventional power semiconductor device;

2 is a structural diagram of an edge termination region of a power semiconductor device provided by an embodiment of the present invention;

3 is a structural diagram of an edge termination region of another power semiconductor device provided by another embodiment of the present invention;

4 is a schematic diagram of growing an N-type epitaxial layer on an N ⁺ substrate according to the present invention;

5 is a schematic diagram of a multi-layer N-type epitaxial layer grown on an N ⁺ substrate according to the present invention;

6 is a schematic diagram of a multi-layer N-type epitaxial layer grown on an N ⁺ substrate according to the present invention, which is annealed to form a floating p-layer ring;

7 is a stacking diagram of an N ⁺ substrate+N-type epitaxial layer+floating p-layer ring+p-doped field ring+insulating field plate of the present invention;

8 is a schematic structural diagram of an edge termination region of a power semiconductor device obtained by applying the processing method of the present invention.

Reference signs: back metal electrode layer 1; N ⁺ substrate 2; N-type epitaxial layer 3; p-doped field ring 4; floating p-layer ring 5; insulating field plate 6; surface metal electrode layer 7; space charge layer boundary 8; Ion 9.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

FIG. 1 is a structural diagram of the edge termination region of a power semiconductor device with a conventional structure. The edge termination region is provided with a shallow p-doped field ring 4, resulting in the space charge layer boundary 8 at its termination being in a shallow layer, which is provided with a longer The insulating field plate 6 is used to disperse the electric field, resulting in a larger area of the edge termination region of the conventional structure, which is not conducive to the miniaturization of the power semiconductor device.

Example

As shown in FIG. 2, an embodiment of the present invention provides an edge termination area structure of a power semiconductor device, and the edge termination area includes:

(1) backside metal electrode layer 1;

(2) N ⁺ substrate 2, adjacent to the backside metal electrode layer 1;

(3) an N-type epitaxial layer 3 adjacent to the N ⁺ substrate 4;

(4) The p-doped field ring 4 is disposed on the upper surface of the N-type epitaxial layer 3;

(5) The floating p-layer ring 5 is arranged in the N-type epitaxial layer 3 and extends longitudinally in the N-type epitaxial layer 3 to extend the longitudinal depth of the space charge layer, and the space charge layer boundary 8 expands in the direction of the back metal electrode layer 1 ;

(6) an insulating field plate 6, arranged above the p-doped field ring 4;

(7) The surface metal electrode layer 7 is disposed above the insulating field plate 6 and the p-doped field ring 4 .

Among them, N ⁺ in the N ⁺ substrate 2 represents high-concentration doping, and N in the N-type epitaxial layer 3 represents low-concentration doping. In one of the preferred embodiments, the N ⁺ substrate 2 is a silicon wafer doped with high-concentration phosphorus, and the N-type epitaxial layer 3 is a single-crystal silicon layer doped with low-concentration phosphorus.

The floating p-layer ring 5 is disposed below the p-doped field ring 4 in the outermost region.

As shown in FIG. 3 , in another preferred embodiment, the floating p-layer ring 5 is disposed outside the p-doped field ring 4 in the outermost region.

To ensure the reliability of power semiconductor devices, the voltage withstand capability of the edge termination region needs to be higher than that of the active region. The most effective way to increase the withstand voltage is to reduce the strength of the applied electric field. Under a constant external voltage, the larger the space charge layer, the smaller the applied electric field strength. The purpose of adding the floating P-layer ring 5 is to extend the longitudinal depth of the space charge layer and reduce the applied electric field strength.

Specifically, a floating p-layer ring 5 is added to the p-doped field ring 4 in the outermost region, and the floating p-layer ring 5 extends longitudinally in the N-type epitaxial layer 3, so that the space charge layer boundary 8 expands to the outer periphery more vertically The extension increases the volume of the space charge layer, reduces the intensity of the applied electric field, and greatly improves the withstand voltage capability of the terminal area of the power semiconductor device. Compared with the traditional terminal area structure, the present invention reduces the peripheral area of the power semiconductor device while ensuring the improvement of the peripheral withstand voltage capability, which is beneficial to the miniaturization of the power semiconductor device.

In one of the preferred embodiments, the floating p-layer ring 5 is disconnected from the p-doped field ring 4, and the disconnection is beneficial to further reduce the strength of the applied electric field.

In one of the preferred embodiments, the insulating field plate 6 is made of silicon dioxide.

The present invention also provides a power semiconductor device, including the edge termination region structure described in any one of the above embodiments, so that the outer circumference of the semiconductor device is reduced in size.

The present invention also provides a method for processing an edge termination region structure of a power semiconductor device according to any one of the above embodiments, comprising the following steps:

(1) As shown in FIG. 4, an N-type epitaxial layer 3 is grown on the N ⁺ substrate 2;

(2) As shown in FIG. 4, ions 9 are implanted into the N-type epitaxial layer 3; in one preferred embodiment, the ions 9 implanted in the N-type epitaxial layer 3 are boron, which is implanted using an ion implanter, and the implanted region is formed p-type semiconductor;

(3) as shown in Figure 5, repeat steps (1) and (2), and carry out multiple epitaxy and ion implantation;

(4) As shown in FIG. 6, annealing, the ions 9 diffuse to form a floating p-layer ring 5; in one preferred embodiment, the annealing condition is an oxidizing atmosphere, and the material is kept at a temperature of 1050-1100 ° C for 1-1.5 h;

(5) As shown in FIG. 7, ions are implanted on the upper surface of the N-type epitaxial layer 3 to form a p-doped field ring 4, and then an insulating field plate 6 is deposited and grown on the p-doped field ring 4; in one of the preferred embodiments , the ions implanted on the upper surface of the N-type epitaxial layer 3 are boron, which is implanted by an ion implanter, and the implanted area forms a p-type semiconductor;

(6) As shown in FIG. 8 , the surface metal electrode layer 7 is formed on the insulating field plate 6 and the p-doped field ring 4 , and the back metal electrode layer 1 is formed on the lower surface of the N ⁺ substrate 2 . Among them, the surface metal electrode layer 7 and the back metal electrode layer 1 are formed by metal evaporation and deposition.

In the present invention, the edge termination region and the active region are integrally formed, and the same layers are processed simultaneously.

The above disclosures are only the preferred embodiments of the present invention, and cannot be used to limit the scope of rights of the present invention. Those of ordinary skill in the art can understand that all or part of the procedures for implementing the above-mentioned embodiments can be made according to the claims of the present invention. The equivalent changes of the invention still belong to the scope of rights covered by the present invention.

Claims (10)

1. A power semiconductor device edge termination region structure, the edge termination region comprising:

a back metal electrode layer;

N⁺the substrate is adjacent to the upper part of the back metal electrode layer;

an N-type epitaxial layer adjacent to the N⁺A substrate over the substrate;

the p-doped field ring is arranged on the upper surface of the N-type epitaxial layer;

the floating p-layer ring is arranged in the N-type epitaxial layer and longitudinally extends in the N-type epitaxial layer so as to extend the longitudinal depth of the space charge layer;

an insulated field plate disposed above the p-doped field ring;

and the surface metal electrode layer is arranged above the insulating field plate and the p-doped field ring.

2. The power semiconductor device edge termination region structure of claim 1, wherein the floating p-layer ring is disposed below a p-doped field ring of an outermost region.

3. The power semiconductor device edge termination region structure of claim 1, wherein the floating p-layer ring is disposed outside a p-doped field ring of an outermost region.

4. The power semiconductor device edge termination region structure of claim 1, wherein the floating p-layer ring is disposed off of the p-doped field ring.

5. The power semiconductor device edge termination region structure of claim 1, wherein the insulating field plate is silicon dioxide.

6. The power semiconductor device edge termination region structure of claim 1, wherein the N is⁺The substrate is made of a silicon wafer doped with phosphorus atoms.

7. A power semiconductor device comprising the edge termination region structure of any one of claims 1 to 6.

8. A method for processing the edge termination region structure of the power semiconductor device according to any one of claims 1 to 6, characterized by comprising the following steps:

(1) in N⁺Growing an N-type epitaxial layer on a substrate;

(2) implanting ions into the N-type epitaxial layer;

(3) repeating the steps (1) and (2), and carrying out multiple times of epitaxy and ion implantation;

(4) annealing, wherein the ions are diffused to form a floating p-layer ring;

(5) implanting ions into the upper surface of the N-type epitaxial layer to form a p-doped field ring, and depositing and growing an insulating field plate on the p-doped field ring;

(6) forming a surface metal electrode layer on the insulating field plate and the p-doped field ring, and forming a metal electrode layer on the surface of the insulating field plate and the p-doped field ring⁺And generating a back metal electrode layer on the lower surface of the substrate.

9. The process of claim 8 wherein the ions implanted in steps (2) and (5) are both boron.

10. The process of claim 8, wherein in step (6), the surface metal electrode layer and the back metal electrode layer are formed by metal evaporation and deposition.

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