CN111446977B - Ultra-wideband preamble receiver and receiving method thereof - Google Patents
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Abstract
本发明公开了一种超宽带前导码接收器，包括N路采样数据串并转换器，第一存储器在第一预设周期内其一部分执行存储采样数据，同时另一部分执行相关运算，且持续第二预设周期后两部分存储器工作任务互换；第二存储器存储不同码相位的相关累加中间结果和最终结果，预处理模块滤除载波频偏，N路并行加法器和动态限幅器，码相位部份相关累加结果累加器；非零前导码选择器将非零前导码位置值，转换为某N个码相位的具体地址值，读取第二存储器中相关累加结果的部份值，加上本次运算的部份相关累加结果值，存回第二存储器同一地址。本发明还公开了一种超宽带前导码接收方法，能有效降低相关器动态功耗、静态功耗和器件面积开销。
The invention discloses an ultra-wideband preamble receiver, comprising N channels of sampling data serial-to-parallel converters, a part of a first memory executes storage of sampling data in a first preset period, while the other part executes a correlation operation, and continues for the first After the two preset cycles, the two parts of the memory are exchanged for work tasks; the second memory stores the intermediate and final results of correlation accumulation of different code phases, the preprocessing module filters out the carrier frequency offset, the N-way parallel adder and the dynamic limiter, the code Phase partial correlation accumulation result accumulator; the non-zero preamble selector converts the non-zero preamble position value into the specific address value of a certain N code phase, reads the partial value of the correlation accumulation result in the second memory, adds The partial correlation accumulation result value of the previous operation is stored back to the same address in the second memory. The invention also discloses an ultra-wideband preamble receiving method, which can effectively reduce the dynamic power consumption, static power consumption and device area overhead of the correlator.
Description
Technical Field
The invention relates to the technical field of wireless communication, in particular to an ultra-wideband (UWB) preamble receiver based on UWB communication transmission technology. The invention also relates to an ultra-wideband (UWB) preamble receiving method based on the UWB communication transmission technology.
Background
In IEEE Standard 802.15.4-2011, an ultra wideband (UWB PHY) communication technology system is proposed, a protocol describes a transceiver originating operation system, and a frame Format (UWB PPDU Format) is defined for a baseband data Format to be transmitted, which is shown in fig. 1. In the UWB PPDU, the SHR is composed of SYNC (synchronization frame) and SFD (start position frame), and the structure is shown with reference to fig. 2. The protocol stipulation SYNC part is composed of two preambles of 31 length and 127 length, and is repeatedly formed for a plurality of times, the preamble is composed of a three-value sequence of { +1, -1,0}, and the preamble of the protocol stipulation part is shown in figure 9. Here, with 31 lengths and preamble number 1 as an example, a SYNC frame is formed, C0 indicates preamble number 1 codeword { +1, -1,0}, and C30 indicates preamble number 1 codeword { +1, -1,0}, with reference to fig. 3. How preamble detection is implemented at the receiving end of the transceiver and the key correlator design architecture are not specified in the protocol.
Chinese patent application CN103222198A discloses a digital correlator design scheme for preamble detection, which adopts a sliding window manner to perform a cross-correlation operation between received data and a preamble in real time. Meanwhile, one path of ADC data close to the sampling frequency of 1Ghz is converted into 16 paths of parallel data through a multiplexer by utilizing a mode of resource consumption and data exchange processing speed. Taking lead code with 127 length as an example, the sampling rate of each path of data is still 1Ghz, but the working frequency of the correlator can be reduced to 62.4Mhz, the 16 correlators work simultaneously in parallel, 8 lead code phase searches (4 x 127 x 2) are completed within 8 symbol times, and equivalently 8 x (4 x 127 x 2) multiplication and addition operations are performed within 8 symbols, and the sum of the results is obtained. Although 63 zeros exist in each group of preambles, the whole arithmetic unit still needs 127 multiply-add units because the sliding window needs to traverse different preambles, and it can be seen in fig. 10 that CN103222198A uses 127 multiply-add units, and the digital circuit gate level flip rate is still maintained at the operation amount level of 8 × 127 (4 × 127 × 2). The correlator architecture obtains the correlation value calculation of the full code phase and can be used for preamble detection.
In the existing architecture, one correlator uses 127-level pipelining, and after the pipelining storage result and the local preamble operation, 127 operand flip and full add operations are required, which results in 16 sets of correlators. For a certain preamble, there are 63 zero-valued preambles, but the accumulator digital circuit of CN103222198A still sums up with 127 multiply-adders, and the level of the number of times of inversion of the adders in the adder tree still approaches the level of 4 × 127 × 2 × 127 correlated accumulation operations. The actual circuit slew rate is not significantly reduced by the 63 zero-valued preambles. The extremely large area of the correlator is caused, the design cost is increased, and the extremely large dynamic power consumption is increased when the circuit drain is inverted. Even if most of the devices do not have inverted drains, the static power consumption of a huge number of devices is very considerable under the deep submicron level process. In some low power IoT application scenarios, this may severely limit the use of the chip.
Disclosure of Invention
In this summary, a series of simplified form concepts are introduced that are simplifications of the prior art in this field, which will be described in further detail in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
The invention aims to solve the technical problem of providing an ultra-wideband lead code receiver which can complete the calculation of the lead code full code phase correlation value and effectively reduce the dynamic power consumption, static power consumption and device area overhead of a correlator in the same working frequency and time compared with the prior art.
The invention aims to solve another technical problem of providing an ultra-wideband lead code receiving method which can complete the calculation of the lead code full code phase correlation value and effectively reduce the dynamic power consumption, static power consumption and device area overhead of a correlator in the same working frequency and time compared with the prior art.
In order to solve the above technical problem, the present invention provides an ultra-wideband preamble receiver, including:
the N-channel serial-parallel converter samples data to be received at a preset sampling frequency and converts the data into N channels of parallel;
the first memory is divided into two parts, one part of the first memory is used for storing sampling data in a first preset period, the other part of the first memory is used for performing correlation operation, and the work tasks of the two parts of the first memory are interchanged after a second preset period continues;
the second memory is used for storing correlation accumulation intermediate results and final results of different code phases, the data stored in the first memory are stored in the second memory after being operated by the parallel adder, and the correlation result of the Xth code phase is stored in the X address of the second memory;
the preprocessing module is used for filtering carrier frequency offset of the N paths of ADC sampling data;
the N paths of parallel adders are used for superposing parallel data and transmitting the current symbol data which is processed by superposing the last symbol data in the X address of the memory for storing the data to the dynamic amplitude limiter;
the dynamic amplitude limiter is used for dynamically limiting the data and storing the limited data into a memory for storing the X address of the data memory;
the accumulator is used for accumulating the correlation of partial code phases;
the non-zero lead code selector converts the position value of the stored non-zero lead code into a specific physical storage address value of a certain N code phases, reads a partial value of the correlation accumulation result stored in the second memory according to the address, adds the partial correlation accumulation result value of the current operation through the operation of an accumulator, and then stores the partial correlation accumulation result value back to the same address of the second memory.
In operation, the sampled data at the same location with different signs are stored at the same address in the first memory.
Wherein the two parts of the first memory structure form a ping-pong memory.
Optionally, the ultra-wideband preamble receiver is further improved, wherein the first predetermined period is one symbol.
Optionally, the ultra-wideband preamble receiver is further improved, and the second preset period is eight symbols.
Optionally, the ultra-wideband preamble receiver is further improved, wherein N is 2mM is an integer, m is not less than 3.
Optionally, the ultra-wideband preamble receiver is further improved, and the working dominant frequency thereof includes but is not limited to 249.6 Mhz.
Optionally, the ultra-wideband preamble receiver is further improved, which is suitable for any architecture using non-zero preambles.
The invention provides an ultra-wideband lead code receiving method which is characterized by comprising the following steps:
sampling data to be received at a preset sampling frequency, and filtering carrier frequency offset of the sampled data;
performing storage sampling data on one part of the first memory in a first preset period, simultaneously performing related operation on the other part of the first memory, and interchanging work tasks of the two parts of the memories after a second preset period;
the data stored in the first memory is stored in the second memory after being operated by the parallel adder, and the correlation result of the Xth code phase is stored in the X address of the second memory;
after the data of the last symbol in the address of the data part X is overlapped with the processed data of the current symbol and output, the data of the last symbol in the address of the data part X is stored in the first memory for storing the address of the data part X after dynamic amplitude limiting;
and converting the position value of the stored nonzero lead code into a specific address value of a certain code phase, reading a partial value of the correlation accumulation result stored in the second memory according to the address, adding the partial correlation accumulation result value of the current operation through the operation of an accumulator, and storing the partial correlation accumulation result value back to the same address of the second memory.
Wherein the sampled data of the same position with different symbols are stored in the same address of the first memory for storing the sampled data part.
Optionally, the method for receiving the ultra-wideband preamble is further improved, and the first preset period is one symbol.
Optionally, the method for receiving the ultra-wideband preamble is further improved, and the second preset period is eight symbols.
Optionally, the uwb preamble receiving method is further improved, and the parallelism of the data samples, the adder and the accumulator is N, where N is 2mM is an integer, m is not less than 3.
The technical scheme of the invention at least has the following technical effects:
1. the invention adopts a mode of circularly displacing non-zero lead codes to carry out correlation operation on fixed data, carries out cross-correlation operation from the angle of codes because 15/63 code values 0 exist in 31/127 two lead code codes, effectively utilizes the characteristic that 0-value codes have no influence on correlation values, directly skips the correlation operation of the 0-value lead codes and carries out the correlation operation of the non-0-value codes. Taking 127-length codes as an example, after one correlation operation is completed, the logic turnover number level is reduced from (4 × 127 × 2) 127 level to (4 × 127 × 2) 64, the total number of logic turnover numbers is reduced, and the overall dynamic power consumption of the device is effectively reduced.
2. The invention uses the architecture of first storage and then operation, uses two high integration level memories as ping-pong buffer to replace the register array in the correlator, and the area of a single storage unit of the high integration level memory is about 1/2 of a register (depending on the process and the type of the memory). Because a ping-pong cache is used and the bit width of a single storage unit is greater than that of a single unit of the register array, the memory area is larger than that of the register array. The dynamic power consumption of the memory is only related to the number of the currently activated bit lines, and in the invention, the number of the activated bit lines per unit time is only (16) multiple bits by 2 times, which is far less than 16 registers of the 4000-bit register array. Therefore, the power consumption of the working state of the invention is far less than that of a correlator formed by a CN103222198A register array.
3. The memory stores N ADC output data in parallel at the same address, and for a certain code phase, taking N-8 as an example, instead of using the equivalent summation logic in 48b in fig. 6 of CN103222198A specification, 8 multi-bit adders are used. Taking 127 code lengths as an example, the data read from the memory during the operation needs 64 clock cycles (because the 63 code values are 0) to complete 1/128 code correlation values of all code phases (127 in total), and the correlation value operation of a certain code phase is completed by 128 times of segmented accumulation. In unit time, the dynamic power consumption, the device area and the static power consumption of the 8 multi-bit adders are far smaller than the equivalent summation logic of CN 103222198A. The device area gain obtained here can completely offset the area overhead of the memory in the second point, and even make the total area smaller in the deep submicron process.
4. The memory of the invention adopts a ping-pong processing mode, and when the ping-pong memory receives data, the ping-pong memory carries out correlation operation and switches once every 8 symbols. The data of the same sampling position of different symbols are stored in the same address of the memory, the carrier frequency offset is eliminated by adopting a preprocessing mode, the data of 8 symbols are accumulated together for processing, and the amplitude is dynamically adjusted.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention, are incorporated in and constitute a part of this specification. The drawings are not necessarily to scale, however, and may not be intended to accurately reflect the precise structural or performance characteristics of any given embodiment, and should not be construed as limiting or restricting the scope of values or properties encompassed by exemplary embodiments in accordance with the invention. The invention will be described in further detail with reference to the following detailed description and accompanying drawings:
fig. 1 is a diagram of a PPDU frame structure.
Fig. 2 is a schematic diagram of an SHR frame structure.
Fig. 3 is a diagram illustrating SYNC frame construction.
FIG. 4 is a schematic diagram illustrating the switching principle of the memory function according to the present invention.
FIG. 5 is a schematic diagram of a partial correlation accumulation calculation according to the present invention.
Fig. 6 is a diagram of an embodiment of the present invention applied to correlation accumulation calculation of 127-length preambles.
FIG. 7 is a diagram illustrating a first principle of correlation value calculation according to the present invention.
FIG. 8 is a second schematic diagram illustrating the correlation value calculation principle of the present invention.
FIG. 9 is a 127 length preamble schematic specified by the IEEE 802.15.4 protocol
FIG. 10 is a schematic diagram of a digital circuit implementation of a related accumulator in Chinese patent CN103222198A
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and technical effects of the present invention will be fully apparent to those skilled in the art from the disclosure in the specification. The invention is capable of other embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the general spirit of the invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict. The following exemplary embodiments of the present invention may be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein. It is to be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the technical solutions of these exemplary embodiments to those skilled in the art.
As shown in fig. 4 and 5, a first embodiment of the ultra-wideband preamble receiver provided by the present invention includes:
the N-channel serial-parallel converter samples data to be received at a preset sampling frequency;
the first memory is divided into two parts, the two parts of the first memory form a ping-pong memory, one part of the first memory stores the sampling data in a first preset period, the other part of the first memory executes the correlation operation, and the work tasks of the two parts of the first memory are exchanged after the second preset period lasts; the sampling data with different symbols and the same position are stored in the same address of the first memory;
the second memory is used for storing correlation accumulation intermediate results and final results of different code phases, the data stored in the first memory are stored in the second memory after being operated by the parallel adder, and the correlation result of the Xth code phase is stored in the X address of the second memory;
the preprocessing module is used for filtering carrier frequency offset of the N paths of ADC sampling data;
the N paths of parallel adders are used for superposing parallel data and transmitting the current symbol data which is processed by superposing the last symbol data in the X address of the memory for storing the data to the dynamic amplitude limiter;
the dynamic amplitude limiter is used for dynamically limiting the data and storing the limited data into a memory for storing the X address of the data memory;
the accumulator is used for accumulating the correlation of partial code phases;
the non-zero lead code selector converts the position value of the stored non-zero lead code into a specific address value of a certain N code phases, reads a partial value of the correlation accumulation result stored in the second memory according to the address, adds the partial correlation accumulation result value of the current operation through the operation of an accumulator, and then stores the partial correlation accumulation result value back to the same address of the second memory.
Further, it will be understood that, although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of exemplary embodiments according to the present invention. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The present invention is further illustrated with reference to fig. 6,7 and 8, which illustrate a 127 length preamble correlation accumulation calculation as a specific embodiment.
The result of 1016 correlation accumulations is obtained in the time domain using a sliding window CN103222198A, equivalent to cyclically shifting the preamble in fig. 4, without moving data. And performing correlation accumulation, namely calculating a summation value of a certain row in the computational graph 4. The first row Data in the figure corresponds to the input signal, and c0 to c126 correspond to a certain preamble. The correlation accumulation result of a certain X code phase (X belongs to 0 to 1015, corresponding to the X-th row in the above table) is obtained by calculating c (Y) × data (Z) + c (Y +1) × data (Z +1) + … c (Y +126) × data (Z + 126). In the above equation, c (y) is the preamble c of the X row in the table above. data (z) represents the corresponding data in row X of the table, column where the non-0 preamble is located. For example, when the code phase 8 is obtained, c (0) is c126, c (1) is 0, data (0) is data0, and data (1) is data 8. Data0 corresponds to Data8 for the 0 th and 8 th input Data in the Data line of the above figure.
In actual operation, the correlation accumulation result of 8 code phases is calculated simultaneously, and the correlation accumulation of 8 code phases is completed in 127 times, and only the correlation result value of 8 code phases 1/127 is calculated each time. (i.e., 8 code phases in a small box, each small box representing 1/127 correlation accumulations of 8 different code phases).
The 1/128 code correlation value for a certain code phase is calculated, i.e. the value in the second box is calculated. The values in the first box are the partial correlation accumulation values at some 8 code phases that are continuously updated. And updating the data values corresponding to the first frame and the second frame in the next operation. And analogizing in sequence, and finishing all correlation value operations of a certain code phase at 127 th time. There are 64 0 value preambles for c 0-c 126, and these 0 value preambles do not require updating the values of the second and first boxes. The position of the non-zero code value in a certain preamble can be pre-stored in the memory by calculation, and the position is the code phase required to perform the correlation operation. When the operation is started, the operation is read into the non-zero preamble selector in fig. 7, and the operation is matched with the relevant accumulated value. Such as a certain code word: 0, 0, +1, -1,0, 0, -1, +1, 0, 0 …, can store 2, 3,6,7 …, and the correspondence of specific non-zero code words and certain code phase storage addresses is not a one-to-one mapping, and can be transformed according to a supplementary graph. But the core mechanism is to store a mapping relation of a non-zero preamble code to a certain code phase storage address. In the process of updating the first frame value, the non-zero preamble selector outputs the 2, 3,6,7 … address to other memory devices, and the other memory devices read the relevant accumulated result value of the previous 1/127 according to the address, add the operation result of the second frame, update the value in the first frame, and store the value back to the same address. Other positions have the same value in the first box because the preamble is 0. Each codeword stores 64 stored values. The non-0 preamble can be directly acquired when the preamble is used.
The pre-update correlation accumulation values correspond to the first box portion in fig. 7, and the post-update correlation accumulation values correspond to the first box portion in fig. 8. The 1/127 correlation accumulation values calculated for each operation correspond to the second block portion of FIGS. 7 and 8. The operation result in the first box is stored in the other storage device (i.e., the second memory) in fig. 6. Each address in the memory device of fig. 6 corresponds to a correlation accumulation intermediate result for a certain code phase. Such as address 0 corresponding to a correlation accumulation intermediate result for code phase 0. Since 63 x 8 code phases are zero in the 0 th to 1015 th code phases, the 63 x 8 code phases do not need to be correlated, so that each operation does not need to traverse all code phases. The code phase values corresponding to the non-zero preambles are stored in the non-zero preamble selector in fig. 6. Each time the value in the second frame is calculated, the values stored in the addresses corresponding to the other storage devices in fig. 6 are read according to the code phase stored in the non-zero preamble selector, and the values are added with the operation result in the second frame and stored back to the addresses corresponding to the other storage devices (i.e., the second memory) in fig. 6, that is, the update of the code phase correlation accumulated value is completed once, and the result in the first frame is updated in the process. After 127 operations, the correlation accumulation operation for a certain code phase is completed.
The technical scheme of the invention is suitable for any architecture for performing correlation accumulation by a fixed received data and mobile preamble mode, such as changing the parallelism to 16/32/64. Any increase/decrease of the operating dominant frequency of the associated accumulator, such as 249.6Mhz operating dominant frequency. Any architecture that uses only non-zero preamble values, and no zero preamble.
The invention provides a first embodiment of an ultra-wideband preamble receiving method, which comprises the following steps:
sampling data to be received at a preset sampling frequency, and filtering carrier frequency offset of the sampled data;
performing storage sampling data on one part of the first memory in a first preset period, simultaneously performing related operation on the other part of the first memory, and interchanging work tasks of the two parts of the memories after a second preset period; the sampling data with different symbols and the same position are stored in the same address of the first memory for storing the sampling data part;
the data stored in the first memory is stored in the second memory after being operated by the parallel adder, and the correlation result of the Xth code phase is stored in the X address of the second memory;
after the data of the last symbol in the address of the data part X is overlapped with the processed data of the current symbol and output, the data of the last symbol in the address of the data part X is stored in the first memory for storing the address of the data part X after dynamic amplitude limiting;
and converting the position value of the stored nonzero lead code into a specific address value of a certain code phase, reading a partial value of the correlation accumulation result stored in the second memory according to the address, adding the partial correlation accumulation result value of the current operation through the operation of an accumulator, and storing the partial correlation accumulation result value back to the same address of the second memory.
Optionally, the first embodiment of the uwb preamble receiving method is further improved, where the first preset period is one symbol, the second preset period is eight symbols, and the parallelism of the data samples, the adder, and the accumulator is N, where N is 2mM is an integer, m is not less than 3.
The present invention has been described in detail with reference to the specific embodiments and examples, but these are not intended to limit the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
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