CN111489773B - Circuit for reading data, nonvolatile memory and method for reading data - Google Patents

Abstract

The invention provides a circuit for reading data, a nonvolatile memory and a method for reading the circuit. The circuit is applied to a non-volatile memory, and the non-volatile memory includes a storage unit, and the circuit includes: a sense amplifier, a latch, a latch management module, a logic circuit, and a data output module, and the sense amplifier The number of the number and the number of the latches are respectively an integer multiple of the number of data output by the data output module, and the logic circuit is connected to the bit line of the storage unit and the sense amplifier respectively, so The sense amplifier is respectively connected to the logic circuit and the latch, the latch is respectively connected to the sense amplifier and the latch management module, and the latch management module is connected to the latch and the data output module are respectively connected, and the data output module is connected with the latch management module.

Description

A circuit for reading data, a non-volatile memory and a method for reading data

technical field

The invention relates to the field of nonvolatile memory, in particular to a circuit for reading data, a nonvolatile memory and a method for reading data.

Background technique

With the development of various electronic devices and embedded systems, non-volatile memory devices are widely used in electronic products. Take non-volatile memory NAND Flash Memory (NAND Flash Memory) as an example. NAND memory is composed of multiple storage cells (cells), which can be programmed multiple times, with large capacity, simple reading and writing, few peripheral devices, and low price.

The principle schematic diagram of existing Nand flash is shown in Figure 1, and the basic operation of Nand flash mainly contains read (read), program (program), erase (erase) three kinds, for read operation, on the word line (word in Figure 1 Line (abbreviated as wl) applies an appropriate voltage to read the data on the selected storage unit and output it through the data transmission module, where wl0 to wlm represent m wls, and the bit line (bit line referred to as bl in Figure 1) is 0 to bit The line (bl in Figure 1) n represents n bls, and each bl corresponds to a sense amplifier (sa in Figure 1) and a latch (latch in Figure 1), when the non-volatile memory performs a read operation, sa first reads all the data in the storage unit through bl, and transmits it to the latch, and then the latch transmits the read data to the data output module (datapath), and finally the datapath uses 16 each time (Q< 15:0>) mode of data will output the read data.

In the process of the above work, when sa receives a high-level enable signal, sa reads the data of the storage unit through bl, and transmits it to the latch, and is transmitted from the latch to the datapath, and then when the datapath receives a high level When the signal is enabled, the received read data is output, and during the time period of datapath data output, sa does not work all the time, even if sa receives a high-level enable signal, sa still does not work until After the datapath has finished outputting all the data, sa receives the high-level enable signal before continuing to read the next set of data, which wastes a lot of time and makes the work efficiency of the non-volatile memory low. On the other hand Since there are many bls, there are tens of thousands of bls in the general non-volatile memory, so there are many latches corresponding to sa and sa, which leads to occupying a large physical layout area in the non-volatile memory. Lost memory needs to be miniaturized today, which is an urgent problem to be solved.

Contents of the invention

A circuit for reading data and a method for reading data provided by the present invention solve the problem that the physical layout area is too large due to the huge number of sa and latch, and also solve the problem that sa cannot work at the same time during datapath data output The problem.

In order to solve the above technical problems, an embodiment of the present invention provides a circuit for reading data, the circuit is applied to a non-volatile memory, the non-volatile memory includes a storage unit, and the circuit includes: a sense amplifier, a latch device, a latch management module, a logic circuit, and a data output module, the number of the sense amplifiers and the number of the latches are respectively integer multiples of the number of data output by the data output module;

The logic circuit is respectively connected to the bit line of the storage unit and the sense amplifier, and is used to select a plurality of bit lines according to the number of the sense amplifiers, and the number of the plurality of bit lines is related to the sensitive amplifier. The number of amplifiers is equal;

The sensitive amplifier is respectively connected to the logic circuit and the latch, and is used to read the data on the plurality of bit lines according to a first working timing signal, the first working timing signal being the sensitive amplifier. The amplifier reads the working signal of the data operation;

The latch is connected to the sense amplifier and the latch management module respectively, and is used to latch the data read by the sense amplifier, and transmit the latched data to the latch management module ;

The latch management module is connected to the latch and the data output module respectively, and is used to transmit the received data to the data output module according to the second working sequence signal, and the second working sequence signal The signal is a working signal for the latch management module to perform data transmission operations;

The data output module is connected with the latch management module, and is used for outputting received data.

Optionally, the non-volatile memory further includes: a control module;

The control module is respectively connected to the sense amplifier and the latch management module, and is used to send the first working sequence signal to the sense amplifier, and send the first working sequence signal to the latch management module. Two working timing signals.

Optionally, when the first operating timing signal is at a high level, the sense amplifier reads data from the plurality of bit lines, and transmits the read data to the latch through the latch In the memory management module;

When the second working timing signal is at a high level, the latch management module transmits the received data to the data output module, so that the data output module outputs the received data.

Optionally, the number of data output by the data output module is 16, and the numbers of the sense amplifiers and the latches are integer multiples of 16, respectively.

Optionally, during the period when the second working timing signal is at high level, if the first working timing signal is at high level, the sense amplifier continues to read the next set of bits from the plurality of bit lines. data.

The embodiment of the present invention also proposes a non-volatile memory, which includes: a control module and any of the circuits for reading data described above, and the control module is connected to the circuit for reading data .

The embodiment of the present invention also proposes a method for reading data, the method is applied to any of the above-mentioned circuits for reading data, and the method includes:

The sense amplifier receives the first working sequence signal sent by the control module;

If the first working timing signal is at a high level, the sense amplifier sends a read data request to the logic circuit;

During the high level period of the first working timing signal, the logic circuit selects a plurality of bit lines according to the number of the sense amplifiers according to the read data request, and the number of the plurality of bit lines is the same as The number of the sense amplifiers is equal, and the bit line numbers of the plurality of bit lines are sent to the sense amplifiers;

During the period when the first working timing signal is at a high level, the sense amplifier receives the bit line number;

During the high level period of the first working timing signal, the sense amplifier reads the data on the bit line corresponding to the bit line number according to the bit line number, and transmits the read data to the lock memory;

During the period when the first working timing signal is at a high level, the latch latches the data read by the sense amplifier, and transmits the latched data to the latch management module;

The latch management module receives the second working sequence signal sent by the control module;

If the second working timing signal is at a high level, the latch management module transmits the received data to the data output module;

During the period when the second working timing signal is at a high level, the data output module outputs the received data.

Optionally, after the sense amplifier receives the first working timing signal sent by the control module, the method further includes:

If the first working timing signal is at low level, the sense amplifier does not send the read data request to the logic circuit.

Optionally, after the latch management module receives the second working timing signal sent by the control module, the method further includes:

If the second working timing signal is at low level, the latch management module does not transmit the received data to the data output module.

Optionally, when the second working timing signal is at a high level, the data output module outputs received data, including:

During the period when the second working timing signal is at high level, if the first working timing signal is at high level, then during the period when the first working timing signal is at high level, the sense amplifier continues to The logic circuit sends a new read data request, finishes reading the new data and transfers the newly read data to the latch, and the latch transfers the newly received data to the latch server management module.

Compared with the prior art, the present invention provides a circuit for reading data and a method for reading data, reducing the number of sense amplifiers and latches on the circuit, and outputting data according to the integer even number of the data output module The number of settings is doubled, and the latch management module and logic circuit are added to realize that according to the working sequence signal, the logic circuit selects bl according to the number of sensitive amplifiers when reading, and then the sensitive amplifier reads the data and transmits it to the latch The management module manages the read data through the latch management module. When the data needs to be output, it transmits the data to the data output module according to another working sequence signal for data output without interfering with each other. The circuit for reading data and the method for reading data provided by the present invention improve the working efficiency of the non-volatile memory and greatly reduce the physical layout occupied by sa and latch.

Description of drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the accompanying drawings that need to be used in the description of the embodiments of the present invention. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention , for those skilled in the art, other drawings can also be obtained according to these drawings without paying creative labor.

FIG. 1 is a schematic diagram of a circuit for reading data inside an existing nonvolatile memory;

Fig. 2 is the schematic diagram of reading data circuit in the embodiment of the present invention;

Fig. 3 is t1 and t2 working sequence chart in the embodiment of the present invention;

4 is a schematic diagram of a non-volatile memory in an embodiment of the present invention;

Fig. 5 is a flowchart of a method for reading a circuit in an embodiment of the present invention.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

Referring to FIG. 2 , a schematic diagram of a circuit for reading data is shown, the circuit is applied to a non-volatile memory, and the non-volatile memory includes a storage unit 10, and the circuit for reading data may specifically include:

Logic circuit 20 (logic in the figure), sense amplifier 30 (SA0-SAx in the figure), latch 40 (latch0-latchx in the figure), latch management module 50 (Latch_path), and data output module 60 (datapath) , the number of sense amplifiers 30 and the number of latches 40 are integer multiples of the number of data output by the data output module 60, for example, the data output mode of the data output module 60 in the embodiment of the present invention is to use 16 data For data output in units, the number of sense amplifiers 30 and the number of latches 40 can be respectively set to 16, or 32, or 64, or 128, etc., which can be set according to user requirements.

The logic circuit 20 is connected with the bl of the storage unit and the sense amplifier 30 respectively, and is used to select a plurality of bl according to the number of the sense amplifier 30. For example, if there are 32 sense amplifiers, then the logic circuit 20 selects 32 bl at a time, so that the sense amplifiers Amplifier 30 carries out data reading, and sense amplifier 30 is connected with logic circuit 20 and latch 40 respectively, is used for according to the first working sequence signal (t1 in the figure), reads the data on a plurality of b1 selected by logic circuit 20, The latch 40 is connected with the sense amplifier 30 and the latch management module 50 respectively, and is used to latch the data read by the sense amplifier 30, and transmit the read data to the latch management module 50, the latch management module 50 is respectively connected with the latch 40 and the data output module 60, and is used to transmit the received read data to the data output module 60 according to the second working timing signal (t2 in the figure), and accept the newly read data, The data output module 60 is connected with the latch management module 50 for outputting the received data.

Optionally, referring to FIG. 2 , the nonvolatile memory further includes: a control module 70, which is connected to the sense amplifier 30 and the latch management module 50 respectively, and is used to send the first working timing signal t1 to the sense amplifier 30, Send the second operating timing signal t2 to the latch management module 50, when t1 is high level, the sense amplifier 30 reads data from the b1 of the storage unit, and the data read is transmitted to the latch by the latch 40 In the latch management module 50, when t2 is a high level, the latch management module 50 transmits the read data to the data output module 60, and the data output module 60 outputs the read data, and at t2 is a high level In a flat time period, if t1 is also at a high level, the sense amplifier 30 continues to read the next set of data from the b1 of the storage unit.

For example, referring to the timing diagram of t1 and t2 shown in Figure 3, during the read operation, sa receives the signal of t1, and during the high level time period of t1, sa sends a request signal for reading data to logic, and logic follows The number of sa, select 32 bls and give them to the sense amplifiers SA0~SA31, SA0~SA31 first read the data in the corresponding storage unit through bl, and send it to latch0~latch31, and then latch0~latch31 will read the data The data is transmitted to Latch_path, and Latch_path receives the signal of t2. During the high level time period of t2, Latch_path transmits the read data to datapath, and datapath outputs the read data in 16 data modes of Q<15:0>, At the same time, in the high level time period of t2, if SA0~SA31 receives the high level of t1 again, then in the high level time period of t1, SA0~SA31 can read data from the next group of 32 bls , whether t1 and t2 are high at the same time, or when the high levels of t1 and t2 are different, the work of SA0~SA31 and the work of Latch_path are carried out separately without affecting each other, because there are 32 SAs and latches respectively. There are only 64 in total, so while improving the working efficiency of the non-volatile memory, it also greatly reduces the physical layout area occupied by SA and latch.

Optionally, referring to FIG. 4, a schematic diagram of a non-volatile memory in an embodiment of the present invention is shown, and the non-volatile memory includes: a control module and any circuit for reading data described above, and the control module and the circuit for reading data circuit connection.

According to the above circuit for reading data, referring to FIG. 5, the embodiment of the present invention also proposes a method for reading the circuit, which may specifically include the following process:

Step 101: The sense amplifier receives the first working timing signal sent by the control module.

In the embodiment of the present invention, SA0-SA31 receive the first working timing signal t1 sent by the control module, which is a timing signal with periodic high and low level changes. This embodiment of the present invention does not limit it in detail, and it can be set according to actual conditions.

Step 102a: If the first working timing signal is at a high level, the sense amplifier sends a data read request to the logic circuit.

In the embodiment of the present invention, if t1 received by SA0-SA31 is a high-level signal, a request for reading data is sent to logic, and the high-level state will last for a preset time. This embodiment of the present invention does not limit it in detail, and it can be set according to actual conditions.

Step 102b: If the first working timing signal is at low level, the sense amplifier does not send a read data request to the logic circuit.

In the embodiment of the present invention, if the t1 received by SA0~SA31 is a low-level signal, no request to read data is sent to the logic, and no other operations are performed. Similarly, the low-level state will continue to be reserved. set time. This embodiment of the present invention does not limit it in detail, and it can be set according to actual conditions.

Step 103: During the high level period of the first working sequence signal, the logic circuit selects a plurality of bit lines according to the number of sense amplifiers according to the read data request, and the number of the plurality of bit lines is equal to the number of sense amplifiers, And send the bit line number of the plurality of bit lines to the sense amplifier.

In the embodiment of the present invention, during the continuous period of t1 high level, logic selects 32 BLs according to the received data read request. It should be noted that the selected 32 BLs do not necessarily have bit numbers 0-32 bl, it may also be 2~34 bl, only need to be 32, not in order, if you select 0~32 this time, then when you choose next time, you will no longer select 0~32, but select the rest bl until the data is read. After logic selects bl, it sends the bit number of bl to SA0~SA31. This embodiment of the present invention does not limit it in detail, and it can be set according to actual conditions.

Step 104: During the high level period of the first working timing signal, the sense amplifier receives the bit line number.

In the embodiment of the present invention, during the continuous period of t1 high level, SA0-SA31 will receive the bit number of bl sent by logic, so SA0-SA31 will know which data of the storage units on bl are read. This embodiment of the present invention does not limit it in detail, and it can be set according to actual conditions.

Step 105: When the first working timing signal is at high level, the sense amplifier reads the data on the bit line corresponding to the bit line number according to the bit line number, and transmits the read data to the latch.

In the embodiment of the present invention, during the continuous period of the high level of t1, SA0-SA31 perform a read operation according to the bit number of b1, read out the data in the storage unit on the bit line corresponding to the bit number of b1, and Transfer the read data to latch0~latch31. It should be noted that when performing a data read operation, depending on the address of the data to be read, there may be a bl that does not need to be read. For the storage unit, according to the regulations of the non-volatile memory, the sense amplifier still needs to read all bls, but there is no data in some bls to be read. This embodiment of the present invention does not limit it in detail, and it can be set according to actual conditions.

Step 106: During the period when the first working timing signal is at a high level, the latch latches the data read by the sense amplifier, and transmits the latched data to the latch management module.

In the embodiment of the present invention, during the continuation period of t1 high level, latch0-latch31 latches the received data read from SA0-SA31 to ensure that the data will not be lost, and play the role of temporary storage, and then store the data The data read from SA0~SA31 is transferred to Latch_path. This embodiment of the present invention does not limit it in detail, and it can be set according to actual conditions.

Step 107: The latch management module receives the second working sequence signal sent by the control module.

In the embodiment of the present invention, Latch_path50 receives the data read by SA0~SA31, but does not operate on the data immediately, but operates according to the enable signal of the control module, and Latch_path will receive the first data sent by the control module. Two working timing signal t2. This embodiment of the present invention does not limit it in detail, and it can be set according to actual conditions.

Step 108a: If the second working timing signal is at high level, the latch management module transmits the received data to the data output module.

In the embodiment of the present invention, if t2 is at a high level, the Latch_path transmits the received data to the datapath during the period of the high level. This embodiment of the present invention does not limit it in detail, and it can be set according to actual conditions.

Step 108b: If the second working timing signal is at low level, the latch management module does not transmit the received data to the data output module.

In the embodiment of the present invention, if t2 is at a low level, the Latch_path does not transmit the received data to the datapath. This embodiment of the present invention does not limit it in detail, and it can be set according to actual conditions.

Step 109: During the period when the second working timing signal is at a high level, the data output module outputs the received data.

In the embodiment of the present invention, the datapath outputs the received data during the period when t2 continues to be at a high level. , so the datapath needs to be output twice in a row before the data output of this time can be completed. This embodiment of the present invention does not limit it in detail, and it can be set according to actual conditions.

Optionally, during the high level period of the second working sequence signal, if the first working sequence signal is high level, then the sense amplifier continues to send a new read signal to the logic circuit during the high level period of the first working sequence signal. Get the data request, finish reading new data and transmit the newly read data to the latch, and the latch transmits the newly received data to the latch management module.

During the period of continuous high level of t2, if t1 is also within the period of continuous high level, SA0~SA31 will continue to send new read data requests to logic, which will make logic select bl again, and repeat the above process, Read out new data and transmit it to Latch_path, and Latch_path waits for t2 to be high again, and then transmits the new data to datapath. Repeating this can achieve a pipeline-like working process, which greatly improves the read data work efficiency.

For example, assuming a data read operation, at this moment t1 and t2 are both high level, then SA0~SA31 sends a request to read data to logic, and Latch_path transmits data to datapath, but there is no data in Latch_path at this moment, Therefore, no data is transmitted to the datapath. During the continuous high level period of t1, logic selects the bl of the bit line number 0~32, and sends 0~32 to SA0~SA31. SA0~SA31 read according to the bit line number 0~32. Fetch the data in the storage unit on the bl corresponding to No. 0~32, assuming that there are all data, then there are 32 data to be read, SA0~SA31 respectively send the read data to the respective corresponding latch0~latch31, latch0 ~latch31 locks and saves the data to ensure that the data will not be lost or missed, and then transmits the data to Latch_path. At this time, t1 becomes low level, and SA0~SA31, logic20 and latch0~latch31 stop working.

Latch_path receives the above data, assuming that the level of t2 is low at this time, then Latch_path does not perform any operation, but temporarily latches the received data, assuming that the level of t2 is still high at this time, then at t2 During the continuous high level period, Latch_path transmits the data read from SA0~SA31 to datapath. After datapath receives the data, it outputs 16 data at a time, and performs two operations on the 32 data read from SA0~SA31. Output, to complete the entire data output process.

Assuming that during the high level period of t2, t1 changes from low level to high level again, then SA0~SA31, logic and latch0~latch31 start to repeat the above steps of data reading. At this moment, SA0~SA31, logic and Latch0~latch31 reads the data and finally transmits it to Latch_path. At the same time, datapath is also working, outputting the 32 data read last time. The process of reading and outputting is not affected by each other. The above process is repeated, resulting in a similar The pipelined working process improves the efficiency of non-volatile memory reading data. The optimal situation is that t2 is a continuous high level period, and the datapath outputs the current read data, and t2 is a continuous low level period, SA0 ~SA31, logic and latch0~latch31 complete the next data read operation and transmit it to Latch_path, which is the most efficient.

Through the above embodiments, the present invention greatly reduces the occupied physical layout area by setting the number of sense amplifiers and latches as an even multiple of the number of output data of the output module, and utilizes two new logic and Latch_path The booster circuit performs its own work between the high and low levels of the timing of t1 and t2 without affecting each other, which improves the working efficiency of the read operation.

Finally, it should also be noted that in this text, relational terms such as first and second etc. are only used to distinguish one entity or operation from another, and do not necessarily require or imply that these entities or operations, any such actual relationship or order exists. Also, herein, the term "comprises," "comprising," or any other variation thereof, is intended to encompass a non-exclusive inclusion such that a process, method, article, or apparatus that includes a set of elements includes not only those elements, but also includes none. other elements specifically listed, or also include elements inherent in such a process, method, article, or device. Without further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus comprising that element.

Embodiments of the present invention have been described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementations, and the above-mentioned specific implementations are only illustrative, rather than restrictive, and those of ordinary skill in the art will Under the enlightenment of the present invention, many forms can also be made without departing from the gist of the present invention and the protection scope of the claims, and these all belong to the protection of the present invention.

Claims (10)

1. A circuit for reading data, characterized in that, the circuit is applied to a non-volatile memory, and the non-volatile memory includes a storage unit, and the circuit includes: a sense amplifier, a latch, a latch management modules, logic circuits, and data output modules, the number of the sense amplifiers and the number of the latches are respectively integer multiples of the number of data output by the data output module, and the number of the sense amplifiers equal to the number of the latches; The logic circuit is respectively connected to the bit line of the storage unit and the sense amplifier, and is used to select a plurality of bit lines according to the number of the sense amplifiers, and the number of the plurality of bit lines is related to the sensitive amplifier. The number of amplifiers is equal; The sensitive amplifier is respectively connected to the logic circuit and the latch, and is used to read the data on the plurality of bit lines according to a first working timing signal, the first working timing signal being the sensitive amplifier. The amplifier reads the working signal of the data operation; The latch is connected to the sense amplifier and the latch management module respectively, and is used to latch the data read by the sense amplifier, and transmit the latched data to the latch management module ; The latch management module is connected to the latch and the data output module respectively, and is used to transmit the received data to the data output module according to the second working sequence signal, and the second working sequence signal The signal is a working signal for the latch management module to perform data transmission operations; The data output module is connected to the latch management module for outputting received data; Wherein, the sense amplifier and the latch management module work independently according to the first working timing signal and the second working timing signal respectively. 2. The circuit according to claim 1, wherein the non-volatile memory further comprises: a control module; The control module is respectively connected to the sense amplifier and the latch management module, and is used to send the first working sequence signal to the sense amplifier, and send the first working sequence signal to the latch management module. Two working timing signals. 3. The circuit according to claim 2, wherein when the first operation timing signal is at a high level, the sense amplifier reads data from the plurality of bit lines, and converts the read data transmitted to the latch management module through the latch; When the second working timing signal is at a high level, the latch management module transmits the received data to the data output module, so that the data output module outputs the received data. 4. The circuit according to claim 1, wherein the number of data output by the data output module is 16, and the numbers of the sense amplifiers and the latches are integer multiples of 16, respectively. 5. The circuit according to claim 3, characterized in that, during the period when the second working timing signal is at a high level, if the first working timing signal is at a high level, then the sense amplifier continues to operate from the Read the next group of data on the plurality of bit lines. 6. A non-volatile memory, comprising: a control module and the circuit for reading data according to any one of claims 1-5, the control module being connected to the circuit for reading data. 7. A method for reading data, characterized in that the method is applied to the circuit for reading data according to any one of claims 1-5, the method comprising: The sense amplifier receives the first working sequence signal sent by the control module; If the first working timing signal is at a high level, the sense amplifier sends a read data request to the logic circuit; During the high level period of the first working timing signal, the logic circuit selects a plurality of bit lines according to the number of the sense amplifiers according to the read data request, and the number of the plurality of bit lines is the same as The number of the sense amplifiers is equal, and the bit line numbers of the plurality of bit lines are sent to the sense amplifiers; During the period when the first working timing signal is at a high level, the sense amplifier receives the bit line number; During the high level period of the first working timing signal, the sense amplifier reads the data on the bit line corresponding to the bit line number according to the bit line number, and transmits the read data to the lock memory; During the period when the first working timing signal is at a high level, the latch latches the data read by the sense amplifier, and transmits the latched data to the latch management module; The latch management module receives the second working sequence signal sent by the control module; If the second working timing signal is at a high level, the latch management module transmits the received data to the data output module; During the period when the second working timing signal is at a high level, the data output module outputs the received data. 8. The method according to claim 7, wherein, after the sense amplifier receives the first working timing signal sent by the control module, the method further comprises: If the first working timing signal is at low level, the sense amplifier does not send the read data request to the logic circuit. 9. The method according to claim 7, characterized in that, after the latch management module receives the second working sequence signal sent by the control module, the method further comprises: If the second working timing signal is at low level, the latch management module does not transmit the received data to the data output module. 10. The method according to claim 7, characterized in that, during the period when the second working timing signal is at a high level, the data output module outputs the received data, comprising: During the period when the second working timing signal is at high level, if the first working timing signal is at high level, then during the period when the first working timing signal is at high level, the sense amplifier continues to The logic circuit sends a new read data request, finishes reading the new data and transfers the newly read data to the latch, and the latch transfers the newly received data to the latch server management module.

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