CN111489960B

CN111489960B - Semiconductor structure and forming method thereof

Info

Publication number: CN111489960B
Application number: CN201910071787.3A
Authority: CN
Inventors: 舒强; 张迎春; 覃柳莎
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2019-01-25
Filing date: 2019-01-25
Publication date: 2023-11-10
Anticipated expiration: 2039-01-25
Also published as: CN111489960A

Abstract

A semiconductor structure and method of forming the same, the method comprising: providing a substrate, wherein the substrate comprises a first graph area, a second graph area and an auxiliary area, and the size of a target graph formed in the first graph area is smaller than that of a target graph formed in the second graph area; forming a first mask pattern on the substrate of the first pattern region and the auxiliary region; forming a second mask pattern on the substrate of the second pattern region and the auxiliary region after forming the first mask pattern, wherein the second mask pattern covers the first mask pattern in the auxiliary region; and etching the substrate by taking the first mask pattern and the second mask pattern as masks to form a target pattern. In the embodiment of the invention, the uniformity of the target patterns formed in the first pattern area and the second pattern area is improved, and the performance uniformity of the device are correspondingly improved.

Description

Semiconductor structure and forming method thereof

Technical Field

The present disclosure relates to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.

Background

In the formation of semiconductor devices, it is necessary to form gate structures of different sizes on a substrate. In the gate structure layout in the prior art, the large-sized pattern is divided into a large-sized pattern and a small-sized pattern according to the size of the gate structure, the large-sized pattern is generally formed by combining photolithography and etching processes, and the small-sized pattern is generally formed by a self-aligned double patterning (SADP) process.

However, the device performance and performance uniformity of the devices formed by the prior art are to be improved.

Disclosure of Invention

The embodiment of the invention provides a semiconductor structure and a forming method thereof, which are used for improving the performance and uniformity of a device.

The invention provides a method for forming a semiconductor structure, which comprises the following steps: providing a substrate, wherein the substrate comprises a first graph area, a second graph area and an auxiliary area, and the size of a target graph formed in the first graph area is smaller than that of a target graph formed in the second graph area; forming a first mask pattern on the substrate of the first pattern region and the auxiliary region; forming a second mask pattern on the substrate of the second pattern region and the auxiliary region after forming the first mask pattern, wherein the second mask pattern covers the first mask pattern in the auxiliary region; and etching the substrate by taking the first mask pattern and the second mask pattern as masks to form a target pattern.

Correspondingly, the invention also provides a semiconductor structure, which comprises: the substrate comprises a first graph area, a second graph area and an auxiliary area, wherein the size of a target graph formed in the first graph area is smaller than that of a target graph formed in the second graph area; a first mask pattern on the substrate of the first pattern region and the auxiliary region; and a second mask pattern on the substrate of the second pattern region and the auxiliary region, wherein the second mask pattern covers the first mask pattern in the auxiliary region.

Compared with the prior art, the technical scheme of the invention has the following advantages:

in the embodiment of the invention, the first mask pattern is formed in the first pattern area and the auxiliary area at the same time, so that the pattern density of the first mask pattern is increased, the etching load effect is avoided, the first mask pattern with good uniformity is formed, and then the small-size target pattern with good uniformity is formed, and when the second mask pattern is formed in the second pattern area, the second mask pattern capable of covering the first mask pattern is formed in the auxiliary area at the same time, the pattern density of the second mask pattern is increased, so that the etching load effect is avoided, the second mask pattern with good uniformity is formed, and then the large-size target pattern with good uniformity is formed, and the uniformity of the target patterns formed in the first pattern area and the second pattern area is better, and the device performance and the performance uniformity are correspondingly improved.

Drawings

FIG. 1 is a diagram of a mask pattern layout structure;

FIG. 2 is a diagram of another mask pattern layout structure;

fig. 3 to 15 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Detailed Description

As known from the background art, the performance and uniformity of devices formed by the prior art still need to be improved. The reason why the device performance is to be improved is now analyzed in conjunction with a method of forming a semiconductor structure.

Specifically, in the process of forming the gate structure, different sizes of mask patterns are formed through different processes, for example, referring to a mask pattern layout structure diagram shown in fig. 1, a small-size mask pattern 101 is formed in the GM region I through a self-aligned double patterning (self-aligned double patterning, SADP) process, a large-size mask pattern 102 is formed in the GT region II through a photolithography and etching process, and then the two mask patterns are used as masks to form the gate structure with corresponding sizes through etching. However, in the process of forming mask patterns with different sizes, the pattern density is low, so that an etching load effect is caused, and the uniformity of a target pattern formed by etching is poor.

Currently, in order to improve the uniformity of the large-size pattern 102, a plurality of auxiliary areas III are generally divided on the substrate, and large-size auxiliary patterns 103 are simultaneously formed in the auxiliary areas III to improve the pattern density and further improve the uniformity of the large-size pattern.

However, this method can only improve the uniformity of large-sized patterns.

In another method, referring to another mask pattern layout structure diagram shown in fig. 2, the large-sized auxiliary pattern 103 and the small-sized auxiliary pattern 104 are simultaneously formed in the auxiliary region III, but it is difficult to simultaneously satisfy pattern density requirements of the large-sized pattern and the small-sized pattern due to the limited area of the auxiliary region III, so that uniformity of the large-sized pattern and the small-sized pattern cannot be simultaneously improved.

Based on the above, in the embodiment of the invention, the first mask pattern is formed in the first pattern area and the auxiliary area at the same time, so that the pattern density of the first mask pattern is increased, and the first mask pattern with good uniformity is formed; and when the second mask pattern is formed in the second pattern area, the second mask pattern capable of covering the first mask pattern is formed in the auxiliary area at the same time, the pattern density of the second mask pattern is increased, and the second mask pattern with good uniformity is formed, so that the first mask pattern and the second mask pattern are further used as masks, and a target pattern with good uniformity is formed, and therefore device performance and performance uniformity are improved.

In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.

Referring to fig. 3, a substrate is provided, the substrate including a first pattern region I, a second pattern region II, and an auxiliary region III, a target pattern size formed in the first pattern region I being smaller than a target pattern size formed in the second pattern region II.

The substrate is used for providing a process foundation for forming a target pattern subsequently.

In this embodiment, the base includes a substrate 200, and a corresponding layer structure may be formed on the substrate 200 through a patterning process, a deposition process, an epitaxy process, and the like.

In this embodiment, the material of the substrate 200 is silicon. In other embodiments, the material of the substrate may be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be a silicon substrate on an insulator or other types of substrates such as a germanium substrate on an insulator, which may be selected by those skilled in the art according to actual needs.

In other embodiments, the substrate may further include a first semiconductor layer for providing a process basis for subsequently forming the substrate and a second semiconductor layer epitaxially grown on the first semiconductor layer for providing a process basis for subsequently forming a specific device structure.

In this embodiment, the base further includes a gate material layer 210 formed on the substrate 200, where the gate material layer 210 is used to provide a process base for forming a gate structure later, and the gate structure is formed by a subsequent etching process. The gate material layer may be silicon (Si), titanium nitride (TiN), titanium (Ti), tantalum nitride (TaN), cobalt (Co), tungsten (W), or a stack of a plurality of the above materials. In this embodiment, the gate material layer may be specifically polysilicon.

In this embodiment, the substrate further includes a Hard Mask (HM) material layer 220 formed on the gate material layer 210, where the hard mask material layer 220 is used to provide a process basis for forming a patterned hard mask layer later. Wherein the hard mask layer is used as a mask for subsequent etching of the gate material layer 210. The hard mask material layer 220 may be silicon nitride (SiN), silicon oxide (SiO) ₂ ) Silicon oxynitride (SiON), silicon oxycarbide (SiOC), amorphous carbon (a-C), silicon oxycarbonitride (SiOCN), or a stack thereof. In this embodiment, the hard mask material layer 220 is a silicon oxide layer.

It should be noted that in other embodiments, the substrate may further include a substrate and other functional material layers located on the substrate, such as a passivation layer, an isolation layer, a metal electrode layer, and the like, where in the step of patterning the substrate, the functional material layer is patterned to form a corresponding functional layer.

With continued reference to fig. 3, the substrate is divided into a first pattern area I, a second pattern area II and an auxiliary area III, wherein different pattern areas are used to form target patterns with different sizes, and specifically, the size of the target pattern formed in the first pattern area I is smaller than that of the target pattern formed in the second pattern area II. Where the size range of the target pattern is large, the target patterns with different sizes need to be formed by different processes, for example, when the feature size and the pitch of the target pattern are large, the process of photolithography and etching may be considered, and when the feature size and the pitch of the target pattern are small, the process of self-aligned double patterning (self-aligned double patterning, SADP) may be considered. Therefore, the process corresponding to the target pattern can be determined according to the feature size and the spacing of the target pattern, and then the region adopting the same process is divided into one region, and the region adopting different processes is divided into different regions. In this embodiment, the substrate is divided into a first pattern region I requiring the SADP process and a second pattern region II requiring the photolithography and etching process.

It should be noted that, the standard corresponding to the different dividing regions may be selected according to the actual process requirement, for example, the first pattern region I and the second pattern region II are divided by using 10nm as a boundary, and when the feature size and/or the pitch of the target pattern is greater than 10nm, photolithography and etching processes are adopted, and the corresponding region is the second pattern region; when the feature size and/or the spacing of the target pattern is less than or equal to 10nm, adopting an SADP process, wherein the corresponding region is a first pattern region; or, dividing by using smaller or larger size standard as boundary under different process conditions, such as 8nm, 7nm, 5nm,12nm, 13nm, 15nm, etc.; alternatively, to ensure the continuity of the regions, the first pattern region and the second pattern region are divided by a numerical range, for example, a region corresponding to a target pattern in a smaller region (< 7 nm) outside the range is a first pattern region, a region corresponding to a target pattern in a larger region (> 15 nm) is a second pattern region, and a target pattern in the size range (7-15 nm) is divided by an adjacent region, and if the adjacent region is a second pattern region, the second pattern region is divided, and if the adjacent region is a first pattern region, the first pattern region is divided.

In this embodiment, the first pattern area I is used to form a gate structure with a feature size and/or a pitch of the target pattern smaller than or equal to 10nm, and the second pattern area II is used to form a gate structure with a feature size and/or a pitch of the target pattern larger than 10 nm.

Generally, the first pattern area I occupies about 20% of the total area of the substrate, and has a small pattern density, so that an etching loading effect is very easy to occur, so that uniformity of a formed mask is poor, and uniformity of a finally formed target pattern is poor.

The auxiliary area III is an area adjacent to the first pattern area I and the second pattern area II in the substrate, and the area is an area of the substrate where a grid structure is not required to be formed and is used for forming mask patterns with the first pattern area I and the second pattern area II at the same time, so that pattern density is improved, etching load effect is avoided, and finally, a pattern structure with good uniformity is formed. The patterned structure formed in assist region III may be removed after the gate structure formation process is completed, may be removed in other steps, or may remain in the final structure of the device in some designs.

It should be noted that the first graphic region I, the second graphic region II, and the auxiliary region III may be a continuous region or may be a plurality of discrete regions, and the present invention is not limited in detail herein.

Referring to fig. 4 to 10 in combination, a first mask pattern 202 (shown in fig. 10) is formed on the substrate of the first pattern region I and the auxiliary region III.

The first mask pattern 202 is used as an etching mask for forming a target pattern in the first pattern region I later.

In the embodiment of the invention, the first mask patterns are formed in the first pattern area I and the auxiliary area III at the same time, and the pattern density of the first mask patterns is increased, so that the etching load effect is avoided, the first mask patterns with good uniformity are formed, and the small-size target patterns with good uniformity are formed.

In this embodiment, the target pattern subsequently formed in the first pattern region I has a smaller size, and thus the first mask pattern is formed using the SADP process.

The step of forming the first mask pattern will be described in detail with reference to the accompanying drawings.

Referring to fig. 4 and 5 in combination, a plurality of discrete core layers 201 are formed on the substrate of the first pattern region I and the auxiliary region III, wherein fig. 4 is a top view and fig. 5 is a cross-sectional view of fig. 4 along the AA1 dividing line.

The core layer 201 is used to provide a process basis for forming a first mask pattern layer that patterns the substrate.

In this embodiment, the core layer 201 is formed on the hard mask material layer 220.

It should be noted that, the core layer 201 is further removed later, so the etching selection of the materials of the core layer 201 and the hard mask material layer 220 is relatively large, and the material of the core layer 201 is a material that is easy to be removed, so that the damage of the process of removing the core layer 201 later to the hard mask material layer 220 is reduced.

Specifically, the material of the core layer 200 may be photoresist, amorphous carbon, organic dielectric layer (organic dielectric layer, ODL) material, dielectric anti-reflective coating (DARC) material, bottom anti-reflective coating (BARC) material, polysilicon or silicon oxide. In this embodiment, the material of the core layer 201 is photoresist, and a spin coating process and a photolithography process are used to form the core layer 201.

It should be noted that, the dimension of the core layer 201 along the normal direction of the substrate surface is the thickness of the core layer 201, and the thickness (not labeled) of the core layer 201 should not be too small or too large. When a pattern layer for patterning the substrate is formed subsequently, the height of the pattern layer along the normal direction of the surface of the substrate is determined by the thickness of the core layer 201, if the thickness of the core layer 201 is too small, the thickness of the pattern layer is correspondingly small, so that the pattern layer is easily insufficient as a mask for etching the substrate, and thus, when a target pattern is not formed, the pattern layer is completely etched; if the thickness of the core layer 201 is excessively large, the aspect ratio between adjacent core layers 201 increases, which tends to cause a decrease in the process window for the subsequent formation of the pattern layer, and also tends to reduce the formation quality of the pattern layer. For this purpose, in the present embodiment, the thickness of the core layer 201 is 5nm to 30nm.

In addition, for convenience of illustration, fig. 5 shows only one core layer 201 located in the first graphic region I and two core layers 201 located in the auxiliary region III.

Referring to fig. 6, a sidewall material layer 230 is formed conformally covering the substrate and core layer 201.

The sidewall material layer 230 is used to form a sidewall as a first mask pattern.

It should be noted that, the sidewall is required to be formed by an etching process in the following step, so that the etching selectivity of the materials of the sidewall material layer 230, the hard mask material layer 220 and the core layer 201 is relatively large, so as to reduce the damage of the subsequent etching process to form the sidewall to the hard mask material layer 220 and the core layer 201.

In addition, the sidewall formed by the sidewall material layer 230 is used as the first mask pattern to etch the target pattern, so the material of the sidewall material layer 230 should also be suitable for being used as a mask. Based on this, the etching selectivity of the sidewall material layer 230 and the substrate 200 is relatively large, so that the sidewall formed by the sidewall material layer 230 can function as an etching mask when the hard mask material layer 220 and the substrate 200 are patterned later.

In this embodiment, the material of the sidewall material layer 230 is silicon nitride. The hardness and the density of the silicon nitride material are higher, and the effect of an etching mask of a side wall formed later is improved by selecting the silicon nitride material. In other embodiments, the material of the sidewall material layer 230 may be one or more of amorphous germanium, silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon carbonitride or silicon carbonitride, depending on the materials of the core layer, the hard mask material layer and the substrate. When the side wall material layer is of a laminated structure, selecting the laminated structure formed by multiple materials of the materials as the side wall material layer.

In this embodiment, in order to improve the thickness uniformity of the sidewall material layer 230, so as to improve the uniformity of the sidewall width, an atomic layer deposition process is used to form the sidewall material layer; moreover, by adopting an atomic layer deposition process, the difficulty in controlling the thickness of the first side wall material layer is reduced. In other embodiments, the sidewall material layer 230 may also be formed by a chemical vapor deposition process.

Referring to fig. 7 and 8 in combination, a first mask pattern 202 having the same extension direction as the core layer 201 is formed on the sidewall of the core layer 201, wherein fig. 7 is a top view, and fig. 8 is a cross-sectional view taken along the AA1 cut line in fig. 7, and the sidewall material layer 230 is etched.

The first mask pattern 202 serves as an etch mask for a subsequently patterned substrate.

It should be noted that, the extending direction of the core layer 201 is a direction perpendicular to the AA1 direction on the substrate plane. Specifically, the step may include removing the sidewall material layer on the top of the substrate and the top of the core layer 201 by etching, and reserving a sidewall group surrounding the core layer 201, where it can be seen that the sidewall group surrounds the core layer, and includes a sidewall located on a sidewall of the core layer 201 and having a same extending direction as the core layer 201, and a sidewall connection portion 203 connected to the sidewall, where the sidewall is used as the first mask pattern 202.

In this embodiment, the material of the sidewall material layer 230 is silicon nitride, so the material of the first mask pattern 202 correspondingly formed is silicon nitride. In other embodiments, the material of the sidewall material layer 230 may be one or more of amorphous germanium, silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon carbonitride or silicon carbonitride. Correspondingly, the material of the first mask pattern is one or more of amorphous germanium, silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon carbonitride or silicon carbonitride oxide. When the side wall material layer is of a laminated structure, the formed first mask pattern is of the laminated structure.

In this step, an anisotropic maskless dry etching (mask dry etching) process is adopted to selectively etch the first sidewall material layer along the normal direction of the substrate surface, so as to retain the sidewall material layer surrounding the core layer 201, and form the sidewall group.

In this embodiment, the thickness (not labeled) of the core layer 201 is 5nm to 30nm along the normal direction of the substrate surface, and correspondingly, the height of the side wall group is 5nm to 30nm along the normal direction of the substrate surface.

The first mask pattern 202 is used to pattern the pattern layer of the substrate as a subsequent pattern, so that the width of the first mask pattern 202 along the AA1 direction is equal to the width of the target pattern formed subsequently along the direction.

In this embodiment, since the hard mask material layer 220 is used to provide a process basis for the subsequent formation of a hard mask layer, and the hard mask layer is used as a mask for the subsequent etching of the substrate 200, the width of the first mask pattern 202 along the AA1 direction is equal to the width of the subsequently formed gate structure.

Referring to fig. 9 and 10 in combination, the core layer 201 is removed (as shown in fig. 8), wherein fig. 9 is a top view and fig. 10 is a cross-sectional view of fig. 9 along line AA 1.

In this embodiment, in order to increase the removal rate of the core layer 201, a dry etching process is used to etch and remove the core layer 201.

After this step, the side wall connection portion 203 may be removed by etching. Specifically, the sidewall connection portion 203 is removed by an etching process. In other embodiments of the present invention, the sidewall connection portion 203 may be removed in a subsequent step, specifically, may be removed together with an unnecessary pattern generated during the formation of the second mask pattern after the subsequent formation of the second mask pattern, or may be removed together with an unnecessary pattern generated during the formation of the target pattern after the formation of the corresponding target pattern, specifically, may be selected according to an actual process situation, and the present invention is not limited herein specifically.

It should be noted that, in other embodiments of the present invention, the first mask pattern may be formed in other manners, for example, a self-aligned quad patterning (self-aligned quadruple patterning, SAQP) method, etc., and those skilled in the art may select the first mask pattern according to the actual process status.

Referring to fig. 11 to 13 in combination, after the first mask pattern 202 is formed, a second mask pattern 204 is formed on the substrate of the second pattern region II and the auxiliary region III, and the second mask pattern 204 covers the first mask pattern 202 in the auxiliary region III.

In this embodiment, the second mask pattern 204 is formed by using a photolithography and etching process, and in other embodiments of the present invention, the second mask pattern may be formed by using an SADP process when the first mask pattern is formed by using an SADP process.

In this step, the second mask pattern 204 in the auxiliary region III covers the first mask pattern 202. Since the first mask pattern 202 with good uniformity is formed on the substrate, the second mask pattern 204 covering the first mask pattern 202 is further formed in the auxiliary area III, and the pattern density of the second mask pattern 204 is further increased, so as to avoid the etching loading effect, form the second mask pattern 204 with good uniformity, further form the large-size target pattern with good uniformity, and correspondingly improve the device performance and performance uniformity.

The step of forming the second mask pattern 204 is described in detail below with reference to the accompanying drawings.

Referring to the cross-sectional view in fig. 11, a mask material layer 240 is formed on the substrate exposed by the first mask pattern 202, and the mask material layer 240 covers the first mask pattern 202.

The masking material layer 240 is used to provide a process basis for forming a second mask pattern that patterns the substrate.

In this embodiment, the mask material layer 240 is formed on the hard mask material layer 220 and covers the first mask pattern 202 on the hard mask material layer 220.

It should be noted that, the mask material layer 240 is etched later to form the second mask pattern, and the etching process needs to expose the first mask pattern 202 in the first pattern area I, so that the material etching selectivity of the mask material layer 240 to the hard mask material layer 220 and the first mask pattern 202 is relatively large, so as to reduce the damage to the hard mask material layer 220 and the first mask pattern 202 caused by the process of etching to form the second mask pattern. Specifically, in this embodiment, the material etching selectivity of the mask material layer 240 and the first mask pattern 202 is greater than 10, or, in a more preferred embodiment, the material etching selectivity of the mask material layer 240 and the first mask pattern 202 may be greater than 15, 20 or 30. In addition, when the second mask pattern formed by the mask material layer 240 is used for etching the subsequent gate structure and the dummy gate (dummy gate), the mask material layer 240 should have a larger material etching selectivity than the gate material layer 210, so as to reduce the etching process difficulty.

In this embodiment, the material of the mask material layer 240 may be silicon carbide. In other embodiments, the material of the mask material layer 240 may be one or more of amorphous germanium, silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon carbonitride or silicon oxycarbonitride, depending on the material of the first mask pattern and the hard mask material layer. When the mask material layer 240 is in a laminated structure, the laminated structure formed by a plurality of materials selected from the above materials is the mask material layer 240.

In this embodiment, the thickness of the mask material layer 240 is greater than the height of the first mask pattern 202, so that the mask material layer 240 covers the first mask pattern 202. That is, specifically, the thickness (not labeled) of the mask material layer 240 is 8nm to 35nm.

In this step, the mask material is filled into the exposed substrate of the first mask pattern 202 by a flowable chemical vapor deposition process. By using a flowable chemical vapor deposition process, the mask material can be sufficiently filled in the gaps between adjacent first mask patterns 202, thereby reducing void (void) defects within the mask material layer 240. In other embodiments, other types of deposition processes may also be selected.

Referring to fig. 12 and 13 in combination, the mask material layer 240 (as shown in fig. 11) is etched to form the second mask patterns 204 (including 204a and 204 b), and any one of the second mask patterns 204 in the auxiliary area III covers at least one of the first mask patterns 202. Fig. 12 is a plan view, and fig. 13 is a sectional view taken along line AA1 in fig. 12.

The second mask pattern 204 is used to pattern the substrate to provide a process basis.

In this embodiment, the number of the second mask patterns 204 covering the first mask patterns 202 may be determined according to the width (the dimension along the AA1 direction) of the second mask pattern 204 in the auxiliary area III, and when the width of the second mask pattern 204 may only cover one first mask pattern 202, the second mask pattern 204 covers one first mask pattern 202, as shown by a second mask pattern 204 a; when the width of the second mask pattern 204 is sufficient to cover two adjacent first mask patterns 202 and a gap between two adjacent first mask patterns 202, the second mask pattern 204 covers the two adjacent first mask patterns 202 as shown by a second mask pattern 204 b.

In other embodiments of the present invention, the second mask pattern may include only a type covering one sidewall or a type covering two sidewalls, which is not particularly limited herein. Alternatively, in other embodiments of the present invention, the second mask pattern may be further configured to cover 3 first mask patterns, 4 first mask patterns, or more first mask patterns according to the width of the second mask pattern, and the second mask pattern may be configured to be of a plurality of types according to different widths at the same time, which is not particularly limited.

When the second mask patterns 204 cover the two first mask patterns 202, specifically, as shown in the first mask patterns 204b in fig. 12, one second mask pattern 204b covers one sidewall group, that is, covers two sidewalls 202 (i.e., the first mask patterns) and two sidewall connecting portions 203 connecting the two sidewalls 202 at the same time, so as to simplify the process layout and avoid that too many redundant patterns are generated in the process of the invention to affect the layout of the gate structure.

Specifically, the width of the side wall group in the auxiliary area III along the AA1 direction (comprising the width of the side wall and the gap between the two side walls) is 80 nm-150 nm; in the step of forming the second mask pattern 204, the width of the second mask pattern 204a in the auxiliary area III is 25nm to 45nm, and thus, the second mask pattern 204a is disposed to cover one sidewall in the sidewall group. In the step of forming the second mask pattern 204, the width of the second mask pattern 204b in the auxiliary area III is 100nm to 200nm, and thus the second mask pattern 204b is disposed to cover the sidewall group.

In this step, the second mask pattern 204 may be formed by etching the mask material layer using a wet etching process or a dry etching process. Specifically, the step may include: a patterned mask is formed over the mask material layer 240, and the mask material layer 240 is etched under the mask to form the second mask pattern 204.

The second mask pattern 204 is etched by the mask material layer 240, so the material of the second mask pattern 204 is the material of the mask material layer 240, and in this embodiment, the material of the second mask pattern 204 is silicon carbide. In other embodiments, the second mask pattern 204 may correspond to one or more of amorphous germanium, silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon carbonitride, or silicon oxycarbonitride, depending on the material of the mask material layer 240. When the mask material layer 240 has a stacked structure, the second mask pattern 204 also has a stacked structure.

In this embodiment, the thickness of the second mask pattern 204 is the same as the thickness of the mask material layer 240, and specifically, when the thickness (not labeled) of the mask material layer 240 is 8nm to 35nm, the thickness of the corresponding second mask pattern 204 is also 8nm to 35nm.

When the second mask pattern is formed in the second pattern area II, a second mask pattern capable of covering the first mask pattern is formed in the auxiliary area III at the same time, so that the pattern density of the second mask pattern is increased, thereby avoiding the etching load effect, forming a second mask pattern with good uniformity, further forming a large-size target pattern with good uniformity, and accordingly, the uniformity of the target pattern formed in the second pattern area II is good, and the device performance and the performance uniformity are improved correspondingly.

In this embodiment, after the second mask pattern 204 is formed, a step of removing the unnecessary patterns formed during the formation of the first mask pattern 202 and the second mask pattern 204 may be further performed, and specifically, the irregular structures that may be formed due to the process at the end of the second mask pattern 204 (including the second pattern region II and the auxiliary region III) may be first removed; next, the sidewall connection portion 203 formed in the first mask pattern 202 (including the first pattern region I and the auxiliary region III) is removed so as to facilitate the subsequent formation of an accurate target pattern.

In other embodiments of the present invention, the step of removing the unnecessary pattern may be performed not but in other steps, for example, after the gate structure is formed, the unnecessary structure formed by the unnecessary pattern of the mask pattern is removed together in the step of removing the dummy gate.

Referring to fig. 14, the substrate is etched with the first mask pattern 202 and the second mask pattern 204 as masks, to form a target pattern.

Referring to fig. 13 in combination, in the present embodiment, in the step of providing a base, the base includes a substrate 200, a gate material layer 210 on the substrate, and a hard mask material layer 220 on the gate material layer; thus, the present step comprises: and etching the gate material layer 210 and the hard mask material layer 220 on the gate material layer by using the first mask pattern 202 and the second mask pattern 204 as masks, forming a gate structure 211 in the first pattern region I and the second pattern region II, and forming a dummy gate structure 211' in the auxiliary region III.

It should be noted that, the first mask pattern 202 and the second mask pattern 204 may be used as masks for etching the hard mask material layer 220 to form a patterned hard mask layer 221, and then, the first mask pattern 202 and the second mask pattern 204 are removed, and the patterned hard mask layer 221 is used as a mask for etching the gate material layer 210 to form a patterned gate structure 211 and a dummy gate structure 211'.

Alternatively, in another alternative, the first mask pattern 202 and the second mask pattern 204 may be used as masks for simultaneously etching the hard mask material layer 220 and the gate material layer 210, i.e., the first mask pattern 202 and the second mask pattern 204 are used as masks for etching the hard mask material layer 220 to form a patterned hard mask layer 221, and then the first mask pattern 202 and the second mask pattern 204 are used as masks for etching the gate material layer 210 to form a patterned gate structure, i.e., after the first pattern region I and the second pattern region II form the gate structure 211 and the auxiliary region III form the dummy gate structure 211', the first mask pattern 202 and the second mask pattern 204 are removed.

In the etching process of the hard mask material layer 220 and the gate material layer 210, a wet etching process or a dry etching process may be selected to perform etching according to the material of the hard mask material layer, which is not particularly limited herein. Because the materials of the hard mask material layer 220 and the gate material layer 210 are different, different etching modes can be adopted to perform corresponding etching, so as to obtain the target pattern.

In the embodiment of the invention, a first mask pattern is formed in the first pattern area I and the auxiliary area III at the same time, the pattern density of the first mask pattern is increased, and a first mask pattern with good uniformity is formed; and when the second mask pattern is formed in the second pattern area II, the second mask pattern capable of covering the first mask pattern is formed in the auxiliary area III at the same time, the pattern density of the second mask pattern is increased, the second mask pattern with good uniformity is formed, and further the first mask pattern and the second mask pattern are used as masks, so that the target pattern with good uniformity is formed, and therefore the device performance and performance uniformity are improved.

Compared with the original process, the method for forming the semiconductor structure provided by the embodiment of the invention only changes the process layout, and does not change the original process sequence, so that the process cost is not increased on the premise of improving the uniformity of the pattern.

Referring to fig. 15 in combination, in this embodiment, after forming the target pattern, the method further includes: the dummy gate structure 211' is removed.

Since the dummy gate structure 211 'is only an auxiliary structure, the dummy gate structure 211' should be removed when the auxiliary structure affects a subsequent device formation process.

In this embodiment, the dummy gate structure 211' may be removed through a photolithography and etching process. Specifically, a mask pattern exposing the auxiliary region III is formed by using a photolithography process, and an etching process is performed using the mask pattern as a mask to remove the dummy gate structure 211'.

In one embodiment of the present invention, a semiconductor structure is also provided. Referring to fig. 12 and 13 in combination, a schematic structural diagram of an embodiment of the semiconductor structure of the present invention is shown, wherein fig. 12 is a top view and fig. 13 is a cross-sectional view taken along line AA1 of fig. 12.

The semiconductor structure includes: the substrate comprises a first graph area I, a second graph area II and an auxiliary area III, and the size of a target graph formed in the first graph area I is smaller than that of a target graph formed in the second graph area II; a first mask pattern 202 on the substrate of the first pattern region I and the auxiliary region III; and a second mask pattern 204 on the substrate of the second pattern region II and the auxiliary region III, wherein the second mask pattern 204 covers the first mask pattern 202 in the auxiliary region III.

In this embodiment, as shown in fig. 13, the base includes a substrate 200, and a corresponding device structure may be formed on the substrate 200 through a patterning process, a deposition process, an epitaxy process, and the like. In this embodiment, the material of the substrate 200 is silicon. In other embodiments, the material of the substrate may be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be a silicon substrate on an insulator or other types of substrates such as a germanium substrate on an insulator, which may be selected by those skilled in the art according to actual needs.

The base further includes a gate material layer 210 formed on the substrate 200, where the gate material layer 210 is used to provide a process basis for the subsequent formation of a gate structure, and the gate structure is formed by a subsequent etching process. The gate material layer may be silicon (Si), titanium nitride (TiN), titanium (Ti), tantalum nitride (TaN), cobalt (Co), tungsten (W), or a stack of a plurality of the above materials. In this embodiment, the gate material layer may be specifically polysilicon.

Further, the substrate further comprises a gate materialA layer 220 of Hard Mask (HM) material on layer 210, the layer 220 of hard mask material being used to provide a process basis for the subsequent formation of a patterned hard mask layer 221 (shown in fig. 14). Wherein the hard mask layer 221 is used as a mask for subsequent etching of the gate material layer 210. The hard mask material layer 220 may be silicon nitride (SiN), silicon oxide (SiO) ₂ ) Silicon oxynitride (SiON), silicon oxycarbide (SiOC), amorphous carbon (a-C), silicon oxycarbonitride (SiOCN), or a stack thereof. In this embodiment, the hard mask material layer 220 is a silicon oxide layer.

Accordingly, the first mask pattern 202 and the second mask pattern 204 are both located on the hard mask material layer 220.

Referring to fig. 12 and 13, a substrate may be divided into a first pattern region I, a second pattern region II, and an auxiliary region III, wherein different pattern regions are used to form target patterns of different sizes, and in particular, the size of the target pattern formed in the first pattern region I is smaller than that of the target pattern formed in the second pattern region II. Where the size range of the target pattern is large, the target patterns with different sizes need to be formed by different processes, for example, when the feature size and the pitch of the target pattern are large, the process of photolithography and etching may be considered, and when the feature size and the pitch of the target pattern are small, the process of self-aligned double patterning (self-aligned double patterning, SADP) may be considered. Therefore, the process corresponding to the target pattern can be determined according to the feature size and the spacing of the target pattern, and then the region adopting the same process is divided into one region, and the region adopting different processes is divided into different regions. In this embodiment, the substrate is divided into a first pattern region I requiring the SADP process and a second pattern region II requiring the photolithography and etching process.

The auxiliary area III is an area adjacent to the first pattern area I and the second pattern area II in the substrate, and the area is an area of the substrate, which does not need to form a gate structure, and is used for forming mask patterns with the first pattern area I and the second pattern area II at the same time, so that the pattern density is improved, the etching load effect is avoided, and finally, the pattern structure with good uniformity is formed. The pattern structure formed in the auxiliary region III may be deleted after the gate structure forming process is completed, may be deleted in other steps, or may still remain in the Dummy region structure in the final structure of the device in some designs.

In this embodiment, the material of the first mask pattern may be selected from a silicon nitride material to enhance the effect of the etching mask of the first mask pattern. In other embodiments, the material of the sidewall (i.e., the first mask pattern) 202 may be one or more of amorphous germanium, silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon carbonitride or silicon carbonitride, depending on the material of the hard mask material layer and the substrate. When the side wall is of a laminated structure, the laminated structure formed by multiple materials of the materials is selected as the side wall structure.

The material etching selectivity of the second mask pattern 204 to the hard mask material layer 220 and the first mask pattern 202 is relatively large, so as to reduce damage to the hard mask material layer 220 and the first mask pattern 202 caused by the process of etching to form the second mask pattern. Specifically, in this embodiment, the material etching selectivity of the second mask pattern 204 and the first mask pattern 202 is greater than 10, or, in a more preferred embodiment, the material etching selectivity of the second mask pattern 204 and the first mask pattern 202 may be greater than 15, 20, or 30. In addition, when the second mask pattern 204 performs the subsequent etching of the gate structure and the dummy gate (dummy gate), the second mask pattern 204 should also have a larger material etching selectivity than the gate material layer 210, so as to reduce the etching process difficulty.

In this embodiment, the material of the second mask pattern 204 may be silicon carbide. In other embodiments, the material of the second mask pattern 204 may also be one or more of amorphous germanium, silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon carbonitride or silicon oxycarbonitride, depending on the materials of the first mask pattern and the hard mask material layer. When the second mask pattern 204 is a laminated structure, the laminated structure formed by a plurality of materials selected from the above materials is the structure of the second mask pattern 204.

In this embodiment, the number of the second mask patterns 204 covering the first mask patterns 202 may be determined according to the width (the dimension along the AA1 direction) of the second mask pattern 204 in the auxiliary area III, and when the width of the second mask pattern 204 may cover only one first mask pattern 202, the second mask pattern 204 covers one first mask pattern, as shown by a second mask pattern 204 a; when the width of the second mask pattern 204 is sufficient to cover two adjacent first mask patterns 202 and a gap between two adjacent first mask patterns 202, the second mask pattern 204 covers the two adjacent first mask patterns 202 as shown by a second mask pattern 204 b.

In the embodiment of the invention, a first mask pattern is formed in the first pattern area I and the auxiliary area III at the same time, the pattern density of the first mask pattern is increased, and a first mask pattern with good uniformity is formed; and when the second mask pattern is formed in the second pattern area II, the second mask pattern capable of covering the first mask pattern is formed in the auxiliary area III at the same time, the pattern density of the second mask pattern is increased, the second mask pattern with good uniformity is formed, and further the first mask pattern and the second mask pattern are used as masks, so that the target pattern with good uniformity is formed, and the device performance and performance uniformity are improved.

The semiconductor structure may be formed by using the forming method described in the foregoing embodiment, or may be formed by using other forming methods. For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, and no further description is given here.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein the substrate comprises a first graph area, a second graph area and an auxiliary area, and the size of a target graph formed in the first graph area is smaller than that of a target graph formed in the second graph area;

forming a first mask pattern on the substrate of the first pattern region and the auxiliary region only;

forming a second mask pattern on the substrate of the second pattern region and the auxiliary region only after forming the first mask pattern, wherein the second mask pattern covers the first mask pattern in the auxiliary region;

And etching the substrate by taking the first mask pattern and the second mask pattern as masks to form a target pattern.

2. The method of forming a semiconductor structure of claim 1, wherein said forming a first mask pattern in said first pattern region and said auxiliary region comprises:

forming a plurality of discrete core layers on the substrate of the first pattern region and the auxiliary region;

forming a side wall material layer which conformally covers the substrate and the core layer;

etching the side wall material layer, and forming a first mask pattern with the same extending direction as the core layer on the side wall of the core layer;

and removing the core layer.

3. The method of forming a semiconductor structure of claim 2, wherein the step of etching the sidewall material layer to form a first mask pattern on the sidewall of the core layer in the same direction as the extending direction of the core layer comprises:

and etching to remove the side wall material layers positioned at the top of the substrate and the top of the core layer, and reserving a side wall group surrounding the core layer, wherein the side wall group comprises side walls positioned on the side wall of the core layer and having the same extending direction as the core layer and side wall connecting parts connected with the side walls, and the side walls are used as the first mask pattern.

4. The method of forming a semiconductor structure of claim 3, further comprising, after forming said set of side walls:

and etching to remove the side wall connecting part.

5. The method of forming a semiconductor structure according to claim 3 or 4, wherein the step of forming a second mask pattern in the second pattern region and the auxiliary region comprises:

forming a mask material layer on the substrate exposed by the first mask pattern, wherein the mask material layer covers the first mask pattern;

and etching the mask material layer to form the second mask patterns, wherein any second mask pattern in the auxiliary area at least covers one first mask pattern.

6. The method of forming a semiconductor structure as claimed in claim 5, wherein in the step of forming the second mask patterns, any one of the second mask patterns covers two adjacent first mask patterns.

7. The method of claim 2, wherein the sidewall material layer is formed by an atomic layer deposition process or a chemical vapor deposition process.

8. The method of claim 5, wherein in the step of forming a masking material layer on the substrate, a material etch selectivity of the masking material layer to the first masking pattern is greater than 10.

9. The method of claim 1, wherein the material of the first mask pattern is one or more of amorphous germanium, silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon carbonitride or silicon carbonitride;

the material of the second mask pattern is one or more of amorphous germanium, silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon carbonitride or silicon carbonitride oxide.

10. The method of forming a semiconductor structure of claim 1, wherein the auxiliary region is adjacent to the first pattern region and the second pattern region.

11. The method of forming a semiconductor structure of claim 1, wherein in the step of providing a base, the base comprises a substrate, a layer of gate material on the substrate, and a layer of hard mask material on the layer of gate material;

the step of etching the substrate by taking the first mask pattern and the second mask pattern as masks to form a target pattern comprises the following steps: and etching the hard mask material layer and the grid material layer by taking the first mask pattern and the second mask pattern as masks, forming a grid structure in the first pattern area and the second pattern area, and forming a pseudo grid structure in the auxiliary area.

12. The method of forming a semiconductor structure of claim 11, further comprising:

and removing the pseudo gate structure.

13. A semiconductor structure, comprising:

the substrate comprises a first graph area, a second graph area and an auxiliary area, wherein the size of a target graph formed in the first graph area is smaller than that of a target graph formed in the second graph area;

a first mask pattern on the substrate only in the first pattern region and the auxiliary region;

and the second mask pattern is only positioned on the substrate of the second pattern area and the auxiliary area, wherein the second mask pattern covers the first mask pattern in the auxiliary area.

14. The semiconductor structure of claim 13, wherein any second mask pattern within said auxiliary region overlies at least one first mask pattern.

15. The semiconductor structure of claim 14, wherein any one of said second mask patterns overlies two adjacent first mask patterns.

16. The semiconductor structure of claim 13, wherein a material etch selectivity of the second mask pattern and the first mask pattern is greater than 10.

17. The semiconductor structure of claim 13, wherein the material of the first mask pattern is one or more of amorphous germanium, silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon carbonitride, or silicon oxycarbonitride;

18. The semiconductor structure of claim 13, wherein the base comprises a substrate, a layer of gate material on the substrate, and a layer of hard mask material on the layer of gate material;

the first mask pattern and the second mask pattern are both located on the hard mask material layer.