CN111538534B - A multi-instruction out-of-order emission method and processor based on instruction withering - Google Patents

Abstract

The invention discloses a multi-instruction out-of-order transmitting method and a processor based on instruction withering, and belongs to the field of processor design. The invention abandons a lengthy arbitration structure in the traditional transmitting framework, increases an instruction withering circuit, adopts an instruction age array to represent the time of storing instructions in a CPU, additionally adds a one-bit wake-up state bit, stores the instructions exceeding the withering threshold value into a sedimentation tank so as to be directly transmitted by the CPU, improves the circuit structures of an instruction request circuit, an instruction distribution circuit, a wake-up circuit and the like, and effectively improves the time sequence of a critical path in the multi-instruction transmitting processor; when the instruction is awakened, the instruction with a short execution period is awakened in a delayed manner, and the instruction with a long execution period is awakened in an advanced manner, so that the instruction can be executed back to back, the requirements of high performance power consumption ratio, low delay and high IPC in a modern superscalar disordered processor are met, and the problems that the number of entries in a transmission queue of the processor in the prior art is increased and the delay is increased are solved.

Description

A multi-instruction out-of-order emission method and processor based on instruction withering

technical field

The invention relates to a multi-instruction out-of-sequence emission method based on instruction withering and a processor, belonging to the field of processor design.

Background technique

CPUs have been particularly slow to improve in single-core performance in the over a decade since the Dennard scaling ended. In this context, it is absolutely necessary to re-study the core microarchitecture to achieve high single-core performance.

Among the many structures of the CPU, the instruction emission architecture is one of the important architectures to realize the high performance of the CPU. The instruction issue architecture schedules instructions for execution by selecting and issuing instructions from the instructions to issue in the instruction issue queue each cycle. In order to achieve high performance, the instruction launch architecture must achieve high IPC (Instructions per clock, the number of instructions executed per cycle) with low latency. At the same time, low latency is an important consideration in the process of designing the instruction emission architecture, because the instruction emission architecture is a timing-critical path in the processor, and the delay of the instruction emission architecture will have a significant impact on the operating frequency of the CPU.

The traditional multi-instruction out-of-order issue architecture selects the instructions that can be issued through the arbitration circuit. The advantage is that the oldest instruction can be accurately selected for transmission, which ensures the efficiency of the processor pipeline. However, as the number of entries in the launch queue increases, the arbitration The delay of the circuit will increase accordingly.

In modern processors, in order to pursue high IPC, many entries are often designed in the launch queue, which causes the delay of the arbitration circuit to be obvious, making the instruction launch circuit a critical path in the processor and a bottleneck of the main frequency of the processor. .

In view of the above requirements and challenges, it is very urgent to provide a multi-instruction out-of-order emission architecture design based on instruction withering for conditions such as low latency and high IPC.

The multi-instruction out-of-order emission architecture designed by the present invention can effectively determine the size of the instruction age and under the condition that the influence on the efficiency of the processor pipeline is as small as possible, the delay of the timing path will not increase with the number of entries in the emission queue. The increase is increased to ensure that the delay in the processor with a large number of table entries is as small as possible, which provides a guarantee for the increase of the main frequency of the processor.

Contents of the invention

In order to solve the problem that the delay of the arbitration circuit will increase correspondingly with the increase of the number of items in the launch queue in the current method of selecting instructions that can be transmitted through the arbitration circuit, the present invention provides a multi-command out-of-sequence transmission method based on command withering and processor.

A multi-instruction out-of-order emission method, adding an instruction withering circuit in the instruction out-of-order emission architecture of the processor, used to store newly allocated instructions into the emission queue, and implement the withering operation on the instructions in the emission queue; Methods include:

Set the highest bit of the instruction age corresponding to each instruction in the instruction withering circuit as the wake-up state bit of the instruction, and the remaining bits of the instruction age represent the intrinsic age of the instruction; the wake-up state bit is used to indicate whether the corresponding The wake-up command age is greater than the non-wake-up command age;

Set the withering threshold. When the instruction age of a certain instruction exceeds the withering threshold, the instruction age array triggers the withering signal, causing the instruction to wither; the instruction that has withered can be randomly selected for launch without arbitration, realizing the randomness of multiple instructions. sequential launch;

Each instruction in the emission queue determines the emission order according to the instruction age and the wake-up state.

Optionally, when waking up instructions, the method delays waking up instructions with short execution cycles, and wakes up instructions with long execution cycles in advance, so as to ensure that the instructions can be executed back-to-back.

Optionally, when waking up the instructions in the method, after the previous instruction is issued among the instructions having a sequence, the processor waits for the execution of the previous instruction to be completed before waking up the subsequent instruction.

Optionally, the instruction out-of-order emission architecture also includes an instruction allocation circuit, an adder-based instruction request circuit and a dynamic delay wake-up circuit;

The instruction allocation circuit is used to allocate multiple instructions sent by the physical register to idle entries in the emission queue;

The instruction request circuit based on the adder is used to count the total number of idle signals in the launch queue, and encode the number of idle signals with a special code, if the total number of idle signals after the code is smaller than the same coded instruction launch width , then send an instruction request signal to the physical register file;

The dynamic delay wake-up circuit is used to send a wake-up signal when the source register number of the instruction to be transmitted is equal to the destination register number of the transmitted instruction. The execution cycle of the instruction adjusts the wake-up signal sequence to ensure that the instructions can be executed back to back.

Optionally, the instruction withering circuit includes an instruction age array, an emission queue, an withering threshold adjuster, a sedimentation pool, and a global age feature extraction circuit;

The instruction age array is used to indicate the instruction age of each instruction in the emission queue and whether it is awakened;

The emission queue is used to store instructions sent from physical registers; the emission queue is designed as a non-compressed structure, that is, when the physical register number of an instruction in a certain entry is idle after being emitted, other entries will not be shifted, In addition to temporarily storing the physical register number of the current instruction, each entry also records the wake-up state of the current instruction and whether the entry is idle;

The withering threshold adjuster is used to dynamically adjust and output the withering threshold according to the number of idle entries in the settling pool and the age values of the instructions still remaining in the emission queue;

The settling tank is used to store withering instructions satisfying withering conditions;

The global age feature extraction circuit is used for statistics of global age features.

Optionally, the input of the withering threshold adjuster is the age of each instruction in the instruction age array, and the output is the withering threshold x, namely:

Among them, σ is the variance of the instruction age, μ is the expectation of the instruction age, α is the adjustment coefficient, and α satisfies

Optionally, the adder-like instruction request circuit includes an addition-like layer and a post-log2(n/2) shift logic layer, where n represents the number of entries in the transmit queue.

Optionally, the dynamic delay wake-up circuit is composed of a comparator, an instruction execution discrimination circuit, and a register; the input of the wake-up circuit is the source register number of the instruction to be transmitted and the destination register number of the transmitted instruction, and the instruction to be transmitted is compared by the comparator Whether the source register number of the source register number and the destination register number of the transmitted instruction are equal, if they are equal, a wake-up signal is sent; at the same time, the wake-up circuit identifies the execution cycle of the instruction to be transmitted through the instruction execution discrimination circuit, and outputs the number of cycles of the instruction to be transmitted. The cycle number of the sending instruction registers the wake-up signal to be sent, so as to achieve the purpose of adjusting the sequence of the wake-up signal.

The present application also provides a processor, the instruction out-of-order emission architecture of the processor includes an instruction distribution circuit, an instruction withering circuit, an instruction request circuit based on a class adder, and a dynamic delay wake-up circuit;

The instruction allocation circuit is used to allocate multiple instructions sent by the physical register to idle entries in the emission queue;

The instruction withering circuit is used to store the newly allocated instructions into the emission queue, and implement the withering operation on the instructions in the emission queue according to the instruction age of each instruction; the instruction withering can be randomly selected for emission without arbitration;

The instruction request circuit based on the adder is used to count the total number of idle signals in the launch queue, and encode the number of idle signals with a special code, if the total number of idle signals after the code is smaller than the same coded instruction launch width , then send an instruction request signal to the physical register file;

The dynamic delay wake-up circuit is used to send a wake-up signal when the source register number of the instruction to be transmitted is equal to the destination register number of the transmitted instruction. The execution cycle of the instruction adjusts the wake-up signal sequence to ensure that the instructions can be executed back to back.

Optionally, the highest bit of the instruction age of each instruction is set as the wake-up state bit of the instruction, and the remaining bits of the instruction age represent the intrinsic age of the instruction; the wake-up state bit is used to indicate whether the corresponding instruction is awakened, and the awakened ones in the emission queue The command age is greater than the non-wakeup command age.

The beneficial effects of the present invention are:

This application abandons the lengthy arbitration structure in the traditional launch architecture, adds an instruction withering circuit, uses an instruction age array to represent the storage time of instructions in the CPU, and adds a wake-up status bit to store instructions that have exceeded the withering threshold in the settlement Pool for direct CPU launch, and improve the circuit structure of instruction request circuit, instruction distribution circuit, wake-up circuit, etc., effectively improve the timing of the critical path in the processor of multi-instruction launch; when waking up instructions, delay the wake-up of instructions with short execution cycles , to wake up the instructions with a long execution cycle in advance to ensure that the instructions can be executed back to back, which meets the requirements of high performance power consumption ratio, low delay, and high IPC in modern superscalar out-of-order processors, and solves the problem that processors in the prior art cannot Problems with increasing delays due to increasing number of launch queue entries.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained based on these drawings without creative effort.

FIG. 1 is a schematic diagram of the overall composition of the multi-instruction out-of-order issue architecture based on instruction withering in the present invention.

FIG. 2 is a schematic diagram of the composition of the instruction withering circuit of the present invention.

FIG. 3 is a schematic diagram of the composition of the instruction distribution circuit of the present invention.

FIG. 4 is a schematic diagram of the composition of the instruction request circuit based on the class adder of the present invention.

FIG. 5 is a schematic diagram of the composition of the dynamic delay wake-up circuit of the present invention.

FIG. 6 is a schematic diagram of a pipeline for adjusting a wake-up sequence through a wake-up circuit.

Detailed ways

In order to make the purpose, technical solution and advantages of the present invention clearer, the following will further describe in detail the embodiments of the present invention in conjunction with the accompanying drawings.

Embodiment one:

This embodiment provides a processor. Referring to FIG. 1 , it is a schematic diagram of the overall structure of the multi-instruction out-of-order emission architecture of the processor. The multi-instruction out-of-order emission architecture includes: an instruction distribution circuit, an instruction withering circuit, and a class-based adder The instruction request circuit, the dynamic delay wake-up circuit.

Wherein, the instruction allocating circuit allocates the register-renamed instruction to each entry in the instruction issuing queue. The instruction issue queue includes multiple entries, and each entry contains an instruction to be issued. If there is an idle entry in the instruction issue queue, the instruction allocated through the allocation circuit will be accepted.

All the instructions to be issued that have just entered the entry are in the non-awakened state. If the number of the source register of an instruction is equal to the label of the target register of the issued instruction, the instruction will be awakened by the wake-up circuit. Instructions in all table entries are implemented by the instruction withering circuit, and all instructions that have completed the withering will be issued eventually, realizing the out-of-order emission of multiple instructions, and the out-of-order emission of multiple instructions can be completed in the superscalar out-of-order emission processor .

The composition diagram of the command withering circuit is shown in Fig. 2, and the command withering circuit includes a command age array, an emission queue, a withering threshold adjuster, a settling pool, and a global age feature extraction circuit.

Instructions newly allocated by the instruction allocation circuit enter the instruction withering circuit and are stored in the idle launch queue entry, and at the same time, the corresponding instruction age in the instruction age array is initialized to a random value between 0 and 1.

Whenever an instruction is issued, the age increment signal is released to the age array, and the age of the instructions that have not been issued in the emission queue is increased by 1 accordingly.

The withering threshold adjuster adjusts and outputs the withering threshold according to the free entry information of the sedimentation tank and the global age threshold. If the age of a certain command in the command age array is greater than the withering threshold, the command age array outputs a withering signal, and the command receiving the withering signal Execute the withering operation, enter the sedimentation pool from the launch queue, and set the corresponding entries in the launch queue to an idle state, waiting for the input of a newly allocated command.

Wither commands that are in a settlement pool can be issued without arbitration.

The input of the withering threshold adjuster is the settling tank idle table item information and the global age feature, the global age feature value is output by the global age feature extraction circuit, and the adjuster adjusts according to the number of free table items in the settling tank and the age values of all current instructions. And output the wither threshold.

The input of the withering threshold adjuster is the age of each instruction in the instruction age array, and the output is the withering threshold, the withering threshold x, namely:

Among them, α satisfies σ is the variance of instruction age and μ is the expectation of instruction age. Its characteristics are worth deriving as follows:

In modern processors, hundreds of millions of instructions can be processed per second, and the initial value of the age is a random value between 0 and 1. Under this large sample condition, it can be considered that the age of the processor is continuous, and according to the large According to the number theorem, it can be considered that the age of the processor obeys a normal distribution:

where σ is the variance of instruction age and μ is the expectation of instruction age.

Constructor g(x):

For (2) variant

Find the first derivative of (3)

Find the second derivative of (3)

Let formula (4) be 0 to get

Bring (6) into (5) so that

have to

In order to make the age withered by x as the threshold as large as possible and have as little impact on the pipeline efficiency as possible, there should be

Taking the lowest threshold, the constraint condition of the adjustment coefficient α is

To sum up, we can get

and α satisfies />

The instruction age array is essentially a counter array, and each counter has a total of bit, representing the instruction age of the corresponding instruction, where low /> The bit is the age counting bit, and the highest bit is the wake-up status bit.

Whenever a newly allocated instruction enters the launch queue of the instruction withering circuit, the corresponding instruction age is set to zero;

Whenever an instruction is issued, the age of the instruction corresponding to the instruction that has not been issued is increased by 1;

Whenever an instruction in the launch queue is woken up, the wake-up status bit of the instruction age corresponding to the instruction is 1. If the instruction age corresponding to a certain instruction is greater than the withering threshold, a withering signal will be output to the launch queue, where n represents the number of entries in the launch queue, s represents the instruction issue width.

The transmit queue includes n entries, and each entry stores an instruction to be transmitted and an idle bit of the entry.

The settling pool is an instruction queue whose number of entries is much smaller than that of the instruction issuing queue, in which there are withering instructions satisfying withering conditions, and the withering instructions in the settling pool can be directly issued without arbitration.

As shown in Figure 3, it is a schematic diagram of the composition of the instruction distribution circuit. The instruction allocating circuit is used for allocating multiple instructions sent from the physical registers to idle entries in the issue queue.

The instruction distribution circuit includes s entry number selection circuits, and the input of each entry number selection circuit is the idle signal sequence of n/s entries in the emission queue in the instruction withering circuit and the corresponding emission queue entry number, The entry number selection circuit selects the entry number of the transmit queue according to whether the input idle signal is valid. If there are multiple idle signals valid, the entry number of the first active idle signal is selected; if there is no effective idle signal, the output value It is the maximum value of the upper limit of data bits, indicating that there is no selected entry. The entry number output by the entry allocation circuit is compared with the upper limit of the numerical value, and if they are equal, the valid signal is set to 1, and if they are not equal, then it is set to 0. The instruction to be allocated for each input of the distribution circuit is written into the corresponding table entry according to the table entry number and the effective signal. Where s represents the instruction issue width, and n represents the number of entries in the issue queue.

The entry number selection circuit is composed of a selector array. As shown in FIG. 2, the selector in the first column inputs the entry number. Since the first idle entry needs to be selected, the selector is based on the idle signal of the smaller entry number. Select the table entry number; the second layer table entry number input is the selection table entry number output of the first layer selection layer, and the selection signal is the idle signal of the smaller table entry number, and so on, there are a total of log2(n) layer selection layers. The selection result of the log2(n) layer selection layer is output to the all-empty item selector, the selection signal of the selector is the selection signal of the log2(n) layer selection layer, and the data to be selected is the log2(n) layer selection layer The selection result and numerical upper limit value, if the selection signal is 0, output the numerical upper limit value as the final entry number output; if not 0, output the selection result of the log2(n) layer selection layer as the final entry number output , where n represents the number of entries.

Figure 4 is a schematic diagram of the composition of the command request circuit. The instruction request circuit is used for counting the total number of idle signals of table entries, and encodes the number of idle signals with a special code, and if the total number of idle signals after the encoding is smaller than the instruction emission width that has also undergone the encoding, an instruction is sent to the physical register file request signal. The instruction request circuit is composed of two parts: the addition-like layer and the post-log2(n/2) shift logic layer.

The class addition layer is composed of a class addition calculation unit; when counting the total number of table item idle signals, the table item idle signal sequence is input into the class addition layer, and the number of idle signals is calculated and specially coded, and the output is specially coded The total number of idle signals at the end; the output of the class addition layer is sent to the rear log2(n/2) layer shifting logic layer, and the final output statistics are compared with the same specially encoded instruction launch width to determine whether A command request signal needs to be sent.

Specifically, when counting the total number of idle signals of table entries, the idle signal sequence of the table entry is input into the addition-like layer, and each addition-like unit is input as two binary numbers in the idle signal sequence and performs AND operation and XOR operation respectively, Then compare the calculation results of the two:

If they are equal, and the result of the AND operation is 1, the code representing 1 is output: "01", which means that the sum of the two binary system inputs of the addition unit is 1, and it is coded as "01";

If they are equal, and the bit of the operation result is 0, then the code representing 0 is output: "10", which means that the sum of the two binary system input of the addition unit is 0, and it is coded as "10";

If they are not equal, then the output represents the coding of 2: "00", which means that the sum of the two binary system input of the addition unit is 2, and it is coded as "00";

The number of encoding bits is n.

The post-log2(n/2) layer shift logic layer is composed of a right-shift shifter; the output of the addition-like layer is input into the post-log2(n/2) layer shift logic layer, and the same specially encoded instruction emission width Comparisons are made to determine if a command request signal needs to be sent, including:

The right-shift shifter takes the output of one type of adding unit as the input of the data to be shifted, and the output of the other type of adding unit as the input of the number of bits to be shifted, and the number of bits to be shifted is shifted right by n bits by the right-shifter. Among them, n is the decimal number corresponding to the number of bits shifted.

For example, if the number to be shifted is "01" and the number of shifted bits is "00", then according to the above coding rules, "01" is shifted to the right by 2 bits;

Figure 5 is a schematic diagram of the composition of the wake-up circuit. The wake-up circuit is composed of a comparator, an instruction execution discrimination circuit and a register.

The input of the wake-up circuit is the source register number of the instruction to be transmitted and the destination register number of the transmitted instruction. The comparator is used to compare the source register number of the instruction to be transmitted and the destination register number of the transmitted instruction. At the same time, the wake-up circuit recognizes the execution cycle of the instruction to be transmitted through the instruction execution discrimination circuit, and outputs the cycle number of the instruction to be transmitted, and the register registers the wake-up signal to be sent by the cycle number of the instruction to be transmitted, so as to achieve the sequence adjustment of the wake-up signal The purpose is to delay the wake-up of instructions with a short execution cycle and wake up the instructions with a long execution cycle in advance, so as to ensure that the instructions on the pipeline can be executed back to back and improve the efficiency of the pipeline.

FIG. 6 is a schematic diagram of a pipeline after instruction wake-up adjustment. Instruction A requires 3 execution cycles, and instructions B, C, and D each require one execution cycle. After adjusting the wake-up sequence of the wake-up circuit, instruction D delays the wake-up of instruction A by two cycles, and two instructions can be inserted between instructions A and D. Instructions B and C are executed back-to-back, so as to ensure that all four instructions are executed back-to-back, without delay bubbles, and improve the execution efficiency of the pipeline.

Embodiment two

This embodiment provides a multi-instruction out-of-order emission method based on instruction withering, which is used in the processor described in Embodiment 1. The emission architecture of the processor is a non-data-capture emission architecture, that is, the CPU executes the instruction after the emission stage. The physical register file will be actually read, and each entry in the launch queue stores the number of the physical register; the method includes:

S1, when the physical register file receives an instruction request signal from the instruction request circuit, output a suitable instruction to the instruction allocation circuit.

S2, the instruction assignment circuit assigns the instruction output by the physical register file to each entry in the instruction emission queue:

The command allocation circuit includes s table entry number selection circuits, and the input of each table entry number selection circuit is the idle signal sequence of n/s table entries in the transmission queue in the instruction withering circuit and the corresponding transmission queue entry number, and the table entry number The selection circuit selects the entry number of the transmit queue according to whether the input idle signal is valid. If multiple idle signals are valid, the entry number of the first idle signal is selected; if there is no effective idle signal, the output value is a data bit The maximum value of the upper limit, indicating that there is no selected entry.

The entry number output by the entry allocation circuit is compared with the upper limit of the numerical value, and if they are equal, the valid signal is set to 1, and if they are not equal, then it is set to 0. The instruction to be allocated for each input of the distribution circuit is written into the corresponding table entry according to the table entry number and the effective signal.

Where s represents the instruction issue width, and n represents the number of entries in the issue queue.

Instructions newly allocated by the instruction allocation circuit enter the instruction withering circuit and are stored in the idle launch queue entry, and at the same time, the corresponding instruction age in the instruction age array is initialized to a random value between 0 and 1.

S3, every time the launch queue in the command withering circuit accepts a new command, the command age in the command age array corresponding to the entry of the command is set to zero; every time the command withering circuit transmits a command, the command still in the transmit queue corresponds to Add one to the instruction age; the highest bit of the instruction age corresponding to the instruction is the wake-up status bit of the instruction, and the remaining bits represent the intrinsic age of the instruction. After the commands in the launch queue are woken up, the highest position of the corresponding age information is one, which ensures that the age of the wake-up command is greater than the age of the non-wake-up command.

When the instruction age exceeds the withering threshold, the instruction age array will trigger the withering signal, causing the instruction to wither, and the withered instruction will enter the settlement pool from the emission queue, and the entry in the emission queue will be set to idle.

The settling pool is an instruction queue whose number of entries is much smaller than that of the launch queue, and there are instructions after withering, and the withering commands in the settling pool can be randomly selected for launch.

The launch queue in the withering circuit is designed as a non-compressed structure, that is, when the physical register number of an instruction in a certain table entry is idle after being sent, other table entries will not be shifted, and each table entry saves the physical register number of the current instruction. The register number also records the wake-up state of the current instruction and whether the entry is idle;

S4, the idle signal of the entry in the launch queue will be sent to the command request circuit at the same time, and the command request circuit will count the number of idle entries in the launch queue. If the number of idle entries in the launch queue is greater than the command launch width, the request circuit will send The physical register file sends an instruction request signal, the physical register file receives the request signal, and sends an instruction to the instruction distribution circuit;

S5, during the instruction emission process, the wake-up circuit is responsible for comparing the target register number of the current emission with the source register number of each instruction in the emission queue. Delayed transmission, early wake-up of instructions with long execution cycle, and delayed transmission of instructions with short execution cycle. The wake-up signal sets the wake-up state bit in the instruction age corresponding to the instruction to 1, ensuring that the age of the awakened instruction is greater than the age of the unawakened instruction.

Part of the steps in the embodiments of the present invention can be realized by software, and the corresponding software program can be stored in a readable storage medium, such as an optical disk or a hard disk.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection of the present invention. within range.

Claims (9)

1. A multi-instruction out-of-order emission method is characterized in that an instruction withering circuit is added in an instruction out-of-order emission framework of a processor and used for storing newly allocated instructions into an emission queue and implementing withering operation on the instructions in the emission queue; the method comprises the following steps:

setting the highest bit of the instruction age corresponding to each instruction in the instruction withering circuit as the awakening state bit of the instruction, wherein the rest bits of the instruction age represent the intrinsic age of the instruction; the wake-up status bit is used for indicating whether the corresponding instruction is waken up, and the waken-up instruction age in the transmitting queue is larger than the non-waken-up instruction age;

setting a withering threshold, and triggering a withering signal by an instruction age array when the instruction age of a certain instruction exceeds the withering threshold so as to enable the instruction to wither; the instruction with withering can be randomly selected to transmit without arbitration, so that out-of-order transmission of multiple instructions is realized;

each instruction in the transmitting queue determines a transmitting sequence according to the instruction age and the awakening state;

the input of the withering threshold value adjuster is the age of each instruction in the instruction age array, and the output is the withering threshold value x, namely:

wherein σ is the variance of the instruction age, μ is the expectation of the instruction age, α is the adjustment coefficient, and α satisfies

2. The method of claim 1, wherein the method wakes up instructions with a short execution period later and wakes up instructions with a long execution period earlier when waking up instructions to ensure that instructions can be executed back-to-back.

3. The method of claim 2, wherein the method wakes up a subsequent instruction after the processor waits for the preceding instruction to complete execution when the preceding instruction is issued among the instructions having the order.

4. The method of claim 3, wherein the instruction out-of-order issue architecture further comprises an instruction dispatch circuit, a class adder based instruction request circuit and a dynamic delay wakeup circuit;

the instruction distribution circuit is used for distributing a plurality of instructions sent by the physical register to idle table items in the transmission queue;

the instruction request circuit based on the class adder is used for counting the total number of idle signals in an entry in the transmission queue, encoding the number of the idle signals by using a special encoding, and if the total number of the encoded idle signals is smaller than the transmission width of the instruction which is also encoded, transmitting an instruction request signal to a physical register file;

the dynamic delay wake-up circuit is used for sending out a wake-up signal when the source register number of the instruction to be transmitted is equal to the destination register number of the transmitted instruction, and meanwhile, the wake-up circuit identifies the execution period of the instruction to be transmitted through the instruction execution distinguishing circuit, and adjusts the sequence of the wake-up signal according to the execution period of the instruction to be transmitted so as to ensure that the instruction can be executed back to back.

5. The method of claim 4, wherein the instruction littering circuit comprises an instruction age array, a transmit queue, a littering threshold regulator, a settling pond, a global age feature extraction circuit;

the instruction age array is used for indicating the instruction age of each instruction in the emission queue and whether the instruction is awakened;

the emission queue is used for storing instructions sent from the physical register; the transmitting queue is designed into a non-compressed structure, namely when the physical register number of an instruction in a certain table item is in an idle state after being transmitted, other table items cannot be shifted, and each table item not only stores the physical register number of the current instruction temporarily, but also records the awakening state of the current instruction and whether the table item is in the idle state;

the withering threshold value adjuster is used for dynamically adjusting and outputting a withering threshold value according to the number of idle items of the sedimentation tank and the age value of an instruction in a remained transmitting queue;

the sedimentation tank is used for storing a withering instruction meeting a withering condition;

the global age characteristic extraction circuit is used for counting global age characteristics.

6. The method of claim 4, wherein the class adder based instruction request circuit comprises a class addition layer and a post log2 (n/2) layer shift logic layer, n representing the number of entries in the transmit queue.

7. The method of claim 4, wherein the dynamic delay wake-up circuit is comprised of a comparator, an instruction execution discrimination circuit, a register; the input of the wake-up circuit is the source register number of the instruction to be transmitted and the destination register number of the transmitted instruction, the source register number of the instruction to be transmitted and the destination register number of the transmitted instruction are compared through a comparator, whether the source register number of the instruction to be transmitted and the destination register number of the transmitted instruction are equal or not is judged, and if the source register number of the instruction to be transmitted and the destination register number of the transmitted instruction are equal, a wake-up signal is sent out; meanwhile, the wake-up circuit recognizes the execution cycle of the instruction to be transmitted through the instruction execution distinguishing circuit, outputs the cycle number of the instruction to be transmitted, and registers the wake-up signal to be transmitted through the cycle number of the instruction to be transmitted, so that the purpose of sequentially adjusting the wake-up signal is achieved.

8. A processor, wherein the instruction out-of-order emission architecture of the processor comprises an instruction distribution circuit, an instruction wither circuit, an instruction request circuit based on class adders and a dynamic delay wake-up circuit;

the instruction distribution circuit is used for distributing a plurality of instructions sent by the physical register to idle table items in the transmission queue;

the instruction withering circuit is used for storing newly allocated instructions into the transmission queue and implementing withering operation on the instructions in the transmission queue according to the instruction ages of the instructions; the instruction with withering can be randomly selected to transmit without arbitration;

the instruction request circuit based on the class adder is used for counting the total number of idle signals in an entry in the transmission queue, encoding the number of the idle signals by using a special encoding, and if the total number of the encoded idle signals is smaller than the transmission width of the instruction which is also encoded, transmitting an instruction request signal to a physical register file;

the dynamic delay wake-up circuit is used for sending out a wake-up signal when the source register number of the instruction to be transmitted is equal to the destination register number of the transmitted instruction, and meanwhile, the wake-up circuit identifies the execution period of the instruction to be transmitted through the instruction execution distinguishing circuit, and adjusts the sequence of the wake-up signal according to the execution period of the instruction to be transmitted so as to ensure that the instruction can be executed back to back.

9. The processor of claim 8, wherein a highest bit of an instruction age of each instruction is set to an awake state bit of the instruction, and remaining bits of the instruction age represent an instruction intrinsic age; the wake state bit is used to indicate whether the corresponding instruction is awakened, and the instruction age of the awakened instruction in the transmit queue is greater than the instruction age of the non-awakened instruction.