CN111564174A - Digital redundancy circuit supporting block erasure and operation method thereof - Google Patents
Digital redundancy circuit supporting block erasure and operation method thereof Download PDFInfo
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/838—Masking faults in memories by using spares or by reconfiguring using programmable devices with substitution of defective spares
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Abstract
The invention provides a digital redundancy circuit supporting block erasure and an operation method thereof, a memory, a plurality of blocks in the memory; each block comprises a plurality of rows, and the plurality of rows comprise a part of bad rows; each row corresponds to a current address of the memory during working; each bad row also corresponds to a bad row address and a redundant row for replacing the bad row; each redundant row corresponds to a redundant address; the bad row address corresponding to each bad row and the current address thereof are connected with the input end of a multiplexer; the output of each multiplexer is connected to a null address. The digital redundancy circuit supporting block erasure and the operation method thereof can replace two selected bad row addresses simultaneously when two bad row addresses in the same block are selected during block operation, thereby realizing the block operation.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and more particularly, to a digital redundancy circuit supporting block erase and a method of operating the same.
Background
With the increasing demand for product profitability, it is indispensable to design a redundant replacement module for a memory capable of greatly reducing factory failure, and in order to improve the erase efficiency, a block erase is applied to the memory, as shown in the drawing, fig. 1 shows a schematic diagram of a conventional redundant module, where the total row number is 112pages (rows) and is divided into 7 sectors (blocks), a general redundant replacement module only supports page (row) operation, when block operation is performed, two damaged page addresses a1 and a2 of the memory are selected at the same time, but the current address is only one of the addresses, the redundant address can only replace one of the damaged page addresses, two damaged row addresses in the same block cannot be replaced at the same time, and block operation is not implemented.
Therefore, a new digital redundancy circuit is needed to solve the above problems.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention provides a digital redundancy circuit adding operation method supporting block erase, which is used to solve the problem that when a block operation is performed in the prior art, two damaged row addresses in the same block cannot be replaced at the same time, thereby making the block operation difficult to implement.
To achieve the above and other related objects, the present invention provides a digital redundancy circuit supporting block erase, comprising: a memory, a plurality of blocks in the memory; each block comprises a plurality of rows, and the plurality of rows comprise a part of bad rows; each line corresponds to a current address of the memory during working; each bad row also corresponds to a bad row address and a redundant row for replacing the bad row; each redundant row corresponds to a redundant address;
the bad row address corresponding to each bad row and the current address thereof are connected with the input end of a multiplexer; the output end of each multiplexer is connected with a null address.
Preferably, the memory comprises two blocks.
Preferably, each block contains two bad rows.
The invention also provides an operation method of the digital redundancy circuit supporting block erasure, which is a row operation and at least comprises the following steps:
step one, selecting a current address corresponding to one of the rows from the memory;
step two, comparing the current address with a bad row address corresponding to the bad row of the row through the multiplexer;
if the bad row address corresponding to the bad row is the same as the current address, the redundant address of the redundant row corresponding to the bad row replaces the bad row address; and if the bad row address corresponding to the bad row is different from the current address, the bad row address corresponding to the bad row is valid.
Preferably, the empty address connected to the output of the multiplexer in step two is equivalent to the redundant address in step three.
The invention also provides an operation method of the digital redundancy circuit supporting block erasure, which is a block operation and at least comprises the following steps:
step a, selecting one current address in one block, and selecting a bad row address corresponding to each of at least two bad rows in the same block;
step b, comparing the selected bad row address with the current address through the multiplexer;
c, selecting a bad row address corresponding to the selected bad row and a null address of the current address of the bad row address connected through the output end of the multiplexer, and selecting a redundant address of the bad row address corresponding to the selected bad row;
and d, replacing the corresponding bad row address by the selected redundant address corresponding to the bad row.
Preferably, the block selected in step a contains two current addresses.
Preferably, in step a, the bad row address corresponding to each of the two bad rows in the same block is selected.
As described above, the digital redundancy circuit supporting block erase and the method for operating the same of the present invention have the following advantageous effects: the digital redundancy circuit supporting block erasure and the operation method thereof can replace two selected bad row addresses simultaneously when two bad row addresses in the same block are selected during block operation, thereby realizing the block operation.
Drawings
FIG. 1 is a block diagram of a block comprising a plurality of rows according to the prior art;
FIGS. 2a and 2b are schematic block diagrams illustrating the operation of the memory according to the present invention;
fig. 3a and 3b are schematic block diagrams illustrating the block operation of the memory according to the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 2a to fig. 3 b. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
The present invention provides a digital redundancy circuit supporting block erase, as shown in fig. 2a and fig. 2b, and fig. 3a and fig. 3b, wherein fig. 2a and fig. 2b are schematic block diagrams of a memory according to the present invention; fig. 3a and 3b are schematic block diagrams illustrating the block operation of the memory according to the present invention, wherein the digital redundancy circuit at least comprises: a memory, a plurality of blocks in the memory; each block comprises a plurality of rows, and the plurality of rows comprise a part of bad rows; each line corresponds to a current address of the memory during working; each bad row also corresponds to a bad row address and a redundant row for replacing the bad row; each redundant row corresponds to a redundant address; the bad row address corresponding to each bad row and the current address thereof are connected with the input end of a multiplexer; the output end of each multiplexer is connected with a null address.
Further to the present invention, the memory includes two blocks. The memory in this embodiment includes two blocks (sectors), namely block 1 and block 2 in fig. 2 a; the block 1 and the block 2 respectively comprise a plurality of rows, and a part of the plurality of rows in the block 1 are bad rows, and a part of the plurality of rows in the block 2 are bad rows. Only two bad rows per block are shown in fig. 2a, where block 1 contains bad row 1 and bad row 2; block 2 contains bad row 3 and bad row 4; each row in the block corresponds to a current address of the memory during operation, as shown in fig. 2B, that is, each row in the block 1 corresponds to a current address, that is, the bad row 1 and the bad row 2 respectively correspond to current addresses B1 and B2 in sequence; bad row 3 and bad row 4 correspond to current addresses B3 and B4, respectively. The bad row 1 and the bad row 2 in the block 1 respectively correspond to a bad row address A1 and A2 in sequence; the bad row 3 and the bad row 4 in the block 2 respectively correspond to a bad row address A3 and a4 in sequence; the bad row 1 and the bad row 2 in the block 1 further respectively correspond to a redundant row for replacing the bad row 1 and the bad row 2 in sequence, as shown in fig. 3a, that is, the bad row 1 corresponds to the redundant row 1, and the bad row 2 corresponds to the redundant row 2; the bad row 3 in the block 2 corresponds to the redundant row 3, and the bad row 4 corresponds to the redundant row 4. The redundant row 1 to the redundant row 4 respectively correspond to a redundant address W1 to a redundant address W4 in sequence; the bad row address corresponding to each bad row and the current address thereof are connected with the input end of a multiplexer; as shown in fig. 3B, the bad row address a1 corresponding to the bad row 1 and the current address B1 of the bad row 1 are commonly connected to an input terminal of a multiplexer MUX, and an output terminal of the MUX is connected to a null address K1; the bad row address A2 corresponding to the bad row 2 and the current address B2 of the bad row 2 are connected with the input end of a Multiplexer (MUX), and the output end of the MUX is connected with an empty address K2; the bad row address A3 corresponding to the bad row 3 and the current address B3 of the bad row 3 are connected with the input end of a Multiplexer (MUX), and the output end of the MUX is connected with a null address K3; the bad row address a4 corresponding to the bad row 4 and the current address B4 of the bad row 4 are commonly connected to an input terminal of a multiplexer MUX, and an output terminal of the MUX is connected to a null address K4.
The invention also provides an operation method of the digital redundancy circuit supporting block erasure, which is a row operation and at least comprises the following steps:
step one, selecting a current address corresponding to one of the rows from the memory; for example, in the present embodiment, the current address B1 is selected;
step two, comparing the current address with a bad row address corresponding to the bad row of the row through the multiplexer; in this embodiment, the current address B1 and the bad row address a1 corresponding to the bad row 1 are compared through the multiplexer MUX, or the current address B2 and the bad row address a2 corresponding to the bad row 2 are compared; or comparing the current address B3 with the bad row address A3 corresponding to the bad row 3; or comparing the current address B4 with the bad row address A4 corresponding to the bad row 4;
if the bad row address corresponding to the bad row is the same as the current address, the redundant address of the redundant row corresponding to the bad row replaces the bad row address; that is, if the bad row address a1 corresponding to the bad row 1 is the same as the current address B1, the bad row address a1 is replaced by the redundant address W1 of the redundant row 1 corresponding to the bad row 1, and the bad row address a2 corresponding to the bad row 2 is the same as the current address B2, the bad row address a2 is replaced by the redundant address W2 of the redundant row 2 corresponding to the bad row 2, and so on; further, when the row operation is performed, the empty address connected to the output terminal of the multiplexer in the second step is equivalent to the redundant address in the third step. And in the third step, if the bad row address corresponding to the bad row is different from the current address, the bad row address corresponding to the bad row is valid.
The operation method of the digital redundancy circuit supporting the block erasure realizes the operation of rows.
The invention also provides an operation method of the digital redundancy circuit supporting block erasure, which is a block operation and at least comprises the following steps:
step a, selecting one current address in one block, and selecting a bad row address corresponding to each of at least two bad rows in the same block; further, the block selected in step a includes two current addresses. Still further, the bad row addresses corresponding to the two bad rows in the same block in step a are selected. In this step of this embodiment, one current address B1 in the block 1 is selected, and the bad row address a1 and the bad row address a2 corresponding to the two bad rows 1 and 2 in the block 1 are selected.
Step b, comparing the selected bad row address with the current address through the multiplexer; the selected line feed address A1 and the current address B1 in this embodiment are compared by the multiplexer MUX;
c, selecting a bad row address corresponding to the selected bad row and a null address of the current address of the bad row, which are connected through the output end of the multiplexer, and simultaneously selecting a redundant address of the bad row address corresponding to the selected bad row; that is, the bad row address a1 corresponding to the bad row 1 and the empty address K1 of the current address B1 connected through the MUX output of the multiplexer are also selected, and the empty address K2 of the bad row address a2 connected through the MUX output is also selected;
and d, replacing the corresponding bad row address by the corresponding redundant address of the selected bad row, namely replacing the corresponding bad row addresses A1 and A2 by the corresponding redundant addresses W1 and W2 of the selected bad row 1 and the bad row 2 respectively. That is, during block operation, the blocks (sectors) with redundant addresses W1-W4 directly selected take over the operation, the bad row addresses a 1-a 4, the current addresses B1-B4 remain unchanged, but the compared redundant addresses W1-W4 are correspondingly connected with the empty addresses K1-K4 respectively; that is, in the block operation, no matter which one of B1-B4 is the current address, two addresses, namely one of the empty addresses K1-K4 and one of the redundant addresses W1-W4, are selected at the same time, but the empty addresses K1-K4 are invalid; this achieves the purpose that redundant addresses can also play a role in block operations.
In summary, the digital redundancy circuit supporting block erase and the operating method thereof of the present invention can replace two selected bad row addresses at the same time when two bad row addresses in the same block are selected during block operation, thereby implementing block operation. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (8)
1. A digital redundancy circuit supporting block erasure, comprising at least:
a memory, a plurality of blocks in the memory; each block comprises a plurality of rows, and the plurality of rows comprise a part of bad rows; each line corresponds to a current address of the memory during working; each bad row also corresponds to a bad row address and a redundant row for replacing the bad row; each redundant row corresponds to a redundant address;
the bad row address corresponding to each bad row and the current address thereof are connected with the input end of a multiplexer; the output end of each multiplexer is connected with a null address.
2. The digital redundancy circuit supporting block erasure of claim 1, wherein: the memory includes two blocks.
3. The digital redundancy circuit supporting block erasure of claim 1, wherein: two bad rows are included in each block.
4. A method of operating a digital redundancy circuit supporting block erasure according to any of claims 1 to 3, wherein the method of operation is a row operation, the method comprising at least the steps of:
step one, selecting a current address corresponding to one of the rows from the memory;
step two, comparing the current address with a bad row address corresponding to the bad row of the row through the multiplexer;
if the bad row address corresponding to the bad row is the same as the current address, the redundant address of the redundant row corresponding to the bad row replaces the bad row address; and if the bad row address corresponding to the bad row is different from the current address, the bad row address corresponding to the bad row is valid.
5. The method of claim 4 wherein the output of the multiplexer is connected to an empty address in step two that is equivalent to the redundant address in step three.
6. A method of operating a digital redundancy circuit supporting block erase according to any of claims 1 to 3, wherein the method of operation is a block operation, the method comprising at least the steps of:
step a, selecting one current address in one block, and selecting a bad row address corresponding to each of at least two bad rows in the same block;
step b, comparing the selected bad row address with the current address through the multiplexer;
c, selecting a bad row address corresponding to the selected bad row and a null address of the current address of the bad row, which are connected through the output end of the multiplexer, and simultaneously selecting a redundant address of the bad row address corresponding to the selected bad row;
and d, replacing the corresponding bad row address by the selected redundant address corresponding to the bad row.
7. The digital redundancy circuit supporting block erasure of claim 5, wherein: the block selected in step a contains two current addresses.
8. The digital redundancy circuit supporting block erasure of claim 6, wherein: and a bad row address corresponding to each of the two bad rows in the same block is selected.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1428788A (en) * | 2001-12-26 | 2003-07-09 | 三菱电机株式会社 | Semiconductor memory |
| CN103812502A (en) * | 2012-11-05 | 2014-05-21 | 阿尔特拉公司 | Programmable integrated circuits with redundant circuitry |
| CN109961819A (en) * | 2017-12-22 | 2019-07-02 | 三星电子株式会社 | Nonvolatile memory device, method of operating the same, and storage device including the same |
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- 2020-04-23 CN CN202010326525.XA patent/CN111564174A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1428788A (en) * | 2001-12-26 | 2003-07-09 | 三菱电机株式会社 | Semiconductor memory |
| CN103812502A (en) * | 2012-11-05 | 2014-05-21 | 阿尔特拉公司 | Programmable integrated circuits with redundant circuitry |
| CN109961819A (en) * | 2017-12-22 | 2019-07-02 | 三星电子株式会社 | Nonvolatile memory device, method of operating the same, and storage device including the same |
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Application publication date: 20200821 |