CN111585516B - Operational amplifier with output clamping function - Google Patents

Abstract

An operational amplifier with an output clamping function, which can be applied to a Buck converter. When the Buck converter is working in a normal state, the output of the operational amplifier module is less than the preset upper limit clamp voltage and greater than the preset lower limit clamp voltage. bit voltage, both the upper limit clamp module and the lower limit clamp module work in the comparator state, which will not affect the normal operation of the op amp. When the output of the operational amplifier module is greater than the upper limit clamp voltage, the upper limit clamp circuit will clamp the output of the op amp, leaving the comparator state, and the upper limit clamp circuit enters the op amp state. When the output of the operational amplifier module is less than the lower limit clamp voltage, the lower limit clamp circuit will clamp the output of the op amp, leaving the comparator state, and the lower limit clamp circuit enters the op amp state. The present invention adds output upper limit clamping and lower limit clamping functions to the operational amplifier, which can accelerate the response speed of the Buck converter and save power consumption.

Description

An Operational Amplifier with Output Clamp Function

technical field

The invention belongs to the technical field of electronics, and relates to an operational amplifier with an output clamping function, which can be applied to a Buck type DC-DC converter.

Background technique

In a Buck DC-DC converter, a large capacitor is usually required for compensation to ensure system stability. When the Buck converter jumps from heavy load to no-load, or the input voltage is suddenly lower than the preset output voltage, the loop will Entering a 0 duty cycle or 100% duty cycle state will cause the output of the op amp to slowly drop to 0 or rise to the supply voltage. If the load increases at this time, or the input voltage returns to normal, the current of the operational amplifier will charge and discharge the compensation capacitor, and it will take a long time to return to the normal level, and the output voltage of the Buck converter will be in an abnormal state for a long time. In order to speed up the response speed of the Buck converter, the operational amplifier current can be increased. Although increasing the operational amplifier current can reduce the recovery time, it will also increase the power consumption.

Contents of the invention

Aiming at the deficiency that the recovery time is too large in the response process of the Buck converter, the present invention proposes an operational amplifier with an output clamp function, adding output upper limit clamp and lower limit clamp functions to the operational amplifier, which can speed up the Buck conversion The response speed of the converter is improved, power consumption is saved, and the problem of excessive recovery time in the response process of the Buck converter is solved.

Technical scheme of the present invention is:

An operational amplifier with an output clamping function, comprising an operational amplifier module, a first resistor, a first capacitor, a bias module, an upper limit clamp module and a lower limit clamp module,

The bias module is used to provide bias for the operational amplification module, the upper limit clamp module and the lower limit clamp module, including a first PMOS transistor, the gate-drain of the first PMOS transistor is short-circuited and connected to a bias current, and its source Pole connected to the supply voltage;

The positive input terminal of the operational amplifier module is used as the positive input terminal of the operational amplifier, its negative input terminal is used as the negative input terminal of the operational amplifier, and its output terminal passes through the first resistor and the first capacitor in turn. grounding; the connection point of the first resistor and the first capacitor is used as the output terminal of the operational amplifier;

The upper limit clamping module includes a fifth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a ninth NMOS transistor, a third resistor and a third capacitor,

The gate of the fifth PMOS transistor is connected to the gate of the first PMOS transistor, its drain is connected to the sources of the tenth PMOS transistor and the eleventh PMOS transistor, and its source is connected to the power supply voltage;

The gate of the tenth PMOS transistor is connected to the upper limit clamping voltage, and its drain is connected to the drain of the fifth NMOS transistor and the gate of the ninth NMOS transistor;

The gate of the eleventh PMOS transistor is connected to the output terminal of the operational amplification module and the drain of the ninth NMOS transistor, and its drain is connected to the gate and drain of the sixth NMOS transistor and the gate of the fifth NMOS transistor;

The sources of the fifth NMOS transistor, the sixth NMOS transistor and the ninth NMOS transistor are grounded;

One end of the third resistor is connected to the output end of the operational amplification module, and the other end is connected to the gate of the ninth NMOS transistor after passing through the third capacitor;

The lower limit clamping module includes a third PMOS transistor, a fourth PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor , the second resistor and the second capacitor,

The gate of the fourth PMOS transistor is connected to the gate of the third PMOS transistor and the gate of the first PMOS transistor, its drain is connected to the sources of the twelfth PMOS transistor and the thirteenth PMOS transistor, and its source is connected to the third PMOS transistor. The source of the tube is connected to the supply voltage;

The gate of the thirteenth PMOS transistor is connected to the lower limit clamping voltage, and its drain is connected to the drain of the eighth NMOS transistor and the gate of the fifteenth PMOS transistor;

The gate of the twelfth PMOS transistor is connected to the output terminal of the operational amplification module and the drain of the fourteenth PMOS transistor, and its drain is connected to the gate and drain of the seventh NMOS transistor and the gate of the eighth NMOS transistor;

The sources of the seventh NMOS transistor and the eighth NMOS transistor and the drain of the fifteenth PMOS transistor are grounded;

The gate of the fourteenth PMOS transistor is connected to the drain of the third PMOS transistor and the source of the fifteenth PMOS transistor, and its source is connected to a power supply voltage or a bias signal, and the bias signal is composed of a current with the first PMOS transistor The sixteenth PMOS tube of the mirror is provided, the gate of the sixteenth PMOS tube is connected to the gate of the first PMOS tube, its source is connected to the power supply voltage, and its drain generates the bias signal;

One end of the second resistor is connected to the gate of the fifteenth PMOS transistor, and the other end is connected to the output end of the operational amplification module after passing through the second capacitor.

Specifically, the operational amplification module includes a second PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a sixth PMOS transistor. Four NMOS tubes,

The gate of the second PMOS transistor is connected to the gate of the first PMOS transistor, its source is connected to the power supply voltage, and its drain is connected to the sources of the sixth PMOS transistor and the seventh PMOS transistor;

The gate of the seventh PMOS transistor is used as the positive input terminal of the operational amplifier module, and its drain is connected to the source of the ninth PMOS transistor;

The gate of the sixth PMOS transistor is used as the negative input terminal of the operational amplifier module, and its drain is connected to the source of the eighth PMOS transistor;

The gate of the eighth PMOS transistor is connected to the gate and bias voltage of the ninth PMOS transistor, and its drain is connected to the drain of the first NMOS transistor and used as the output terminal of the operational amplification module;

The gate-drain of the third NMOS transistor is short-circuited and connected to the drain of the ninth PMOS transistor and the gate of the first NMOS transistor, and its source is connected to the gate and drain of the fourth NMOS transistor and the gate of the second NMOS transistor;

The drain of the second NMOS transistor is connected to the source of the first NMOS transistor, and the source thereof is connected to the source of the fourth NMOS transistor and grounded.

Specifically, the sixteenth PMOS transistor is the second PMOS transistor in the operational amplifier module.

Specifically, the eighth PMOS transistor and the ninth PMOS transistor are low-threshold PMOS transistors.

The beneficial effect of the present invention is: the present invention adds output upper limit clamp and lower limit clamp function in operational amplifier, can be applicable to Buck converter; When Buck converter works normally, upper limit clamp circuit and lower limit clamp circuit work in The state of the comparator does not affect the normal operation of the operational amplifier; when the output VO1 of the operational amplifier module is greater than the upper limit clamping voltage VH, the limit clamp circuit will clamp the output of the operational amplifier. When the output VO1 of the operational amplifier module When the lower limit clamp voltage VL is lower than the lower limit clamp voltage VL, the lower limit clamp circuit will clamp the output VO1 of the operational amplifier. Therefore, when the operational amplifier proposed by the present invention is applied to a Buck converter, it can speed up the response speed of the Buck converter and save power consumption.

Description of drawings

FIG. 1 is a specific circuit diagram of an operational amplifier with an output clamping function in an embodiment of the present invention.

Detailed ways

The present invention will be further elaborated below in conjunction with the accompanying drawings and specific embodiments.

The present invention proposes an operational amplifier with an output clamping function, as shown in Figure 1, which mainly includes two parts: an operational amplifier module and a clamp circuit, and the bias module provides bias for the operational amplifier circuit and the clamp circuit. The setting module includes the first PMOS transistor MP1, the gate-drain of the first PMOS transistor MP1 is short-circuited and connected to the bias current IBIAS, and its source is connected to the power supply voltage VDD; all branches of the present invention are biased by the mirror image of the first PMOS transistor MP1 set current supply.

The operational amplifier module is used to implement the operational amplifier function. In this embodiment, a single-stage telescopic structure is used as an example for illustration, but operational amplifiers with other structures are also applicable to the present invention. The operational amplifier with a single-stage telescopic structure can increase the gain. As shown in Figure 1, the operational amplifier module in this embodiment includes the second PMOS transistor MP2, the sixth PMOS transistor MP6, the seventh PMOS transistor MP7, and the eighth PMOS transistor MP8. , the ninth PMOS transistor MP9, the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3 and the fourth NMOS transistor MN4, the gate of the second PMOS transistor MP2 is connected to the gate of the first PMOS transistor, and its source The pole is connected to the power supply voltage VDD, and its drain is connected to the sources of the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7; the gate of the seventh PMOS transistor MP7 is used as the positive input terminal of the operational amplifier module, and its drain is connected to the ninth PMOS transistor. The source of the transistor MP9; the gate of the sixth PMOS transistor MP6 is used as the negative input terminal of the operational amplifier module, and its drain is connected to the source of the eighth PMOS transistor MP8; the gate of the eighth PMOS transistor MP8 is connected to the ninth PMOS transistor The gate of MP9 and the bias voltage VB, its drain is connected to the drain of the first NMOS transistor MN1 and used as the output terminal VO1 of the operational amplifier module; the gate-drain of the third NMOS transistor MN3 is short-circuited and connected to the ninth PMOS transistor MP9 The drain and the gate of the first NMOS transistor MN1, the source of which is connected to the gate and drain of the fourth NMOS transistor MN4 and the gate of the second NMOS transistor MN2; the drain of the second NMOS transistor MN2 is connected to the first NMOS transistor The source of MN1 is connected to the source of the fourth NMOS transistor MN4 and grounded to GND.

The second PMOS transistor MP2 is a tail current source, the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7 are input pair transistors, the eighth PMOS transistor MP8 and the ninth PMOS transistor MP9 are common gate transistors, and the eighth PMOS transistor MP8 and the seventh PMOS transistor MP8 are input pair transistors. Nine PMOS transistors MP9 preferably use low-threshold transistors, especially when the power supply voltage VDD is low, which can improve the common-mode input range and output swing of the op amp, and VB is the bias voltage of the common-gate transistor. The first NMOS transistor MN1 , the second NMOS transistor MN2 , the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are cascode current mirror loads. The first resistor R1 and the first capacitor C1 are compensating resistors and compensating capacitors, and simultaneously filter the output VO1 of the operational amplifier module to obtain the final output signal EA_OUT of the operational amplifier proposed by the present invention.

The clamping circuit includes two parts: an upper limit clamping module and a lower limit clamping module.

As shown in Figure 1, the upper limit clamping module includes a fifth PMOS transistor MP5, a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a ninth NMOS transistor MN9, a third The resistor R3 and the third capacitor C3, the gate of the fifth PMOS transistor MP5 is connected to the gate of the first PMOS transistor MP1, the drain is connected to the source of the tenth PMOS transistor MP10 and the eleventh PMOS transistor MP11, and the source is connected to Power supply voltage VDD; the gate of the tenth PMOS transistor MP10 is connected to the upper limit clamping voltage VH, and its drain is connected to the drain of the fifth NMOS transistor MN5 and the gate of the ninth NMOS transistor MN9; the gate of the eleventh PMOS transistor MP11 Connect the output terminal VO1 of the operational amplification module to the drain of the ninth NMOS transistor MN9, and its drain is connected to the gate and drain of the sixth NMOS transistor MN6 and the gate of the fifth NMOS transistor MN5; the fifth NMOS transistor MN5, the drain of the fifth NMOS transistor MN5 The sources of the sixth NMOS transistor MN6 and the ninth NMOS transistor MN9 are grounded to GND; one end of the third resistor R3 is connected to the output terminal VO1 of the operational amplifier module, and the other end is connected to the gate of the ninth NMOS transistor MN9 after passing through the third capacitor C3.

In the present invention, the upper limit clamp module adopts a two-stage structure. The first stage structure of the upper limit clamp module includes the fifth PMOS transistor MP5, the tenth PMOS transistor MP10, the eleventh PMOS transistor MP11, the fifth NMOS transistor MN5 and the sixth NMOS transistor. tube MN6, wherein the fifth PMOS tube MP5 is the tail current source, the tenth PMOS tube MP10 and the eleventh PMOS tube MP11 are input pair tubes, the fifth NMOS tube MN5 and the sixth NMOS tube MN6 are current mirror loads, and the first stage The output is VO2. The second stage of the upper limit clamping module is a common source structure, the ninth NMOS transistor MN9 is a common source transistor, and the output VO1 of the operational amplifier module is used as the load of the ninth NMOS transistor MN9. The positive input terminal of the upper limit clamping module, that is, the gate of the tenth PMOS transistor is connected to the preset upper limit clamping voltage VH, and the negative input terminal of the upper limit clamping module is connected to the output VO1 of the operational amplifier module to form a negative feedback. When the Buck converter works in a normal state, VO1<VH, the upper limit clamp circuit works in the comparator state, VO2 is at low level, and the ninth NMOS transistor MN9 is turned off, which does not affect the normal operation of the operational amplifier. When VO1>VH, the upper limit clamp circuit will clamp the output of the op amp, leaving the comparator state, and the upper limit clamp circuit enters the op amp state.

When the upper limit clamp module works in a small signal state, there are two low-frequency poles, and the third resistor R3 and the third capacitor C3 are needed as Miller compensation to separate the two poles to ensure stability. The loop gain of the upper limit clamp circuit can be expressed as :

Among them, g _m is the transconductance of the corresponding MOS tube, and r _o is the equivalent resistance of the corresponding MOS tube. The Miller effect produces an equivalent large capacitance on the gate of the ninth NMOS transistor MN9, forming a low-frequency main pole. In the high frequency range, the compensation capacitor short-circuits the gate-drain of the ninth NMOS transistor MN9 to push up the secondary pole. At the same time, the feedforward effect of the Miller capacitor, namely the third capacitor C3, introduces the zero point in the right half plane, and the position of the zero point is adjusted by the zero adjustment resistor, namely the third resistor R3, to push the zero point to high frequency.

As shown in Figure 1, the lower limit clamping module includes a third PMOS transistor MP3, a fourth PMOS transistor MP4, a twelfth PMOS transistor MP12, a thirteenth PMOS transistor MP13, a fourteenth PMOS transistor MP14, and a fifteenth PMOS transistor MP15. , the seventh NMOS transistor MN7, the eighth NMOS transistor MN8, the second resistor R2 and the second capacitor C2, the gate of the fourth PMOS transistor MP4 is connected to the gate of the third PMOS transistor MP3 and the gate of the first PMOS transistor, which The drain is connected to the source of the twelfth PMOS transistor MP12 and the thirteenth PMOS transistor MP13, and the source is connected to the source of the third PMOS transistor MP3 and connected to the power supply voltage VDD; the gate of the thirteenth PMOS transistor MP13 is connected to the lower limit clamp Bit voltage VL, the drain of which is connected to the drain of the eighth NMOS transistor MN8 and the gate of the fifteenth PMOS transistor MP15; the gate of the twelfth PMOS transistor MP12 is connected to the output terminal VO1 of the operational amplifier module and the fourteenth PMOS transistor The drain of MP14 is connected to the gate and drain of the seventh NMOS transistor MN7 and the gate of the eighth NMOS transistor MN8; the sources of the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 and the fifteenth PMOS transistor The drain of MP15 is grounded to GND; the gate of the fourteenth PMOS transistor MP14 is connected to the drain of the third PMOS transistor MP3 and the source of the fifteenth PMOS transistor MP15, the source of which is connected to the power supply voltage or bias signal, and the second resistor One end of R2 is connected to the gate of the fifteenth PMOS transistor MP15, and the other end is connected to the output end of the operational amplifier module after passing through the second capacitor C2. The bias signal is provided by the sixteenth PMOS transistor which forms a current mirror with the first PMOS transistor, the gate of the sixteenth PMOS transistor is connected to the gate of the first PMOS transistor, its source is connected to the power supply voltage, and its drain generates a bias set signal. In some embodiments, the second PMOS transistor in the operational amplifier module can also be used as the sixteenth PMOS transistor for providing the bias signal, as shown in FIG. 1 .

The lower limit clamping module has a three-stage structure. The first stage includes the fourth PMOS transistor MP4 of the tail current source, the twelfth PMOS transistor MP12 and the thirteenth PMOS transistor MP13 of the input pair, and the seventh NMOS transistor MN7 and the thirteenth PMOS transistor MP13 of the current mirror load. Eight NMOS tubes MN8. The second stage of the lower limit clamping circuit includes the fifteenth PMOS transistor MP15 and the third PMOS transistor MP3 as a level shift circuit, which raises the output level of the first stage of the lower limit clamping module, and the output level of the second stage of the lower limit clamping circuit Signal VO3. The third stage of the lower limit clamping module uses the fourteenth PMOS transistor MP14 as a common source transistor, and uses the output VO1 of the operational amplifier module as a load. The positive input terminal of the lower limit clamping circuit is the gate of the thirteenth PMOS transistor MP13 connected to the preset lower limit clamping voltage VL, the negative input terminal of the lower limit clamping circuit is the gate of the twelfth PMOS transistor MP12 and the operational amplifier The output VO1 is connected to form a negative feedback. When the Buck converter works in the normal state, VO1>VL, the lower limit clamp circuit works in the comparator state, VO3 is high level, and the fourteenth PMOS transistor MP14 is turned off, which does not affect the normal operation of the op amp. When VO1<VL, the lower limit clamp circuit will clamp the output VO1 of the op amp, leaving the comparator state, and the lower limit clamp circuit enters the op amp state. The second resistor R2 and the second capacitor C2 are compensation resistors and capacitors of the lower limit clamping circuit.

When the clamp circuit works in the comparator state, VO2 and VO3 can be considered as AC ground, and the Miller capacitance, namely the second capacitor C2 and the third capacitor C3, become the load capacitance of the main op amp, and a secondary pole is introduced into the main op amp . Regardless of the internal high-frequency parasitic poles and mirror zero poles, the transfer function of the op amp can be expressed as:

The secondary pole introduced by the second capacitor C2 and the third capacitor C3 of the Miller capacitor of the clamping circuit is at a high frequency and will not cause too much influence on the loop. The whole system can be kept stable, thereby realizing the normal operation of the op amp and the output clamping in the response state.

In summary, the present invention proposes an operational amplifier with an output clamping function, which can be applied to a Buck converter. When the Buck converter is operating in a normal state, the output VO1 of the operational amplifier module is less than the preset upper limit clamping voltage VH , the output VO1 of the operational amplifier module is greater than the preset lower limit clamp voltage VL, the upper limit clamp circuit and the lower limit clamp circuit work in the comparator state, the output VO2 of the upper limit clamp circuit is low level, and the ninth NMOS tube MN9 is turned off is off, the output VO3 of the lower limit clamping circuit is at high level, and the fourteenth PMOS transistor MP14 is turned off, which does not affect the normal operation of the operational amplifier. When the output VO1 of the operational amplifier module is greater than the upper limit clamp voltage VH, the upper limit clamp circuit will clamp the output of the op amp, leaving the comparator state, and the upper limit clamp circuit enters the op amp state. When the output VO1 of the operational amplifier module is less than the lower limit clamp voltage VL, the lower limit clamp circuit will clamp the output VO1 of the op amp, leaving the comparator state, and the lower limit clamp circuit enters the op amp state. It can be seen that the present invention adds output upper limit clamping and lower limit clamping functions to the operational amplifier, which can speed up the response speed of the Buck converter and save power consumption.

Those skilled in the art can make various other specific modifications and combinations based on the technical revelations disclosed in the present invention without departing from the essence of the present invention, and these modifications and combinations are still within the protection scope of the present invention.

Claims (4)

1. An operational amplifier with an output clamping function, comprising an operational amplifier module, a first resistor, a first capacitor, a bias module, an upper limit clamp module and a lower limit clamp module, The bias module is used to provide bias for the operational amplification module, the upper limit clamp module and the lower limit clamp module, including a first PMOS transistor, the gate-drain of the first PMOS transistor is short-circuited and connected to a bias current, and its source Pole connected to the supply voltage; The positive input terminal of the operational amplifier module is used as the positive input terminal of the operational amplifier, its negative input terminal is used as the negative input terminal of the operational amplifier, and its output terminal passes through the first resistor and the first capacitor in turn. grounding; the connection point of the first resistor and the first capacitor is used as the output terminal of the operational amplifier; It is characterized in that the upper limit clamping module includes a fifth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a ninth NMOS transistor, a third resistor and a third capacitor, The gate of the fifth PMOS transistor is connected to the gate of the first PMOS transistor, its drain is connected to the sources of the tenth PMOS transistor and the eleventh PMOS transistor, and its source is connected to the power supply voltage; The gate of the tenth PMOS transistor is connected to the upper limit clamping voltage, and its drain is connected to the drain of the fifth NMOS transistor and the gate of the ninth NMOS transistor; The gate of the eleventh PMOS transistor is connected to the output terminal of the operational amplification module and the drain of the ninth NMOS transistor, and its drain is connected to the gate and drain of the sixth NMOS transistor and the gate of the fifth NMOS transistor; The sources of the fifth NMOS transistor, the sixth NMOS transistor and the ninth NMOS transistor are grounded; One end of the third resistor is connected to the output end of the operational amplification module, and the other end is connected to the gate of the ninth NMOS transistor after passing through the third capacitor; The lower limit clamping module includes a third PMOS transistor, a fourth PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor , the second resistor and the second capacitor, The gate of the fourth PMOS transistor is connected to the gate of the third PMOS transistor and the gate of the first PMOS transistor, its drain is connected to the sources of the twelfth PMOS transistor and the thirteenth PMOS transistor, and its source is connected to the third PMOS transistor. The source of the tube is connected to the supply voltage; The gate of the thirteenth PMOS transistor is connected to the lower limit clamping voltage, and its drain is connected to the drain of the eighth NMOS transistor and the gate of the fifteenth PMOS transistor; The gate of the twelfth PMOS transistor is connected to the output terminal of the operational amplification module and the drain of the fourteenth PMOS transistor, and its drain is connected to the gate and drain of the seventh NMOS transistor and the gate of the eighth NMOS transistor; The sources of the seventh NMOS transistor and the eighth NMOS transistor and the drain of the fifteenth PMOS transistor are grounded; The gate of the fourteenth PMOS transistor is connected to the drain of the third PMOS transistor and the source of the fifteenth PMOS transistor, and its source is connected to a power supply voltage or a bias signal, and the bias signal is composed of a current with the first PMOS transistor The sixteenth PMOS tube of the mirror is provided, the gate of the sixteenth PMOS tube is connected to the gate of the first PMOS tube, its source is connected to the power supply voltage, and its drain generates the bias signal; One end of the second resistor is connected to the gate of the fifteenth PMOS transistor, and the other end is connected to the output end of the operational amplification module after passing through the second capacitor. 2. The operational amplifier with output clamping function according to claim 1, wherein the operational amplifier module comprises a second PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, PMOS transistors, first NMOS transistors, second NMOS transistors, third NMOS transistors, and fourth NMOS transistors, The gate of the second PMOS transistor is connected to the gate of the first PMOS transistor, its source is connected to the power supply voltage, and its drain is connected to the sources of the sixth PMOS transistor and the seventh PMOS transistor; The gate of the seventh PMOS transistor is used as the positive input terminal of the operational amplifier module, and its drain is connected to the source of the ninth PMOS transistor; The gate of the sixth PMOS transistor is used as the negative input terminal of the operational amplifier module, and its drain is connected to the source of the eighth PMOS transistor; The gate of the eighth PMOS transistor is connected to the gate and bias voltage of the ninth PMOS transistor, and its drain is connected to the drain of the first NMOS transistor and used as the output terminal of the operational amplification module; The gate-drain of the third NMOS transistor is short-circuited and connected to the drain of the ninth PMOS transistor and the gate of the first NMOS transistor, and its source is connected to the gate and drain of the fourth NMOS transistor and the gate of the second NMOS transistor; The drain of the second NMOS transistor is connected to the source of the first NMOS transistor, and the source thereof is connected to the source of the fourth NMOS transistor and grounded. 3. The operational amplifier with output clamping function according to claim 2, wherein the sixteenth PMOS transistor is the second PMOS transistor in the operational amplification module. 4. The operational amplifier with output clamping function according to claim 2 or 3, wherein the eighth PMOS transistor and the ninth PMOS transistor are low-threshold PMOS transistors.

Images