CN111597044A - Task scheduling method and device, storage medium and electronic equipment - Google Patents

Abstract

The embodiment of the application discloses a task scheduling method, a task scheduling device, a storage medium and electronic equipment, wherein the method comprises the following steps: when a first CPU in a plurality of CPUs in a system enters an idle state to trigger load balancing, acquiring task switching time of each task on other CPUs except the first CPU in the CPUs; and acquiring the farthest time from the current time in the task switching time, and scheduling the target task indicated by the farthest time from the current time to other CPUs except the CPU where the target task is currently located to run. Therefore, by adopting the embodiment of the application, the scheduling delay can be reduced while the load balance is realized.

Description

Task scheduling method, device, storage medium and electronic device

technical field

The present application relates to the field of computer technology, and in particular, to a task scheduling method, device, storage medium and electronic device.

Background technique

When a task wakes up or a task is created, when selecting a running CPU, consider the current load of each of the multiple CPUs included in the system to maintain load balancing, and, based on CPU idle (IDLE) load balancing, in the CPU When there is a load imbalance between them, some tasks are shifted from the CPU with high load to the CPU with lower load.

The above operations generally ensure load balancing on the CPU, but load balancing does not necessarily mean that tasks can be executed in a timely manner. In the Linux system, some operations (such as atomic locks, soft interrupts, hardware interrupts, etc.) will disable task preemption, that is, task scheduling is not allowed. In this case, even if the task is woken up and its virtual time (vruntime) is the lowest, it cannot obtain CPU resources, and it has been in a waiting state until the above operations (atomic locks, etc.) are completed to obtain CPU resources.

SUMMARY OF THE INVENTION

Embodiments of the present application provide a task scheduling method, apparatus, storage medium, and electronic device, which can reduce scheduling delay while achieving load balancing. The technical solution is as follows:

In a first aspect, an embodiment of the present application provides a task scheduling method, the method comprising:

When the first CPU of the plurality of central processing units (CPUs) included in the system enters an idle state to trigger load balancing, obtain the task switching time of each task on the remaining CPUs in the plurality of CPUs except the first CPU;

Obtain the farthest time from the current time in the task switching time, and schedule the target task indicated by the farthest time from the current time to run on other CPUs other than the CPU where the target task is currently located.

In a second aspect, an embodiment of the present application provides a task scheduling apparatus, and the apparatus includes:

A time acquisition module, configured to acquire tasks on other CPUs in the multiple CPUs except the first CPU when the first CPU of the multiple central processing units (CPUs) included in the system enters an idle state and triggers load balancing task switching time;

A task scheduling module, configured to obtain the farthest time from the current time in the task switching time, and schedule the target task indicated by the farthest time from the current time to the remaining CPUs other than the CPU where the target task is currently located run on.

In a third aspect, an embodiment of the present application provides a computer storage medium, where the computer storage medium stores a plurality of instructions, and the instructions are suitable for being loaded by a processor and executing the above method steps.

In a fourth aspect, an embodiment of the present application provides an electronic device, which may include: a processor and a memory; wherein, the memory stores a computer program, and the computer program is adapted to be loaded by the processor and execute the above method steps .

The beneficial effects brought by the technical solutions provided by some embodiments of the present application include at least:

In this embodiment of the present application, when the first CPU among the multiple CPUs included in the system enters an idle state and triggers load balancing, the tasks of the tasks on the remaining CPUs in the multiple CPUs except the first CPU are obtained Switching time, and then obtain the farthest time from the current time in the task switching time, and schedule the target task indicated by the farthest time from the current time to run on the remaining CPUs other than the CPU where the target task is currently located. . When the CPU enters the idle state to trigger the load balancing, according to the task switching time of each task, the tasks that have not been run for a long time for some reasons can be scheduled to the remaining CPUs, so that the load balancing can be achieved at the same time. Scheduling delays can also be reduced.

Description of drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only These are some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without any creative effort.

1 is a schematic flowchart of a task scheduling method provided by an embodiment of the present application;

2 is a schematic structural diagram of a multitasking system provided by an embodiment of the present application;

FIG. 3 is an exemplary schematic diagram of a time relationship of task scheduling provided by an embodiment of the present application;

4 is a schematic flowchart of a task scheduling method provided by an embodiment of the present application;

FIG. 5 is a schematic structural diagram of a task scheduling apparatus provided by an embodiment of the present application;

6 is a schematic structural diagram of a task scheduling apparatus provided by an embodiment of the present application;

FIG. 7 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present application clearer, the embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

Where the following description refers to the drawings, the same numerals in different drawings refer to the same or similar elements unless otherwise indicated. The implementations described in the illustrative examples below are not intended to represent all implementations consistent with this application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application, as recited in the appended claims.

In the description of the present application, it should be understood that the terms "first", "second" and the like are used for descriptive purposes only, and should not be construed as indicating or implying relative importance. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood in specific situations. Also, in the description of the present application, unless otherwise specified, "a plurality" means two or more. "And/or", which describes the association relationship of the associated objects, means that there can be three kinds of relationships, for example, A and/or B, which can mean that A exists alone, A and B exist at the same time, and B exists alone. The character "/" generally indicates that the associated objects are an "or" relationship.

The task scheduling method provided by the embodiment of the present application will be described in detail below with reference to FIG. 1 to FIG. 4 . The method can be implemented by relying on a computer program, and can be run on a task scheduling device based on the von Neumann system. The computer program can be integrated into an application or run as a stand-alone utility application. Wherein, the task scheduling apparatus in this embodiment of the present application may be a user terminal, and the user terminal includes but is not limited to: a smart phone, a personal computer, a tablet computer, a handheld device, a vehicle-mounted device, a wearable device, a computing device, or a device connected to a wireless Other processing equipment of the modem, etc.

Please refer to FIG. 1 , which is a schematic flowchart of a task scheduling method provided by an embodiment of the present application. As shown in FIG. 1, the method of the embodiment of the present application may include the following steps:

S101 , when a first CPU among the multiple central processing units (CPUs) included in the system enters an idle state and triggers load balancing, obtain the task switching time of each task on the remaining CPUs in the multiple CPUs except the first CPU ;

The embodiments of the present application are applied in a multi-central processing unit (Central Processing Unit, CPU) system, which includes multiple CPUs.

Among them, the CPU is the computing core and control core of a computer, and is the final execution unit for information processing and program operation. The CPU includes arithmetic logic components, register components, control components, etc., and has functions such as processing instructions, executing operations, controlling time, and processing data.

The performance of the CPU is mainly reflected in the speed at which it runs programs. The performance indicators that affect the running speed include parameters such as the operating frequency of the CPU, Cache capacity, instruction system and logical structure. The CPU load is the CPU usage rate. When the CPU usage rate is high, the CPU runs slowly, and the CPU usage can be limited by CPU frequency modulation.

Multi-CPU systems generally include four different forms, namely, Multiprocessor Systems, Multicomputer Systems, Network Systems, and Distributed Systems.

A multi-processor system refers to two or more processors with similar functions. The processors can exchange data with each other. All processors share memory, I/O devices, controllers, and external devices. The entire hardware system consists of a unified system. It realizes full parallelism at all levels of jobs, tasks, programs, arrays and even elements between processors and programs.

For example, FIG. 2 is a schematic structural diagram of a multi-CPU system. The system includes multiple CPUs, and the multiple CPUs share memory. The system may be an SMP system or an HMP system.

The difference between the SMP and the HMP system is that the multiple CPUs of the SMP system have the same performance, while the multiple CPUs of the HMP system have different performances.

It should be noted that each CPU has different computing capabilities. Even if the computing capabilities of each CPU are the same, due to different tasks running on each CPU at different times, there will be differences in the remaining computing capabilities. The remaining computing capacity refers to the capacity of the remaining CPU resources available for computing at a certain moment in addition to the CPU resources occupied by tasks running on the CPU.

When a certain CPU (the first CPU) enters the idle (IDLE) state to trigger load balancing, or when a tick triggers load balancing, it indicates that the first CPU has enough resources for one or some tasks to run. Therefore, in order to To maintain system load balance, it is necessary to detect tasks in the task queues on the remaining CPUs that have been waiting for a long time and have not been allocated CPU resources. Load balancing is to distribute tasks to multiple operating units for execution, such as Web servers, FTP servers, enterprise key application servers and other mission-critical servers, so as to complete work tasks together. In this embodiment of the present application, it refers to scheduling tasks to run on other CPUs to achieve load balancing.

Specifically, the task switching time last_sched_ts of each task needs to be acquired, and the task switching time last_sched_ts refers to the time when a task is awakened or the time that is forcibly scheduled because the time slice is exhausted. That is, the difference between the task switching time and the current time is the delay time before obtaining CPU resources. When last_sched_ts is smaller, it indicates that the distance from the current time is farther, that is, the delay time before obtaining CPU resources is longer.

Among them, a task can be regarded as a thread. Usually a process can contain at least one thread. Threads can utilize the resources owned by processes. In operating systems that introduce threads, processes are usually used as the basic unit for allocating resources, and threads are used as the basic unit for independent operation and independent scheduling. Since a thread is smaller than a process and basically does not own system resources, the overhead for its scheduling will be much smaller, which can more efficiently improve the degree of concurrent execution among multiple programs in the system.

Generally, a process has the following three basic states: ready (Ready) state, executing (Running) state and blocking (Blocked) state.

Among them, when the process has the running conditions (all necessary resources except the CPU have been allocated), it can be executed immediately as long as the CPU resources are obtained, and the process state at this time is called the ready state.

When the process has obtained the CPU and its program is being executed on the CPU, the process state at this time is called the execution state.

When a process that is executing cannot be executed due to waiting for an event to occur, it will give up the CPU and be in a blocking state. There can be various events that cause a process to block, for example, waiting for I/O to complete, requesting a buffer that cannot be satisfied, waiting for a signal, and so on.

For each task, its running state is the same as the running state of the owning process. In the embodiments of the present application, the targeted tasks refer to the assumption that the running state is the ready state. For example, the task can be a wake-up task or a time that is forcibly scheduled because the time slice runs out, or a newly created task. In short, it is from Ready to tasks that need to obtain CPU resources.

S102: Acquire the farthest time from the current time in the task switching time, and schedule the target task indicated by the farthest time from the current time to run on other CPUs other than the CPU where the target task is currently located.

It can be understood that whenever a task switch occurs on the CPU, the task switch time last_sched_ts of the task needs to be updated. If the task is actively giving up CPU resources, set the last_sched_ts of the task to 0. If it is forced to switch out or wake up because the time slice is used up, set the last_sched_ts of the task to the time when the task switch occurs. . This process continues in real time or periodically, so the recorded last_sched_ts are all times before the current time.

It should be noted that the current time refers to the time when the task switching time of each task on each CPU is obtained in this round.

For example, as shown in Figure 3, every time any CPU among the multiple CPUs included in the system enters an idle state to trigger load balancing, task scheduling needs to be performed, or when the system detects and triggers task scheduling every preset period, it needs to execute round of this program. If the current time is t1, that is, the trigger time of the current round of execution of this scheme, the trigger time of the previous round of execution of this scheme is t0, and the trigger time of the next round of execution of this scheme is t2, then the statistics need to be within the period of t0 to t1. , the task switching time of each task, for example, recorded as ta, tb, tc, you need to calculate t1-ta, t1-tb, t1-tc, the difference is the largest, indicating that it is the farthest from the current time, and the task waits for the time to allocate CPU resources Therefore, the task needs to be scheduled preferentially to obtain CPU resources, specifically, scheduling to run on other CPUs other than the CPU where the target task is currently located.

For example, if the system includes CPU A, CPU B, CPU C, and CPU D, and the target task is currently running on CPU A, and CPU B is the first CPU, the target task can be scheduled to run on CPU B or on CPU B. , CPU C and CPU D run on a CPU with a small load and a large task switching time, and it can also be the CPU with the largest remaining computing power among CPU B, CPU C, and CPU D.

Of course, the target task can include one or more. When the target task includes multiple tasks, the multiple tasks can be added to the stack or queue and scheduled in sequence.

In this embodiment of the present application, when the first CPU among the multiple CPUs included in the system enters an idle state and triggers load balancing, the tasks of the tasks on the remaining CPUs in the multiple CPUs except the first CPU are obtained Switching time, and then obtain the farthest time from the current time in the task switching time, and schedule the target task indicated by the farthest time from the current time to run on the remaining CPUs other than the CPU where the target task is currently located. . When the CPU enters the idle state to trigger the load balancing, according to the task switching time of each task, the tasks that have not been run for a long time for some reasons can be scheduled to the remaining CPUs, so that the load balancing can be achieved at the same time. Scheduling delays can also be reduced.

Please refer to FIG. 4 , which is a schematic flowchart of a task scheduling method provided by an embodiment of the present application. The difference between the embodiment shown in Figure 4 and the embodiment shown in Figure 1 is that Figure 1 emphasizes the idea of obtaining task switching time for task scheduling when triggering load balancing, and Figure 4 describes the specific implementation of the solution , emphasizing the specific method of obtaining the task switching time of each task from the process description structure, and the scheme of updating and saving the task switching time. The task scheduling method may include the following steps:

S201, when the first CPU of the plurality of CPUs included in the system enters an idle state and triggers load balancing, obtain the process description structure corresponding to each task on the remaining CPUs in the plurality of CPUs except the first CPU;

The embodiments of the present application are applied in a multi-central processing unit (Central Processing Unit, CPU) system, which includes multiple CPUs. The system may be an SMP system or an HMP system.

When a certain CPU (the first CPU) enters the idle (IDLE) state to trigger load balancing, or when a tick triggers load balancing, it indicates that the first CPU has enough resources for one or some tasks to run. Therefore, in order to To maintain system load balance, it is necessary to detect tasks in the task queues on the remaining CPUs that have been waiting for a long time and have not been allocated CPU resources. Specifically, the process description structure of each task needs to be obtained to read the task switching time last_sched_ts.

When a program is loaded into memory, at this point, there is a process. Regarding the process, there is a related structure called the process control block (PCB), which is a data structure set by the system to facilitate the management of the process. Through the PCB, the characteristics of the process and some information can be recorded. The process descriptor task_struct is used in the kernel.

task_struct is a structure through which all relevant information of the process can be maintained and managed, which is usually defined in the include/linux/sched.h file.

For example, a process description structure is as follows:

Specifically, the process description structures corresponding to the tasks on the remaining CPUs except the first CPU are respectively obtained.

S202, acquiring a switching time field in a process description structure corresponding to each task, and acquiring a task switching time corresponding to each of the switching time fields;

The switching time field last_sched_ts is included in the above process description structure. last_sched_ts refers to the time when a task was woken up or the time it was forced to be scheduled out because the time slice was exhausted.

The difference between the task switching time and the current time is the delay time before obtaining CPU resources. The smaller the last_sched_ts, the farther from the current time, that is, the longer the delay time before obtaining CPU resources.

S203, obtaining the farthest time from the current time in the task switching time;

It can be understood that, first determine the corresponding minimum last_sched_ts on each CPU, and then find the minimum last_sched_ts, that is, the farthest time from the current time.

Optionally, when there are many remaining resources of the first CPU, multiple tasks in the task switching time that are longer from the current time, such as the first three, may also be acquired.

Optionally, each task has a corresponding priority that determines when it runs and how much CPU resources it receives. The Windows system has a total of 32 priority levels, which are values from 0 to 31, called the basic priority. The system schedules the operation of tasks according to different priorities. Among them, levels 0-15 are common priorities. The priority of tasks can be dynamically changed. High-priority tasks run first. Only when high-priority tasks are not running, low-priority tasks are scheduled. Tasks with the same priority run in turn according to the time slice. Level 16-31 is the real-time priority. The biggest difference between the real-time priority and the ordinary priority is that the operation of the same priority task does not rotate according to the time slice, but the task that runs first will control the CPU first. If it does not voluntarily give up control, Tasks of the same or lower priority cannot run. The priority of Linux system ranges from 0-140, 0-99 represents real-time tasks, and 100-140 represents non-real-time tasks. Contrary to Windows, the smaller the Linux priority value, the higher the level, and the priority of the task to be scheduled by the kernel.

In the embodiments of the present application, it is not limited to a Windows system or a Linux system. It is possible to first determine a plurality of tasks with a long distance from the current time, and a plurality of tasks waiting for allocation of CPU resources for a long time, and then according to the priority of each task, determine one or more target tasks to be scheduled.

S204, when the farthest time from the current time is greater than or equal to a preset threshold, schedule the target task indicated by the farthest time from the current time to run on the first CPU, or schedule the target task indicated by the farthest time from the current time to run on the first CPU. The target task indicated by the farthest time in time is scheduled to run on a second CPU, where the second CPU is a CPU with a load less than a load threshold among the plurality of CPUs, and the task switching time corresponding to the CPU is the closest to the current time;

It can be understood that when the farthest time from the current time is less than the preset threshold, it indicates that the target task indicated by the farthest time has not waited for a long time to allocate CPU resources, and does not need to be scheduled to the remaining CPUs, and continue to wait. Can. At this time, compared to scheduling on other CPUs, the amount of calculation is increased. Therefore, when the farthest time from the current time is greater than or equal to the preset threshold, it indicates that the target task indicated by the farthest time waits for a long time to allocate CPU resources and needs to be scheduled.

Since the first CPU enters an idle state, there are enough CPU resources left and no task to process, therefore, the target task can be preferentially scheduled to the first CPU, so that the target task can be quickly allocated CPU resources for running.

Alternatively, in addition to the first CPU, there is a second CPU with large remaining computing capacity and a low load, and there is no waiting for a long task to be executed, the target task can be scheduled to run on the second CPU.

Of course, if the number of target tasks is large, the plurality of target tasks can also be scheduled to the first CPU and the second CPU respectively, so that the scheduling and running of multiple tasks can be satisfied.

S205 , when detecting that a task switching event occurs on at least one of the multiple CPUs, update the task switching time of each task on the multiple CPUs.

Before reaching the next round of task scheduling time (between t1 and t2 in Figure 3), if a task switching event (such as a task being woken up or forced to be scheduled, etc.) is detected on a certain CPU or multiple CPUs, Then, the task switching time last_sched_ts of the task on the CPU is updated, and updated to the time when the task switching event occurs. If a task switching event occurs in multiple tasks, they are updated respectively.

Specifically, when it is determined that the switching state corresponding to the task switching event is the awakened state or the forced scheduling state, the task switching time of each task on the multiple CPUs is set to the current time, and the task switching event corresponding to the task switching event is determined. When the switching state is not the awakened state or the forced scheduling state, the task switching time of each task on the multiple CPUs is set to zero.

Further, when it is determined that the switching state corresponding to the task switching is the awakened state or the forced scheduling state, the task switching time is saved according to the order of the task switching time (such as in the form of a red-black tree), so as to facilitate the next time. During round task scheduling, task scheduling is performed based on the saved task switching time.

It should be noted that, before the first CPU among the multiple central processing units (CPUs) included in the system enters an idle state and triggers load balancing (in the time period from t0 to t1 in FIG. 3 ), when the multiple CPUs are detected When a task switching event occurs on at least one of the CPUs, the task switching time of each task on the multiple CPUs is updated.

Specifically, when it is determined that the switching state corresponding to the task switching event is the awakened state or the forced scheduling state, the task switching time of each task on the multiple CPUs is set to the current time; the task switching time corresponding to the task switching event is determined. When the switching state is not the awakened state or the forced scheduling state, the task switching time of each task on the multiple CPUs is set to zero.

When it is determined that the switching state corresponding to the task switching is the awakened state or the forced scheduling state, the task switching time is saved according to the order of the task switching time.

In the embodiment of the present application, the triggering timing of load balancing is triggered by the CPU entering the idle state, and the scheduling delay is calculated according to the task switching time of each task, so that the task with a larger scheduling delay can be scheduled to the idle first CPU or the load It runs on the second CPU with low scheduling delay and low scheduling delay, so that load balancing can be achieved while scheduling delay can be reduced, system performance can be improved, and user experience can be improved. In addition, before or after scheduling, updating and saving the task switching time of the task in time can ensure that the task scheduling time obtained during task scheduling is accurate and effective, thereby improving the accuracy of task scheduling.

The following are apparatus embodiments of the present application, which can be used to execute the method embodiments of the present application. For details not disclosed in the device embodiments of the present application, please refer to the method embodiments of the present application.

Please refer to FIG. 5 , which shows a schematic structural diagram of a task scheduling apparatus provided by an exemplary embodiment of the present application. The task scheduling apparatus can be implemented as a whole or a part of the electronic device through software, hardware or a combination of the two. The device 1 includes a time acquisition module 10 and a task scheduling module 20 .

The time acquisition module 10 is configured to acquire, when the first CPU of the plurality of central processing units (CPUs) included in the system enters an idle state and triggers load balancing, obtain the time acquisition module 10 of each of the remaining CPUs of the plurality of CPUs except the first CPU. The task switching time of the task;

The task scheduling module 20 is used to obtain the farthest time from the current time in the task switching time, and schedule the target task indicated by the farthest time from the current time to the rest of the CPU where the target task is currently located. run on the CPU.

Optionally, the time acquisition module 10 is specifically used for:

Obtain the process description structure corresponding to each task on the remaining CPUs except the first CPU in the plurality of CPUs;

The switching time field in the process description structure corresponding to each task is acquired, and the task switching time corresponding to each switching time field is acquired.

Optionally, the task scheduling module 20 is specifically used for:

When the farthest time from the current time is greater than or equal to a preset threshold, the target task indicated by the farthest time from the current time is scheduled to run on other CPUs other than the CPU where the target task currently resides.

Optionally, the task scheduling module 20 is specifically used for:

The target task indicated by the farthest time from the current time is scheduled to run on the first CPU, or the target task indicated by the farthest time from the current time is scheduled to run on the second CPU. The second CPU is a CPU whose load is less than a load threshold among the plurality of CPUs, and the task switching time corresponding to the CPU is the closest to the current time.

Optionally, as shown in FIG. 6 , the device further includes a time update module 30 for:

When it is detected that a task switching event occurs on at least one of the multiple CPUs, the task switching time of each task on the multiple CPUs is updated.

Optionally, the time update module 30 is specifically used for:

When it is determined that the switching state corresponding to the task switching event is the awakened state or the forced scheduling state, the task switching time of each task on the multiple CPUs is set to the current time;

When it is determined that the switching state corresponding to the task switching event is not the awakened state or the forced scheduling state, the task switching time of each task on the multiple CPUs is set to zero.

Optionally, as shown in FIG. 6 , the device further includes a time saving module 40 for:

When it is determined that the switching state corresponding to the task switching is the awakened state or the forced scheduling state, the task switching time is saved according to the order of the task switching time.

It should be noted that, when the task scheduling apparatus provided in the above embodiments executes the task scheduling method, only the division of the above functional modules is used as an example for illustration. In practical applications, the above functions may be allocated to different functional modules as required. , that is, dividing the internal structure of the device into different functional modules to complete all or part of the functions described above. In addition, the task scheduling apparatus and the task scheduling method embodiments provided by the above embodiments belong to the same concept, and the implementation process of the embodiment is described in the method embodiments, which will not be repeated here.

The above-mentioned serial numbers of the embodiments of the present application are only for description, and do not represent the advantages or disadvantages of the embodiments.

In the embodiment of the present application, the triggering timing of load balancing is triggered by the CPU entering the idle state, and the scheduling delay is calculated according to the task switching time of each task, so that the task with a larger scheduling delay can be scheduled to the idle first CPU or the load It runs on the second CPU with low scheduling delay and low scheduling delay, so that load balancing can be achieved while scheduling delay can be reduced and user experience can be improved. In addition, before or after scheduling, updating and saving the task switching time of the task in time can ensure that the task scheduling time obtained during task scheduling is accurate and effective, thereby improving the accuracy of task scheduling.

An embodiment of the present application further provides a computer storage medium, where the computer storage medium can store multiple instructions, and the instructions are suitable for being loaded by a processor and executing the method steps of the embodiments shown in FIG. 1 to FIG. 4 above. , and the specific execution process may refer to the specific description of the embodiments shown in FIG. 1 to FIG. 4 , which will not be repeated here.

Please refer to FIG. 7 , which is a schematic structural diagram of an electronic device according to an embodiment of the present application. As shown in FIG. 7 , the electronic device 1000 may include: at least one processor 1001 , at least one network interface 1004 , user interface 1003 , memory 1005 , and at least one communication bus 1002 .

Among them, the communication bus 1002 is used to realize the connection and communication between these components.

The user interface 1003 may include a display screen (Display) and a camera (Camera), and the optional user interface 1003 may also include a standard wired interface and a wireless interface.

Wherein, the network interface 1004 may optionally include a standard wired interface and a wireless interface (eg, a WI-FI interface).

The processor 1001 may include one or more processing cores. The processor 1001 uses various excuses and lines to connect various parts of the entire electronic device 1000, and executes by running or executing the instructions, programs, code sets or instruction sets stored in the memory 1005, and calling the data stored in the memory 1005. Various functions of the electronic device 1000 and processing data. Optionally, the processor 1001 may employ at least one of a digital signal processing (Digital Signal Processing, DSP), a Field-Programmable Gate Array (Field-Programmable Gate Array, FPGA), and a Programmable Logic Array (Programmable Logic Array, PLA). A hardware form is implemented. The processor 1001 may integrate one or a combination of a central processing unit (Central Processing Unit, CPU), a graphics processing unit (Graphics Processing Unit, GPU), a modem, and the like. Among them, the CPU mainly handles the operating system, user interface, and application programs; the GPU is used to render and draw the content that needs to be displayed on the display screen; the modem is used to handle wireless communication. It can be understood that, the above-mentioned modem may not be integrated into the processor 1001, but is implemented by a single chip.

The memory 1005 may include random access memory (Random Access Memory, RAM), or may include read-only memory (Read-Only Memory). Optionally, the memory 1005 includes a non-transitory computer-readable storage medium. Memory 1005 may be used to store instructions, programs, codes, sets of codes, or sets of instructions. The memory 1005 may include a stored program area and a stored data area, wherein the stored program area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playback function, an image playback function, etc.), Instructions and the like used to implement the above method embodiments; the storage data area may store the data and the like involved in the above method embodiments. Optionally, the memory 1005 may also be at least one storage device located away from the aforementioned processor 1001 . As shown in FIG. 7 , the memory 1005 as a computer storage medium may include an operating system, a network communication module, a user interface module, and a task scheduling application program.

In the electronic device 1000 shown in FIG. 7 , the user interface 1003 is mainly used to provide an input interface for the user and obtain the data input by the user; and the processor 1001 can be used to call the task scheduling application program stored in the memory 1005, and specifically Do the following:

When the first CPU of the plurality of central processing units (CPUs) included in the system enters an idle state to trigger load balancing, obtain the task switching time of each task on the remaining CPUs in the plurality of CPUs except the first CPU;

Obtain the farthest time from the current time in the task switching time, and schedule the target task indicated by the farthest time from the current time to run on other CPUs other than the CPU where the target task is currently located.

In one embodiment, the processor 1001 specifically performs the following operations when acquiring the task switching time of each task on the remaining CPUs in the plurality of CPUs except the first CPU:

Obtain the process description structure corresponding to each task on the remaining CPUs except the first CPU in the plurality of CPUs;

The switching time field in the process description structure corresponding to each task is acquired, and the task switching time corresponding to each switching time field is acquired.

In one embodiment, when the processor 1001 executes scheduling the target task indicated by the farthest time from the current time to run on other CPUs other than the CPU where the target task is currently located, the processor 1001 specifically performs the following operations :

When the farthest time from the current time is greater than or equal to a preset threshold, the target task indicated by the farthest time from the current time is scheduled to run on other CPUs other than the CPU where the target task currently resides.

In one embodiment, when the processor 1001 executes scheduling the target task indicated by the farthest time from the current time to run on other CPUs other than the CPU where the target task is currently located, the processor 1001 specifically performs the following operations :

The target task indicated by the farthest time from the current time is scheduled to run on the first CPU, or the target task indicated by the farthest time from the current time is scheduled to run on the second CPU. The second CPU is a CPU whose load is less than a load threshold among the plurality of CPUs, and the task switching time corresponding to the CPU is the closest to the current time.

In one embodiment, the processor 1001 further performs the following operations:

When it is detected that a task switching event occurs on at least one of the multiple CPUs, the task switching time of each task on the multiple CPUs is updated.

In one embodiment, the processor 1001 specifically performs the following operations when updating the task switching time of each task on the multiple CPUs:

When it is determined that the switching state corresponding to the task switching event is the awakened state or the forced scheduling state, the task switching time of each task on the multiple CPUs is set to the current time;

When it is determined that the switching state corresponding to the task switching event is not the awakened state or the forced scheduling state, the task switching time of each task on the multiple CPUs is set to zero.

In one embodiment, the processor 1001 further performs the following operations:

When it is determined that the switching state corresponding to the task switching is the awakened state or the forced scheduling state, the task switching time is saved according to the order of the task switching time.

In this embodiment of the present application, the triggering timing is when the CPU enters an idle state to trigger load balancing, and the scheduling delay is calculated according to the task switching time of each task, so that a task with a larger scheduling delay can be scheduled to the idle first CPU or load It runs on the second CPU with low scheduling delay and low scheduling delay, so that load balancing can be achieved while scheduling delay can be reduced and user experience can be improved. In addition, before or after scheduling, updating and saving the task switching time of the task in time can ensure that the task scheduling time obtained during task scheduling is accurate and effective, thereby improving the accuracy of task scheduling.

Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be implemented by instructing relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium. During execution, the processes of the embodiments of the above-mentioned methods may be included. Wherein, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, or a random storage memory, and the like.

The above disclosures are only the preferred embodiments of the present application, and of course, the scope of the rights of the present application cannot be limited by this. Therefore, equivalent changes made according to the claims of the present application are still within the scope of the present application.

Claims (10)

1. A method for task scheduling, the method comprising:

when a first CPU in a plurality of CPUs in a system enters an idle state to trigger load balancing, acquiring task switching time of each task on other CPUs except the first CPU in the CPUs;

and acquiring the farthest time from the current time in the task switching time, and scheduling the target task indicated by the farthest time from the current time to other CPUs except the CPU where the target task is currently located to run.

2. The method according to claim 1, wherein the obtaining of the task switching time of each task on the remaining CPUs, except the first CPU, of the plurality of CPUs includes:

acquiring a process description structure corresponding to each task on the rest CPUs except the first CPU in the CPUs;

and acquiring switching time fields in the process description structure body corresponding to the tasks, and acquiring task switching time corresponding to the switching time fields.

3. The method of claim 1, wherein the scheduling the target task indicated by the farthest time from the current time to be executed on other CPUs other than the CPU where the target task is currently located comprises:

and when the farthest time from the current time is greater than or equal to a preset threshold value, scheduling the target task indicated by the farthest time from the current time to other CPUs except the CPU where the target task is currently located to run.

4. The method of claim 3, wherein the scheduling the target task indicated by the farthest time from the current time to be executed on other CPUs than the CPU where the target task is currently located comprises:

and scheduling the target task indicated by the farthest time from the current time to the first CPU for running, or scheduling the target task indicated by the farthest time from the current time to a second CPU for running, wherein the second CPU is a CPU of which the load is smaller than a load threshold value and the task switching time corresponding to the CPU is closest to the current time.

5. The method of claim 1, further comprising:

and when detecting that a task switching event occurs on at least one of the CPUs, updating the task switching time of each task on the CPUs.

6. The method of claim 5, wherein updating the task switch time for each task on the plurality of CPUs comprises:

when the switching state corresponding to the task switching event is determined to be an awakened state or a forced scheduling state, setting the task switching time of each task on the CPUs as the current time;

and when determining that the switching state corresponding to the task switching event is not in the awakened state or the forced scheduling state, setting the task switching time of each task on the CPUs to be zero.

7. The method of claim 6, further comprising:

and when the switching state corresponding to the task switching is determined to be the awakened state or the forced scheduling state, storing the task switching time according to the sequence of the task switching time.

8. A task scheduling apparatus, characterized in that the apparatus comprises:

the system comprises a time acquisition module, a load balancing module and a load balancing module, wherein the time acquisition module is used for acquiring task switching time of each task on other CPUs except a first CPU in a plurality of CPUs (central processing units) contained in the system when the first CPU enters an idle state to trigger load balancing;

and the task scheduling module is used for acquiring the farthest time from the current time in the task switching time and scheduling the target task indicated by the farthest time from the current time to other CPUs except the CPU where the target task is currently located to run.

9. A computer storage medium, characterized in that it stores a plurality of instructions adapted to be loaded by a processor and to carry out the method steps according to any one of claims 1 to 7.

10. An electronic device, comprising: a processor and a memory; wherein the memory stores a computer program adapted to be loaded by the processor and to perform the method steps of any of claims 1 to 7.

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