CN111629513B - Multi-layer circuit board structure with through hole and blind hole and its making method - Google Patents
Multi-layer circuit board structure with through hole and blind hole and its making method Download PDFInfo
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- 238000000034 method Methods 0.000 title claims description 16
- 229910000679 solder Inorganic materials 0.000 claims abstract description 116
- 238000004519 manufacturing process Methods 0.000 claims abstract description 10
- 230000000149 penetrating effect Effects 0.000 claims abstract description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 207
- 229910052802 copper Inorganic materials 0.000 claims description 207
- 239000010949 copper Substances 0.000 claims description 207
- 239000000758 substrate Substances 0.000 claims description 83
- 239000000853 adhesive Substances 0.000 claims description 52
- 230000001070 adhesive effect Effects 0.000 claims description 52
- 238000010030 laminating Methods 0.000 claims description 6
- 238000010147 laser engraving Methods 0.000 claims description 5
- 238000000576 coating method Methods 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000003384 imaging method Methods 0.000 claims 6
- 238000002161 passivation Methods 0.000 claims 3
- 230000002265 prevention Effects 0.000 claims 2
- 238000003466 welding Methods 0.000 claims 2
- 238000003475 lamination Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 279
- 238000001723 curing Methods 0.000 description 7
- 239000011241 protective layer Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 239000000615 nonconductor Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 2
- MOFOBJHOKRNACT-UHFFFAOYSA-N nickel silver Chemical compound [Ni].[Ag] MOFOBJHOKRNACT-UHFFFAOYSA-N 0.000 description 2
- 239000010956 nickel silver Substances 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 239000004743 Polypropylene Substances 0.000 description 1
- 229920000297 Rayon Polymers 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- CAYNKYSECUDBKJ-UHFFFAOYSA-N [Ag].[Ni].[Au] Chemical compound [Ag].[Ni].[Au] CAYNKYSECUDBKJ-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- -1 polypropylene Polymers 0.000 description 1
- 229920001155 polypropylene Polymers 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000001029 thermal curing Methods 0.000 description 1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/421—Blind plated via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
技术领域technical field
本发明是有关于一种电路板结构及其制法,特别是关于一种同时具有贯孔及盲孔的多层电路板结构及其制法。The present invention relates to a circuit board structure and its manufacturing method, in particular to a multi-layer circuit board structure with both through holes and blind holes and its manufacturing method.
背景技术Background technique
随着电子零件的小型化、高集积化,高功能电路的多层电路板(简称多层板)的需求日殷,又因表面贴装组件(SMD)的盛行,使得电路板线路图案的形状越趋复杂。尤有甚者,在现有多层电路板结构中,又有将SMD改为内嵌式设计而不凸出电路板表面的需求,更进一步推升电路板结构的设计难度及制程难度。如何克服前述问题,实是值得本领域人士思量的。With the miniaturization and high integration of electronic components, the demand for multi-layer circuit boards (referred to as multi-layer boards) of high-function circuits is increasing, and due to the prevalence of surface mount components (SMD), the circuit board pattern The shape becomes more and more complex. What's more, in the existing multi-layer circuit board structure, there is a need to change the SMD into an embedded design without protruding from the surface of the circuit board, which further increases the difficulty of designing and manufacturing the circuit board structure. How to overcome the foregoing problems is really worthy of consideration by those skilled in the art.
发明内容Contents of the invention
有鉴于此,本发明提出一种能实现内嵌表面贴装组件的多层电路板结构及其制法。In view of this, the present invention proposes a multi-layer circuit board structure capable of embedding surface mount components and a manufacturing method thereof.
为了达成上述及其他目的,本发明提供一种同时具有贯孔及盲孔的多层电路板结构,其包括一第一多层板、一第二多层板、一第二防焊层及一第四防焊层,第一多层板具有一第一基板、一图像化的第一铜层、一第二铜层及一黏着介质层,第一铜层形成于第一基板的一侧,第二铜层形成于第二基板的另侧,黏着介质层形成于第二铜层表面;第二多层板具有一第二基板、一图像化的第三铜层、一图像化的第四铜层及一第一防焊层,第三铜层形成于第二基板的一侧,第四铜层形成于第二基板的另侧,第一防焊层至少局部覆盖第三铜层,黏着介质层层合于第一防焊层表面;第二防焊层至少局部覆盖第一铜层,第三防焊层至少局部覆盖第四铜层;其中,多层电路板结构更包括至少一贯孔,其贯穿第一铜层、第一基板、第二铜层、黏着介质层、第一防焊层、第三铜层、第二基板及第四铜层,且贯孔的孔壁形成有孔铜,孔铜电性连接于第一、第二铜层至少其中一者与第三、第四铜层至少其中一者;其中,多层电路板结构更包括至少一盲孔,盲孔贯穿第二防焊层、第一铜层、第一基板、第二铜层及黏着介质层,盲孔裸露第一防焊层的一部份;其中,多层电路板结构更包括至少一雷射开窗,其形成于盲孔内裸露的第一防焊层,雷射开窗贯穿第一防焊层而使第三铜层的一部份裸露;其中,盲孔是供内嵌至少一表面贴装组件,雷射开窗则是供内嵌的表面贴装组件与第三铜层形成电性连接。In order to achieve the above and other objects, the present invention provides a multilayer circuit board structure having both through holes and blind holes, which includes a first multilayer board, a second multilayer board, a second solder resist layer and a The fourth solder resist layer, the first multilayer board has a first substrate, a patterned first copper layer, a second copper layer and an adhesive dielectric layer, the first copper layer is formed on one side of the first substrate, The second copper layer is formed on the other side of the second substrate, and the adhesive medium layer is formed on the surface of the second copper layer; the second multilayer board has a second substrate, an imaged third copper layer, and an imaged fourth copper layer. Copper layer and a first solder resist layer, the third copper layer is formed on one side of the second substrate, the fourth copper layer is formed on the other side of the second substrate, the first solder resist layer at least partially covers the third copper layer, and the adhesive The dielectric layer is laminated on the surface of the first solder resist layer; the second solder resist layer at least partially covers the first copper layer, and the third solder resist layer at least partially covers the fourth copper layer; wherein, the multilayer circuit board structure further includes at least one through hole , which runs through the first copper layer, the first substrate, the second copper layer, the adhesive dielectric layer, the first solder resist layer, the third copper layer, the second substrate and the fourth copper layer, and the hole wall of the through hole is formed with a hole Copper, the hole copper is electrically connected to at least one of the first and second copper layers and at least one of the third and fourth copper layers; wherein, the multilayer circuit board structure further includes at least one blind hole, and the blind hole runs through the first The second solder resist layer, the first copper layer, the first substrate, the second copper layer and the adhesive medium layer, and the blind hole exposes a part of the first solder resist layer; wherein, the multi-layer circuit board structure further includes at least one laser opening The window is formed in the exposed first solder resist layer in the blind hole, and the laser opening penetrates the first solder resist layer to expose a part of the third copper layer; wherein, the blind hole is for embedding at least one surface mount Mounting components, laser opening is for the embedded surface mount components to form an electrical connection with the third copper layer.
为了达成上述及其他目的,本发明还提供一种同时具有贯孔及盲孔的多层电路板结构,其包括一第一多层板、一第二多层板、一第二防焊层及一第三防焊层;第一多层板具有一第一基板、一图像化的第一铜层及一黏着介质层,第一铜层形成于第一基板的一侧,黏着介质层形成于第二基板的另侧;第二多层板具有一第二基板、一图像化的第三铜层、一图像化的第四铜层及一第一防焊层,第三铜层形成于第二基板的一侧,第四铜层形成于第二基板的另侧,第一防焊层至少局部覆盖第三铜层,黏着介质层层合于第一防焊层表面;第二防焊层至少局部覆盖第一铜层,第二防焊层至少局部覆盖第四铜层;其中,多层电路板结构更包括至少一贯孔,其贯穿第一铜层、第一基板、黏着介质层、第一防焊层、第三铜层、第二基板及第四铜层,且贯孔的孔壁形成有孔铜,孔铜电性连接于第一铜层与第三、第四铜层至少其中一者;其中,多层电路板结构更包括至少一盲孔,至少一盲孔贯穿第二防焊层、第一铜层、第一基板及黏着介质层,至少一盲孔裸露第一防焊层的一部份;多层电路板结构更包括至少一雷射开窗,其形成于盲孔内裸露的第一防焊层,且雷射开窗贯穿第一防焊层而使第三铜层的一部份裸露;其中,盲孔是供内嵌至少一表面贴装组件,雷射开窗则是供内嵌的表面贴装组件与第三铜层形成电性连接。In order to achieve the above and other objects, the present invention also provides a multilayer circuit board structure having both through holes and blind holes, which includes a first multilayer board, a second multilayer board, a second solder resist layer and A third solder resist layer; the first multilayer board has a first substrate, an imaged first copper layer and an adhesive dielectric layer, the first copper layer is formed on one side of the first substrate, and the adhesive dielectric layer is formed on The other side of the second substrate; the second multilayer board has a second substrate, an imaged third copper layer, an imaged fourth copper layer and a first solder resist layer, and the third copper layer is formed on the first layer On one side of the second substrate, the fourth copper layer is formed on the other side of the second substrate, the first solder resist layer at least partially covers the third copper layer, and the adhesive medium layer is laminated on the surface of the first solder resist layer; the second solder resist layer The first copper layer is at least partially covered, and the second solder resist layer is at least partially covered by the fourth copper layer; wherein, the multilayer circuit board structure further includes at least one through hole, which penetrates the first copper layer, the first substrate, the adhesive medium layer, the second A solder resist layer, a third copper layer, a second substrate, and a fourth copper layer, and hole copper is formed on the wall of the through hole, and the hole copper is electrically connected to at least one of the first copper layer and the third and fourth copper layers One; wherein, the multilayer circuit board structure further includes at least one blind hole, at least one blind hole penetrates the second solder resist layer, the first copper layer, the first substrate and the adhesive dielectric layer, and at least one blind hole exposes the first solder resist layer A part of the layer; the multilayer circuit board structure further includes at least one laser opening, which is formed in the exposed first solder resist layer in the blind hole, and the laser opening penetrates the first solder resist layer to make the third copper A part of the layer is exposed; wherein, the blind hole is for embedding at least one surface mount component, and the laser opening is for the embedded surface mount component to form an electrical connection with the third copper layer.
为了达成上述及其他目的,本发明还提供一种多层电路板结构的制法,其包括下列步骤:In order to achieve the above and other objects, the present invention also provides a method for making a multilayer circuit board structure, which includes the following steps:
(A)提供一第一多层板及一第二多层板:第一多层板具有一第一基板、一第一铜层及一第二铜层,第一铜层形成于第一基板的一侧,第二铜层形成于第二基板的另侧;第二多层板具有一第二基板、一第三铜层及一第四铜层,第三铜层形成于第二基板的一侧,第四铜层形成于第二基板的另侧;(A) Provide a first multilayer board and a second multilayer board: the first multilayer board has a first substrate, a first copper layer and a second copper layer, and the first copper layer is formed on the first substrate On one side of the second substrate, the second copper layer is formed on the other side of the second substrate; the second multilayer board has a second substrate, a third copper layer and a fourth copper layer, and the third copper layer is formed on the second substrate On one side, the fourth copper layer is formed on the other side of the second substrate;
(B)对第一、第二多层板进行预处理:在第二铜层表面形成一未完全固化的黏着介质层,并在第一多层板形成至少一贯穿第一铜层、第一基板、第二铜层及黏着介质层的盲孔前置孔;将第三铜层图像化,并在第三铜层表面形成一第一防焊层,并令第一防焊层完全固化;(B) Pre-treat the first and second multilayer boards: form an incompletely cured adhesive medium layer on the surface of the second copper layer, and form at least one through the first copper layer, the first multilayer board on the first multilayer board. The base plate, the second copper layer and the blind hole pre-hole of the adhesive medium layer; the third copper layer is imaged, and a first solder mask layer is formed on the surface of the third copper layer, and the first solder mask layer is completely cured;
(C)结合第一、第二多层板:将第一、第二多层板加以层合,使所述未完全固化的黏着介质层层合于第一防焊层表面,并令所述未完全固化的黏着介质层完全固化;(C) Combining the first and second multilayer boards: laminating the first and second multilayer boards, laminating the incompletely cured adhesive medium layer on the surface of the first solder resist layer, and making the The incompletely cured adhesive medium layer is completely cured;
(D)形成贯孔及图像化处理:形成至少一贯穿第一铜层、第一基板、第二铜层、黏着介质层、第一防焊层、第三铜层、第二基板及第四铜层的贯孔,并在至少一贯孔的孔壁形成孔铜,使孔铜电性连接于第一、第二铜层至少其中一者与第三、第四铜层至少其中一者,并将第一、第四铜层图像化;(D) Forming through holes and image processing: forming at least one through the first copper layer, the first substrate, the second copper layer, the adhesive dielectric layer, the first solder resist layer, the third copper layer, the second substrate and the fourth through holes in the copper layer, and form hole copper on the hole wall of at least one through hole, so that the hole copper is electrically connected to at least one of the first and second copper layers and at least one of the third and fourth copper layers, and Image the first and fourth copper layers;
(E)进一步形成防焊层:分别在第一、第四铜层覆盖一未完全固化的第二防焊层及一未完全固化的第三防焊层,且第二防焊层更填设于盲孔前置孔中;(E) Further forming the solder resist layer: respectively cover an incompletely cured second solder resist layer and an incompletely cured third solder resist layer on the first and fourth copper layers, and the second solder resist layer is further filled In the front hole of the blind hole;
(F)形成盲孔:将盲孔前置孔中的第二防焊层移除以形成至少一贯穿第二防焊层、第一铜层、第一基板、第二铜层及黏着介质层的盲孔;(F) Forming a blind hole: removing the second solder resist layer in the pre-hole of the blind hole to form at least one through the second solder resist layer, the first copper layer, the first substrate, the second copper layer and the adhesive medium layer blind hole;
(G)雷射开窗与防焊层固化:利用雷射雕刻机在盲孔内裸露的第一防焊层形成至少一雷射开窗,并令第二、第三防焊层完全固化,雷射开窗贯穿第一防焊层而使第三铜层的一部份裸露。(G) Laser window opening and solder mask curing: use a laser engraving machine to form at least one laser window on the exposed first solder mask layer in the blind hole, and completely cure the second and third solder mask layers, Laser opening penetrates through the first solder resist layer to expose a part of the third copper layer.
为了达成上述及其他目的,本发明还提供一种多层电路板结构的制法,其包括下列步骤:In order to achieve the above and other objects, the present invention also provides a method for making a multilayer circuit board structure, which includes the following steps:
(A)提供一第一多层板及一第二多层板:第一多层板具有一第一基板及一第一铜层,第一铜层形成于第一基板的一侧;第二多层板具有一第二基板、一第三铜层及一第四铜层,第三铜层形成于第二基板的一侧,第四铜层形成于第二基板的另侧;(A) providing a first multilayer board and a second multilayer board: the first multilayer board has a first substrate and a first copper layer, and the first copper layer is formed on one side of the first substrate; The multilayer board has a second substrate, a third copper layer and a fourth copper layer, the third copper layer is formed on one side of the second substrate, and the fourth copper layer is formed on the other side of the second substrate;
(B)对第一、第二多层板进行预处理:在第一基板相反于该第一铜层的一侧表面形成一未完全固化的黏着介质层,并在第一多层板形成至少一贯穿第一铜层、第一基板及黏着介质层的盲孔前置孔;将第三铜层图像化,并在第三铜层表面形成一第一防焊层,并令第一防焊层完全固化;(B) Pretreat the first and second multilayer boards: form an incompletely cured adhesive dielectric layer on the surface of the first substrate opposite to the first copper layer, and form at least A blind via hole through the first copper layer, the first substrate and the adhesive medium layer; image the third copper layer, and form a first solder resist layer on the surface of the third copper layer, and make the first solder resist The layer is fully cured;
(C)结合第一、第二多层板:将第一、第二多层板加以层合,使所述未完全固化的黏着介质层层合于第一防焊层表面,并令所述未完全固化的黏着介质层完全固化;(C) Combining the first and second multilayer boards: laminating the first and second multilayer boards, laminating the incompletely cured adhesive medium layer on the surface of the first solder resist layer, and making the The incompletely cured adhesive medium layer is completely cured;
(D)形成贯孔及图像化处理:形成至少一贯穿第一铜层、第一基板、黏着介质层、第一防焊层、第三铜层、第二基板及第四铜层的贯孔,并在至少一贯孔的孔壁形成孔铜,使孔铜电性连接于第一铜层与第三、第四铜层至少其中一者,并将第一、第四铜层图像化;(D) Forming through holes and image processing: forming at least one through hole penetrating through the first copper layer, the first substrate, the adhesive medium layer, the first solder resist layer, the third copper layer, the second substrate and the fourth copper layer , and forming hole copper on the hole wall of at least one through hole, so that the hole copper is electrically connected to at least one of the first copper layer and the third and fourth copper layers, and the first and fourth copper layers are imaged;
(E)进一步形成防焊层:分别在第一、第四铜层覆盖一未完全固化的第二防焊层及一未完全固化的第三防焊层,且第二防焊层更填设于盲孔前置孔中;(E) Further forming the solder resist layer: respectively cover an incompletely cured second solder resist layer and an incompletely cured third solder resist layer on the first and fourth copper layers, and the second solder resist layer is further filled In the front hole of the blind hole;
(F)形成盲孔:将盲孔前置孔中的第二防焊层移除以形成至少一贯穿第二防焊层、第一铜层、第一基板及黏着介质层的盲孔;(F) Forming a blind hole: removing the second solder resist layer in the pre-hole of the blind hole to form at least one blind hole penetrating through the second solder resist layer, the first copper layer, the first substrate and the adhesive medium layer;
(G)雷射开窗与防焊层固化:利用雷射雕刻机在盲孔内裸露的第一防焊层形成至少一雷射开窗,并令第二、第三防焊层完全固化,至少一雷射开窗贯穿第一防焊层而使第三铜层的一部份裸露。(G) Laser window opening and solder mask curing: use a laser engraving machine to form at least one laser window on the exposed first solder mask layer in the blind hole, and completely cure the second and third solder mask layers, At least one laser opening penetrates the first solder resist layer to expose a part of the third copper layer.
通过上述设计,本发明的多层电路板结构同时具有贯孔及盲孔,且盲孔能够支持表面贴装组件的内嵌式设置,从而满足产业界的需求。Through the above design, the multilayer circuit board structure of the present invention has both through holes and blind holes, and the blind holes can support the embedded arrangement of surface mount components, thereby meeting the needs of the industry.
有关本发明的其它功效及实施例的详细内容,配合附图说明如下。Details about other functions and embodiments of the present invention are described as follows with reference to the accompanying drawings.
附图说明Description of drawings
为了更清楚地说明本申请实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本申请中记载的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其它的附图。In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments described in this application. Those skilled in the art can also obtain other drawings based on these drawings without creative work.
图1是本发明多层电路板结构第一实施例的剖面示意图;Fig. 1 is the cross-sectional schematic diagram of the first embodiment of multilayer circuit board structure of the present invention;
图2为本发明多层电路板结构第一实施例贴装表面贴装组件及封装后的剖面示意图;2 is a schematic cross-sectional view of the first embodiment of the multilayer circuit board structure of the present invention after mounting surface mount components and packaging;
图3A至图3D为本发明多层电路板结构第一实施例的第一多层板预处理的制程示意图;3A to 3D are schematic diagrams of the first multilayer board pretreatment process of the first embodiment of the multilayer circuit board structure of the present invention;
图4A至图4C为本发明多层电路板结构第一实施例的第二多层板预处理的制程示意图;4A to 4C are schematic diagrams of the second multilayer board pretreatment process of the first embodiment of the multilayer circuit board structure of the present invention;
图5至图12图为本发明多层电路板结构第一实施例的制程示意图;5 to 12 are schematic diagrams of the manufacturing process of the first embodiment of the multilayer circuit board structure of the present invention;
图13为本发明多层电路板结构第二实施例的剖面示意图;13 is a schematic cross-sectional view of a second embodiment of the multilayer circuit board structure of the present invention;
图14为本发明多层电路板结构第三实施例的剖面示意图。FIG. 14 is a schematic cross-sectional view of a third embodiment of the multilayer circuit board structure of the present invention.
符号说明Symbol Description
10表面贴装组件 100多层电路板结构10
101、102开窗 110第一多层板101, 102
111第一基板 112第一铜层111
113第二铜层 114黏着介质层113
115保护层 116盲孔前置孔115
120第二多层板 121第二基板120
122第三铜层 123第四铜层122
124第一防焊层 130第二防焊层124 first
140第三防焊层 150贯孔140 third
151孔铜 152孔塞151
160盲孔 170雷射开窗160
180、181、182表面镀层 200多层电路板结构180, 181, 182
210第一多层板 211第一基板210
212第一铜层 214黏着介质层212
300多层电路板结构 314黏着介质层300 multi-layer
3141黏着层 3142介质层3141
3143黏胶3143 viscose
具体实施方式Detailed ways
有关本发明的前述及其它技术内容、特点与功效,在以下配合参考附图的一优选实施例的详细说明中,将可清楚的呈现。以下实施例中所提到的方向用语,例如:上、下、左、右、前或后等,仅是参考附图的方向。因此,使用的方向用语是用来说明并非用来限制本发明。The aforementioned and other technical content, features and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. The directional terms mentioned in the following embodiments, such as: up, down, left, right, front or back, etc., are only referring to the directions of the drawings. Accordingly, the directional terms used are for the purpose of illustration and not for the purpose of limiting the invention.
请参阅图1、图2,所绘示者为本发明多层电路板结构的第一实施例,该多层电路板结构100包括一第一多层板110、一第二多层板120、一第二防焊层130及一第三防焊层140。Please refer to Fig. 1 and Fig. 2, what is depicted is the first embodiment of the multilayer circuit board structure of the present invention, the multilayer
第一多层板110具有一第一基板111、一图像化的第一铜层112、一第二铜层113及一黏着介质层114。第一基板111为电绝缘体,例如介电质,在可能的实施方式中,第一基板111例如为FR-4基板。第一、第二铜层112、113分别形成于第一基板111的两相对侧,且第一、第二铜层112、113可具有图像化电路;在可能的实施方式中,第二铜层113也可能未被图形化。黏着介质层114例如是聚丙烯、黏胶等具有黏着能力的电绝缘体,在第一、第二多层板110、120彼此层合之前,黏着介质层114未完全固化,例如,前驱物未完全交联的聚丙烯,而在第一、第二多层板110、120层合后,黏着介质层114始被完全固化。The
第二多层板120具有一第二基板121、一图像化的第三铜层122、一图像化的第四铜层123及一第一防焊层124。第二基板121同样为电绝缘体,例如介电质,在可能的实施方式中,第二基板121例如为FR-4基板。第三、第四铜层122、123分别形成于第一基板121的两相对侧,且第三、第四铜层122、123具有图像化电路。第一、第二、第三防焊层124、130、140用于保护多层电路板结构100上的电路,能防止线路氧化,避免线路被后续制程污染或破坏。其中,第一防焊层124至少局部覆盖第三铜层122,保护第三铜层122的图像化电路;第二防焊层130至少局部覆盖第一铜层112,保护第一铜层112的图像化电路;第三防焊层140至少局部覆盖第四铜层123,保护第四铜层123的图像化电路。The
多层电路板结构100还包括至少一贯孔150(图1仅绘示一个作为例示),其由上至下依序贯穿第一铜层112、第一基板111、第二铜层113、黏着介质层114、第一防焊层124、第三铜层122、第二基板121及第四铜层123,贯孔150的孔壁形成有孔铜151,其电性连接于第一、第二铜层112、113至少其中一者与第三、第四铜层122、123至少其中一者,亦即,孔铜151可将不同层、不同多层板的电路加以电性连接。本实施例中,贯孔150没有被第二、第三防焊层130、140覆盖。在其他可能的实施方式中,贯孔也可能被第二、第三防焊层至少其中一者覆盖。The multilayer
另一方面,多层电路板结构100更包括至少一盲孔160(图1仅绘示一个作为例示),其由上而下依序贯穿第二防焊层130、第一铜层112、第一基板111、第二铜层113及黏着介质层114,使第一防焊层124的一部份裸露。亦即,盲孔160贯穿第一多层板110。On the other hand, the multilayer
此外,多层电路板结构100更包括至少一雷射开窗170(图1绘示两个作为例示),其形成于盲孔160内裸露的第一防焊层124,雷射开窗170贯穿第一防焊层124而使第三铜层122的一部份裸露。雷射开窗170例如是通过雷射雕刻机形成。本实施例中,盲孔160的孔壁没有形成孔铜,因此开设盲孔的主要目的不是为了让多个电路层连通(但在其他可能的实施方式中并不排除),而是供内嵌至少一表面贴装组件10(如图2),例如覆晶LED。内嵌表面贴装组件的顶面可以视需求低于、齐平或稍高于第二防焊层的顶面。为利于表面贴装组件的贴接,第三铜层122自雷射开窗裸露的表面还形成有一表面镀层180,其可为但不限于镍层、金层、银层、钯层其中一者或其层叠结构,例如电镀镍金层叠结构、电镀镍银金层叠结构、电镀镍银层叠结构、化学镍金层叠结构、化学镍银层叠结构或镍钯金层叠结构。In addition, the multilayer
以下搭配图式说明多层电路板结构制法的其中一种实施方式。One implementation of the manufacturing method of the multilayer circuit board structure is described below with the drawings.
首先,提供第一多层板110及一第二多层板120;如图3A所示,第一多层板110具有一第一基板111、一第一铜层112及一第二铜层113,第一、第二铜层112、113分别形成于第一基板111的两相对侧;另外,如图4A所示,第二多层板120具有一第二基板121、一第三铜层122及一第四铜层123,第三、第四铜层122、123分别形成于第二基板121的两相对侧;第一、第二多层板110、120可以选用双面预设有铜箔的双面板;First, a
接着,对第一、第二多层板110、120进行预处理;就第一多层板110而言,如图3B所示,在第二铜层113表面形成一未完全固化的黏着介质层114,并在第一铜层112表面形成一保护层115,先后顺序不限,必要时可在黏着介质层114形成之前,先对第二铜层113通过蚀刻制程进行图像化处理;接着如图3C所示,在第一多层板110形成至少一贯穿保护层115、第一铜层112、第一基板111、第二铜层112及黏着介质层114的盲孔前置孔116,之后如图3D所示,将保护层115移除,保护层115的设置目的是为了避免或至少大幅减少冲孔过程时第一铜层112产生毛边;就第二多层板120而言,如图4B所示,对第三铜层122进行图像化处理,接着如图4C所示,在第三铜层122表面形成一第一防焊层124,第一防焊层124也会一并覆盖因图像化处理而裸露的第二基板121表面。需说明的是,第一、第二多层板的预处理可以同时进行或先后进行,且先后顺序不限;Next, the first and second
接着,结合第一、第二多层板110、120;如图5所示,将第一、第二多层板110、120加以层合,使未完全固化的黏着介质层114层合于第一防焊层124表面,并令黏着介质层114完全固化,例如通过热固化使黏着介质层完全固化;Next, combine the first and second
再接着,形成贯孔及图像化处理:如图6所示,形成至少一贯穿第一铜层112、第一基板111、第二铜层113、黏着介质层114、第一防焊层124、第三铜层122、第二基板121及第四铜层123的贯孔150;接着,如图7所示,在多层电路板半成品表面利用化学镀方式镀上一铜层,而后如图8所示,通过蚀刻制程将不必要的铜去除,保留并形成贯孔150孔壁上的孔铜151,同时也对第一、第四铜层112、123图像化处理,形成所需的图像化电路;Then, forming through holes and image processing: as shown in FIG. The
接着,进一步形成防焊层:如图9所示,先在贯孔150内填入孔塞152,而后如图10所示,分别在第一、第四铜层112、123覆盖一未完全固化的第二防焊层130及一未完全固化的第三防焊层140,第二、第三防焊层130、140可为热固型、光固型或同时兼具热固型及光固型特性的防焊树酯材料制成,其中第二防焊层130还进一步填设于盲孔前置孔116中,之后将孔塞152移除;Next, further form the solder resist layer: as shown in Figure 9, first fill the
再接着,形成盲孔:如图11所示,通过微影成像及蚀刻制程将盲孔前置孔116中的第二防焊层130移除,形成贯穿第二防焊层130、第一铜层112、第一基板111、第二铜层113及黏着介质层114的盲孔160,同时也一并将需要裸露第一、第四铜层112、123的位置形成开窗101、102;Next, form blind holes: as shown in FIG. 11 , the second solder resist
然后,雷射开窗与防焊层固化:如图12所示,利用雷射雕刻机在盲孔160内裸露的第一防焊层124形成至少一雷射开窗170,雷射开窗170贯穿第一防焊层124而使第三铜层122的一部份裸露;并对第二、第三防焊层130、140进行热固化及/或光固化(视其特性),使两者完全固化;雷射开窗与防焊层固化的先后顺序不限,但在本实施例中,防焊层固化早于雷射开窗。Then, laser window opening and solder mask curing: as shown in FIG. A part of the
最后,必要时,在第三铜层122自雷射开窗170裸露的表面及开窗101、102处分别形成表面镀层180、181、182,即成为图1所示的多层电路板结构100。其后可再进行表面贴装组件的贴装及封装制程,成为如图2所示的多层电路板结构。Finally, if necessary,
在其他可能的实施方式中,第一多层板也可为单层板,例如图13所示的多层电路板结构200第二实施例中,第一多层板210没有第二铜层,因此黏着介质层214直接形成于第一基板211相对于第一铜层212的相反侧,其余结构与制程与第一实施例则无实质差异。In other possible implementations, the first multilayer board can also be a single layer board, for example, in the second embodiment of the multilayer
在其他可能的实施方式中,黏着介质层可由多层介质组成,例如在图14所示的多层电路板结构300第三实施例中,黏着介质层314包括一黏着层3141(Bonding Sheet)、介质层3142(例如聚酰亚胺,PI)及黏胶3143(Adhesive),但并不以此组合为限。In other possible implementations, the adhesive medium layer may be composed of multiple layers of medium. For example, in the third embodiment of the multilayer
以上所述的实施例及/或实施方式,仅是用以说明实现本发明技术的较佳实施例及/或实施方式,并非对本发明技术的实施方式作任何形式上的限制,任何本领域技术人员,在不脱离本发明内容所公开的技术手段的范围,当可作些许的更动或修改为其它等效的实施例,但仍应视为与本发明实质相同的技术或实施例。The embodiments and/or implementations described above are only used to illustrate the preferred embodiments and/or implementations of the technology of the present invention, and are not intended to limit the implementation of the technology of the present invention in any form. Personnel, without departing from the scope of the technical means disclosed in the content of the present invention, may make some changes or modifications to other equivalent embodiments, but it should still be regarded as the technology or embodiment substantially the same as the present invention.
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| JP2013236048A (en) * | 2012-05-03 | 2013-11-21 | Kyokutoku Kagi Kofun Yugenkoshi | Substrate structure manufacturing method |
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