CN111638994B - A kind of flash memory and its error bit count detection method and system - Google Patents
A kind of flash memory and its error bit count detection method and system Download PDFInfo
- Publication number
- CN111638994B CN111638994B CN202010484571.2A CN202010484571A CN111638994B CN 111638994 B CN111638994 B CN 111638994B CN 202010484571 A CN202010484571 A CN 202010484571A CN 111638994 B CN111638994 B CN 111638994B
- Authority
- CN
- China
- Prior art keywords
- block
- error bit
- module
- address
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Read Only Memory (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
本发明提供了一种闪存存储器及其错误比特计数检测方法和系统，ECC控制模块将需要进行错误比特计数的逻辑块的逻辑地址发送至块标志电路，块标志电路对逻辑块的逻辑地址进行译码，获得与逻辑块的逻辑地址对应的物理地址，并将物理地址的地址标记信号发送至对应的错误比特模块，错误比特模块根据块标志电路发送的地址标记信号以及页缓存器输出的错误标记信号，对具有验证错误的存储单元进行计数，即本发明中按照ECC控制模块的逻辑块进行错误比特计数，提高了错误比特计数检测的准确性。
The invention provides a flash memory and an error bit count detection method and system. The ECC control module sends the logical address of the logic block that needs to be counted in error bits to the block mark circuit, and the block mark circuit interprets the logical address of the logic block. code, obtain the physical address corresponding to the logical address of the logical block, and send the address mark signal of the physical address to the corresponding error bit module. The error bit module is based on the address mark signal sent by the block mark circuit and the error mark output by the page buffer. The signal is used to count the memory cells with verification errors, that is, in the present invention, the error bit count is performed according to the logic block of the ECC control module, which improves the accuracy of the error bit count detection.
Description
Technical Field
The present invention relates to the field of semiconductor memory technology, and more particularly, to a flash memory and a method and system for detecting an error bit count thereof.
Background
Flash memories (Flash memories) have been widely used in various fields such as micro-electromechanical systems, automation control, etc. because they have the advantages of long-term retention of stored information without power-up, high integration, fast access speed, and easy erasing and rewriting. In order to further increase the bit density of flash memories while reducing the bit cost, three-dimensional flash memories (3D NAND) have been rapidly developed.
The conventional three-dimensional flash memory uses ISPP (Incremental Step Pulse Programming) to perform program and erase operations, and after the erase or program operation, a verification operation is performed to check whether the memory location is normal. After verification, the error bits that fail verification are counted to determine whether the location passes verification, and whether the next programming operation continues programming the memory cell is determined according to the verification result. However, the conventional error bit judgment method has the problem of inaccurate error bit judgment.
Disclosure of Invention
In view of the above, the present invention provides a flash memory and a method and a system for detecting an erroneous bit count thereof, so as to improve the accuracy of the erroneous bit count detection.
In order to achieve the purpose, the invention provides the following technical scheme:
an error bit count detection system of a flash memory comprises an ECC control module, a block buffer, a block marking circuit and an error bit module;
each block buffer comprises a plurality of page buffers, each page buffer is connected with the memory control module, and the page buffers are used for storing the programming verification data of the corresponding page memory units and obtaining error marking signals for marking the page memory units with verification errors according to the programming verification data;
the ECC control module is used for sending a logic address of a logic block which needs to be subjected to error bit counting to the block marking circuit;
the block marking circuit is used for decoding the logic address of the logic block, obtaining a physical address corresponding to the logic address of the logic block and sending an address marking signal of the physical address to an error bit module which is arranged corresponding to a storage unit with the physical address;
the error bit module is used for counting the memory units with verification errors according to the address marking signals sent by the block marking circuit and the error marking signals output by the page buffer, and judging whether the programming verification is successful according to the counting result.
Optionally, the error bit module comprises an error bit counting module and an analog error bit counting and accumulating module;
the error bit counting module is connected with the page buffer and the block marking circuit, and is used for outputting an intermediate level signal according to the address marking signal sent by the block marking circuit and the error marking signal output by the page buffer and sending the intermediate level signal to the analog error bit counting and accumulating module;
and the analog error bit counting and accumulating module is used for counting the storage units with verification errors according to the intermediate level signal and judging whether the programming verification is successful according to the counting result.
Optionally, the error bit counting module is further connected to a flag latch;
the flag latch is used for storing an address replacement flag signal which indicates whether the page memory cell is replaced by a page memory cell in the redundant cell array;
the error bit counting module is further configured to output an intermediate level signal according to the address flag signal sent by the block flag circuit, the error flag signal output by the page buffer, and the address replacement flag signal output by the flag latch.
Optionally, the error bit counting module includes a nor gate, a first switch tube, a second switch tube and the flag latch;
a first input end of the NOR gate is connected with the block flag circuit, a second input end of the NOR gate is connected with the page buffer, a third input end of the NOR gate is connected with the mark latch, and an output end of the NOR gate is connected with a grid electrode of the first switch tube;
the first end of the first switch tube is grounded, the second end of the first switch tube is connected with the first end of the second switch tube, the second end of the second switch tube is connected with the output end of the error bit counting module, and the grid electrode of the second switch tube is connected with the analog output control signal line of the analog error bit counting and accumulating module;
when the block marking circuit outputs a low-level address marking signal as a low-level signal, the marking latch outputs a low-level address replacement marking signal and the page buffer outputs a low-level error marking signal, the nor gate inputs a high-level signal to the gate of the first switch tube, so that the first switch tube is conducted;
when the analog output control signal line inputs a control signal to the grid electrode of the second switch tube, the second switch tube is conducted, the output end of the error bit counting module outputs a middle level signal, and the middle level signal is sent to the analog error bit counting and accumulating module, so that the analog error bit counting and accumulating module compares the middle level signal with a reference level signal to complete counting.
Optionally, the memory cell array of the flash memory includes a main cell array and a redundant cell array;
the block buffers comprise a first block buffer and a second block buffer, a page buffer in the first block buffer is connected with a bit line of each page storage unit in the main cell array, and a page buffer in the second block buffer is connected with a bit line of each page storage unit in the redundant cell array;
the error bit counting module comprises a first error bit counting module and a second error bit counting module, the first error bit counting module is connected with the page buffer in the first block buffer, and the second error bit counting module is connected with the page buffer in the second block buffer;
the block flag circuit comprises a first block flag circuit and a second block flag circuit, the first block flag circuit is connected with the first error bit counting module, and the second block flag circuit is connected with the second error bit counting module.
A method for detecting an erroneous bit count of a flash memory includes:
the ECC control module sends a logic address of a logic block which needs to be subjected to error bit counting to a block marking circuit;
the block marking circuit decodes the logic address of the logic block to obtain a physical address corresponding to the logic address of the logic block, and sends an address marking signal of the physical address to an error bit module which is arranged corresponding to a storage unit with the physical address;
the error bit module is used for generating an error bit according to the address mark signal sent by the block marking circuit and the error mark signal output by the page buffer,
and counting the memory cells with verification errors, and judging whether the programming verification is successful according to the counting result.
Optionally, the step of the error bit module counting the memory cells with verification errors according to the address flag signal sent by the block flag circuit and the error flag signal output by the page buffer, and determining whether the program verification is successful according to the counting result includes:
the error bit counting module outputs an intermediate level signal according to the address mark signal sent by the block marking circuit and the error mark signal output by the page buffer, and sends the intermediate level signal to the analog error bit counting and accumulating module;
and the analog error bit counting and accumulating module counts the memory cells with verification errors according to the intermediate level signal and judges whether the programming verification is successful according to the counting result.
Optionally, the outputting, by the error bit counting module, the intermediate level signal according to the address flag signal sent by the block flag circuit and the error flag signal output by the page buffer includes:
the error bit counting module outputs an intermediate level signal according to the address mark signal sent by the block marking circuit, the error mark signal output by the page buffer and the address replacement mark signal output by the mark latch.
Optionally, when the error bit counting module includes a nor gate, a first switch tube, a second switch tube and the flag latch, the outputting, by the error bit counting module, an intermediate level signal according to the address flag signal sent by the block flag circuit, the error flag signal output by the page buffer, and the address replacement flag signal output by the flag latch includes:
the block marking circuit outputs a low-level address marking signal, the marking latch outputs a low-level address replacement marking signal and the page buffer outputs a low-level error marking signal, and the NOR gate inputs a high-level signal to the grid electrode of the first switch tube to enable the first switch tube to be conducted;
the analog output control signal line inputs a control signal to a grid electrode of the second switch tube, the second switch tube is conducted, and an output end of the error bit counting module outputs a middle level signal.
A flash memory comprising an error bit count detection system of a flash memory as described in any one of the above.
Compared with the prior art, the technical scheme provided by the invention has the following advantages:
the invention provides a flash memory and a method and a system for detecting error bit count thereof, an ECC control module sends a logic address of a logic block which needs to be subjected to error bit count to a block marking circuit, the block marking circuit decodes the logic address of the logic block to obtain a physical address corresponding to the logic address of the logic block and sends an address marking signal of the physical address to an error bit module which is arranged corresponding to a storage unit with the physical address, the error bit module counts the storage unit with verification error according to the address marking signal sent by the block marking circuit and an error marking signal output by a page buffer and judges whether programming verification is successful according to a counting result, namely, the invention carries out error bit count according to the logic block of the ECC control module, thereby improving the accuracy of the erroneous bit count detection.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a schematic diagram of a conventional flash memory;
FIG. 2 is a schematic diagram of an embodiment of a system for detecting an erroneous bit count of a flash memory according to the present invention;
FIG. 3 is a schematic diagram of an embodiment of an error bit count detection system of a flash memory according to the present invention;
fig. 4 is a schematic structural diagram of an error bit counting module according to an embodiment of the present invention;
fig. 5 is a flowchart of a method for detecting an erroneous bit count of a flash memory according to an embodiment of the present invention.
Detailed Description
As described in the background, the existing error bit count detection method has a problem of inaccurate error bit count detection.
The conventional flash memory includes a main cell array 11, a redundant cell array 12, an error bit detection module 13, a memory control module 14, and an ECC control module 15. The main cell array 11 and the redundant cell array 12 each include a plurality of memory strings each including a plurality of memory cells, and the memory string in the redundant cell array 12 is used to replace the memory string of the erroneous bit in the main cell array 11. Wherein one or more of the memory cells constitute a page, the plurality of pages constitute a memory block, the memory block is an erasable cell, and the page is a readable and programmable cell.
The error bit detection module 13 is configured to count verification result data in the memory block and count error bits after the memory block is subjected to an erase or program verification operation.
Also, the existing NAND uses an ECC (Error Correcting Code) control module 15 to encode and correct data, and the ECC control module 15 may correct some Error bits, that is, allow some correctable Error bits to exist according to the correction standard of the ECC control module 15. Generally, the comparison unit of ECC is 2KB or 4KB, and for a NAND with a capacity of 16KB, the technology of error bit grouping for every 2KB of logical storage units in the verification operation required by ECC is more in accordance with the standard of ECC. However, the actual physical address distribution of the NAND16KB data is not as concentrated as the logical addresses. It is possible that a centralized physical region has data belonging to the first 2KB, the second 2KB, the third 2KB, the fourth 2KB, etc. When counting is then performed, the operations are all performed in blocks because of layout constraints. Therefore, the counting cannot be performed according to the address of the ECC, which is not accurate.
Based on this, the invention provides a flash memory and a method and a system for detecting the error bit count thereof, so as to overcome the problems in the prior art, wherein the system for detecting the error bit count of the flash memory comprises an ECC control module, a block buffer, a block marking circuit and an error bit module;
each block buffer comprises a plurality of page buffers, each page buffer is connected with the memory control module, and the page buffers are used for storing the programming verification data of the corresponding page memory units and obtaining error marking signals for marking the page memory units with verification errors according to the programming verification data;
the ECC control module is used for sending a logic address of a logic block which needs to be subjected to error bit counting to the block marking circuit;
the block marking circuit is used for decoding the logic address of the logic block, obtaining a physical address corresponding to the logic address of the logic block and sending an address marking signal of the physical address to an error bit module which is arranged corresponding to a storage unit with the physical address;
the error bit module is used for counting the memory units with verification errors according to the address marking signals sent by the block marking circuit and the error marking signals output by the page buffer, and judging whether the programming verification is successful according to the counting result.
The invention provides a flash memory and a method and a system for detecting error bit count thereof, an ECC control module sends a logic address of a logic block which needs to be subjected to error bit count to a block marking circuit, the block marking circuit decodes the logic address of the logic block to obtain a physical address corresponding to the logic address of the logic block and sends an address marking signal of the physical address to an error bit module which is arranged corresponding to a storage unit with the physical address, the error bit module counts the storage unit with verification error according to the address marking signal sent by the block marking circuit and an error marking signal output by a page buffer and judges whether programming verification is successful according to a counting result, namely, the invention carries out error bit count according to the logic block of the ECC control module, thereby improving the accuracy of the erroneous bit count detection.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, so that the above is the core idea of the present invention, and the above objects, features and advantages of the present invention can be more clearly understood. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
An embodiment of the present invention provides an error bit count detection system for a flash memory, where the flash memory may be a NAND flash memory such as a Single Level Cell (SLC), a multi-level cell (MLC), a three-level cell (TLC), a four-level cell (QLC), and as shown in fig. 2, the flash memory includes a cell array, and the error bit count detection system includes an ECC control module 21, a memory control module 22, a block buffer 23, an error bit module, and a block flag circuit 25.
The block buffer 23 is arranged corresponding to a physical block of the flash memory. Specifically, the memory cell array includes a main cell array 201 and a redundant cell array 202, and as shown in fig. 3, the block buffer 23 includes a first block buffer 231 and a second block buffer 232, the first block buffer 231 is disposed corresponding to a physical memory block in the main cell array 201, and the second block buffer 232 is disposed corresponding to a physical memory block in the redundant cell array 202.
Each block buffer 23 includes a plurality of page buffers. The first block buffer 231 includes a plurality of page buffers 2310 and the second block buffer 232 includes a plurality of page buffers 2320. A plurality of page buffers are respectively connected to bit lines of respective memory cells on the same word line, and specifically, the page buffer 2310 in the first block buffer 231 is connected to the bit line of each memory cell in the main cell array 201, and the page buffer 2320 in the second block buffer 232 is connected to the bit line of each memory cell in the redundant cell array 202.
Each block buffer 23 is connected to the memory control module 22, and is configured to store program verification data of a corresponding page of memory cells, and obtain an error flag signal for identifying that a verification error exists in the page of memory cells according to the program verification data. Specifically, the memory control module 22 may also write and read data to and from the corresponding memory cells through the block buffer 23 so as to program the data, thereby obtaining program verification data.
The ECC control module 21 is configured to encode and error-correct data input by the flash memory, decode and error-correct data output by the flash memory, and send a logical address of a logical block that needs to be subjected to error bit counting to the block flag circuit according to an address bit requirement of the ECC.
The block flag circuit 25 is configured to decode a logical address of the logical block, obtain a physical address corresponding to the logical address of the logical block, and send an address flag signal of the physical address to an error bit module set corresponding to a memory cell having the physical address.
The error bit module is used for counting the memory units with verification errors according to the address mark signals sent by the block marking circuit and the error mark signals output by the page buffer, and judging whether the programming verification is successful according to the counting result.
Specifically, the error bit module includes an error bit count module 24, an analog error bit count and accumulation module 26. The error bit counting module 24 is connected to the page buffer 230 and the block flag circuit 25, and is configured to output an intermediate level signal according to the address flag signal sent by the block flag circuit 25 and the error flag signal output by the page buffer 230, and send the intermediate level signal to the analog error bit counting and accumulating module 26;
the analog error bit counting and accumulating module 26 is used for counting the memory cells with verification errors according to the intermediate level signal and judging whether the programming verification is successful according to the counting result.
In one embodiment of the present invention, the block flag circuit includes a first block flag circuit 251 and a second block flag circuit 252, the first block flag circuit 251 being coupled to the first error bit count module 241, the second block flag circuit 252 being coupled to the second error bit count module 242.
Since the corresponding relationship between the physical address and the logical address of the main cell array 201 is known, after the first block flag circuit 251 obtains the logical address of each logical block, the physical address of each storage unit in the main cell array 201 can be obtained according to the corresponding relationship between the physical address and the logical address, that is, the physical block where the corresponding storage unit of each logical block is located is obtained, and then the first block flag circuit 251 sends the address flag signal of the physical address to the first error bit counting module 241 corresponding to the storage unit with the physical address.
However, since it is not known which location of the memory string in the main cell array 201 is replaced by the memory string in the redundant cell array 202 after the memory string in the redundant cell array 202 replaces the memory string in the main cell array 201, in the embodiment of the present invention, the block flag circuit includes a first block flag circuit 251 and a plurality of second block flag circuits 252, the first block flag circuit 251 is connected to all of the first error bit count modules 241, each of the second block flag circuits 252 is connected to one of the second error bit count modules 242, and the second block flag circuit 252 uses the redundant CAM address to determine which block the page memory cell adjacent thereto belongs to.
Each error bit counting module 24 is connected to the page buffer 230 and the block flag circuit 25, and specifically, the error bit counting module 24 includes a first error bit counting module 241 and a second error bit counting module 242, the first error bit counting module 241 is connected to the page buffer in the first block buffer 231, and the second error bit counting module 242 is connected to the page buffer in the second block buffer 232.
It should be noted that the present invention is not limited to this, and in other embodiments, the present invention may only include the first block buffer 231, the first block flag circuit 251, and the first error bit counting module 241, that is, in the embodiment of the present invention, the error bit counting may only be performed on the main array unit 201.
Because of the small pitch of the bit lines, in the embodiment of the present invention, as shown in fig. 3, a plurality of page buffers 230 are sequentially arranged in a plurality of columns, and each block buffer 23 is sequentially arranged in a plurality of rows, so that the page buffers can be reasonably arranged within the pitch of the bit lines. Of course, the invention is not limited to this, and in other embodiments, the page buffers may be arranged according to actual situations.
In the embodiment of the present invention, the error bit counting module 24 is further connected to the flag latch;
the flag latch is used to store an address replacement flag signal indicating whether a page memory cell is replaced by a page memory cell in the redundant cell array 202;
the error bit counting block 24 is further configured to output an intermediate level signal according to the address flag signal sent by the block flag circuit 25, the error flag signal output by the page buffer, and the address replacement flag signal output by the flag latch.
As shown in fig. 4, the error bit count module includes a nor gate 2410, a first switch tube 2411, a second switch tube 2412, and a flag latch. Of course, the present invention is described by taking the circuit structure as an example, but the present invention is not limited thereto.
A first input terminal of the nor gate 2410 is connected to the block flag circuit 25, e.g., the first block flag circuit or the second block flag circuit, a second input terminal of the nor gate 2410 is connected to the page buffer, e.g., 230 or 232, a third input terminal of the nor gate 2410 is connected to the tag latch, and an output terminal of the nor gate 2410 is connected to the gate of the first switch 2411;
a first end of the first switch tube 2411 is grounded, a second end of the first switch tube 2411 is connected with a first end of the second switch tube 2412, a second end of the second switch tube 2412 is connected with an output end of the error bit counting module 24, and a grid electrode of the second switch tube 2412 is connected with an analog output control signal line of the analog error bit counting and accumulating module 26;
when the block flag circuit 25 outputs the low-level address flag signal chunk _ sig, the flag latch outputs the low-level address replacement flag signal, and the page buffer outputs the low-level error flag signal ver _ sig, the nor gate 2410 inputs the high-level signal to the gate of the first switch tube 2411, so that the first switch tube 2411 is turned on;
when the analog output control signal line ver _ iref _ sig inputs a control signal to the gate of the second switch tube 2412, the second switch tube 2412 is turned on, the output end of the error bit counting module 24 outputs an intermediate level signal, and the intermediate level signal is sent to the analog error bit counting and accumulating module 26, so that the analog error bit counting and accumulating module 26 compares the intermediate level signal with the reference level signal to complete counting.
Specifically, when the block flag circuit 25 sends an address flag to the error bit count module 24 indicating that the block of data is not within the address of the required ECC count, the address flag signal sent by the block flag circuit 25 is high. The output of the nor gate 2410 is low no matter what the level of the other input terminals of the error bit counting module 24 is; the memory verify error bits for this region will not be counted.
When the block flag circuit 25 sends an address flag signal to the error bit count module 24 indicating that the block of data is within the address of the required ECC count, the address flag signal sent by the block flag circuit 25 is low. The output of the NOR gate 2410 is determined by the page register and the tag latch output. The output of the NOR gate 2410 is determined by the page buffer when the flag latch output of the page buffer is low. When the page buffer indicates that the cell is verified to be erroneous, the page buffer outputs a low level, and the input end of the error bit counting module 24 connected thereto is a low level; the memory verify error bits for this region are counted. When the page buffer indicates that the unit is correctly verified, the page buffer outputs a high level, and the input end connected with the error bit counting module 24 is a low level; the memory verify error bits for this region are counted. When the three input terminals of the nor gate input a low level, the nor gate 2410 inputs a high level to the gate of the first switch tube 2411, so that the first switch tube 2411 is turned on, indicating that there is an error data.
When the analog output control signal line ver _ iref _ sig inputs a control signal to the gate of the second switch tube 2412, the second switch tube 2412 is turned on, the output end of the error bit counting module 24 outputs an intermediate level signal, and the intermediate level signal is sent to the analog error bit counting and accumulating module 26, so that the analog error bit counting and accumulating module 26 compares the intermediate level signal with the reference level signal to complete counting.
The invention provides an error bit counting detection system of a flash memory, wherein an ECC control module sends a logic address of a logic block needing error bit counting to a block marking circuit according to the address bit requirement of the ECC, the block marking circuit decodes the logic address of the logic block to obtain a physical address corresponding to the logic address of the logic block and sends an address marking signal of the physical address to an error bit counting module correspondingly arranged with a storage unit with the physical address, the error bit counting module outputs a middle level signal according to the address marking signal sent by the block marking circuit and an error marking signal output by a page buffer and sends the middle level signal to a simulation error bit counting and accumulating module; the analog error bit counting and accumulating module is used for counting the storage units with verification errors according to the intermediate level signal and judging whether the programming verification is successful or not according to the counting result, namely, the error bit counting is carried out according to the logic block of the ECC control module, so that the accuracy of error bit counting detection is improved.
Embodiments of the present invention further provide a flash memory, which includes a memory cell array and the error bit count detection system provided in any of the above embodiments.
An embodiment of the present invention further provides a method for detecting an error bit count of a flash memory, which is applied to the error bit count detection system provided in any of the above embodiments, and as shown in fig. 5, the method includes:
s101: the ECC control module sends a logic address of a logic block which needs to be subjected to error bit counting to a block marking circuit;
s102: the block marking circuit decodes the logic address of the logic block, obtains a physical address corresponding to the logic address of the logic block, and sends an address marking signal of the physical address to an error bit module which is arranged corresponding to a storage unit with the physical address;
s103: the error bit module counts the memory cells with verification errors according to the address mark signals sent by the block marking circuit and the error mark signals output by the page buffer, and judges whether the programming verification is successful according to the counting result.
Wherein, the error bit module counts the memory cells with verification errors according to the address mark signal sent by the block marking circuit and the error mark signal output by the page buffer, and judges whether the program verification is successful according to the counting result comprises:
the error bit counting module outputs an intermediate level signal according to the address mark signal sent by the block marking circuit and the error mark signal output by the page buffer, and sends the intermediate level signal to the analog error bit counting and accumulating module;
and the analog error bit counting and accumulating module counts the memory cells with verification errors according to the intermediate level signal and judges whether the programming verification is successful according to the counting result.
Optionally, the outputting, by the error bit counting module, the intermediate level signal according to the address flag signal sent by the block flag circuit and the error flag signal output by the page buffer includes:
the error bit counting module outputs an intermediate level signal according to the address mark signal sent by the block marking circuit, the error mark signal output by the page buffer and the address replacement mark signal output by the mark latch.
When the error bit counting module comprises a nor gate, a first switch tube, a second switch tube and a mark latch, the error bit counting module outputs an intermediate level signal according to an address mark signal sent by the block marking circuit, an error mark signal output by the page buffer and an address replacement mark signal output by the mark latch, and comprises:
the block marking circuit outputs a low-level address marking signal, the marking latch outputs a low-level address replacement marking signal and the page buffer outputs a low-level error marking signal, and the NOR gate inputs a high-level signal to the grid electrode of the first switch tube to enable the first switch tube to be conducted;
the analog output control signal line inputs a control signal to a grid electrode of the second switch tube, the second switch tube is conducted, and the output end of the error bit counting module outputs a middle level signal.
Specifically, as shown in fig. 4, when the block flag circuit 25 sends an address flag to the error bit count module 24 indicating that the block data is not within the address of the required ECC count, the address flag signal sent by the block flag circuit 25 is high. The output of the nor gate 2410 is low no matter what the level of the other input terminals of the error bit counting module 24 is; the memory verify error bits for this region will not be counted.
When the block flag circuit 25 sends an address flag signal to the error bit count module 24 indicating that the block of data is within the address of the required ECC count, the address flag signal sent by the block flag circuit 25 is low. The output of the NOR gate 2410 is determined by the page register and the tag latch output. The output of the NOR gate 2410 is determined by the page buffer when the flag latch output of the page buffer is low. When the page buffer indicates that the cell is verified to be erroneous, the page buffer outputs a low level, and the input end of the error bit counting module 24 connected thereto is a low level; the memory verify error bits for this region are counted. When the page buffer indicates that the unit is correctly verified, the page buffer outputs a high level, and the input end connected with the error bit counting module 24 is a low level; the memory verify error bits for this region are counted. When the three input terminals of the nor gate input a low level, the nor gate 2410 inputs a high level to the gate of the first switch tube 2411, so that the first switch tube 2411 is turned on, indicating that there is an error data.
When the analog output control signal line ver _ iref _ sig inputs a control signal to the gate of the second switch tube 2412, the second switch tube 2412 is turned on, the output end of the error bit counting module 24 outputs an intermediate level signal, and the intermediate level signal is sent to the analog error bit counting and accumulating module 26, so that the analog error bit counting and accumulating module 26 compares the intermediate level signal with the reference level signal to complete counting.
The error bit counting detection method of the flash memory provided by the invention counts the error bits according to the logic block of the ECC control module, thereby improving the accuracy of error bit counting detection.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. The error bit count detection system of a flash memory is characterized by comprising an ECC control module, a block buffer, a block marking circuit and an error bit module;
each block buffer comprises a plurality of page buffers, each page buffer is connected with the memory control module, and the page buffers are used for storing the programming verification data of the corresponding page memory units and obtaining error marking signals for marking that the page memory units have verification errors according to the programming verification data;
the ECC control module is used for sending a logic address of a logic block which needs to be subjected to error bit counting to the block marking circuit;
the block marking circuit is used for decoding the logic address of the logic block, obtaining a physical address corresponding to the logic address of the logic block and sending an address marking signal of the physical address to an error bit module which is arranged corresponding to a storage unit with the physical address;
the error bit module is used for counting the memory units with verification errors according to the address marking signals sent by the block marking circuit and the error marking signals output by the page buffer, and judging whether the programming verification is successful according to the counting result.
2. The system of claim 1, wherein the error bit module comprises an error bit count module and an analog error bit count and accumulation module;
the error bit counting module is connected with the page buffer and the block marking circuit, and is used for outputting an intermediate level signal according to the address marking signal sent by the block marking circuit and the error marking signal output by the page buffer and sending the intermediate level signal to the analog error bit counting and accumulating module;
and the analog error bit counting and accumulating module is used for counting the storage units with verification errors according to the intermediate level signal and judging whether the programming verification is successful according to the counting result.
3. The system of claim 2, wherein the error bit count module is further coupled to a flag latch;
the flag latch is used for storing an address replacement flag signal which indicates whether the page memory cell is replaced by a page memory cell in the redundant cell array;
the error bit counting module is further configured to output an intermediate level signal according to the address flag signal sent by the block flag circuit, the error flag signal output by the page buffer, and the address replacement flag signal output by the flag latch.
4. The system of claim 3, wherein the error bit count module comprises a NOR gate, a first switch tube, a second switch tube, and the flag latch;
a first input end of the NOR gate is connected with the block flag circuit, a second input end of the NOR gate is connected with the page buffer, a third input end of the NOR gate is connected with the mark latch, and an output end of the NOR gate is connected with a grid electrode of the first switch tube;
the first end of the first switch tube is grounded, the second end of the first switch tube is connected with the first end of the second switch tube, the second end of the second switch tube is connected with the output end of the error bit counting module, and the grid electrode of the second switch tube is connected with the analog output control signal line of the analog error bit counting and accumulating module;
when the block marking circuit outputs a low-level address marking signal as a low-level signal, the marking latch outputs a low-level address replacement marking signal and the page buffer outputs a low-level error marking signal, the nor gate inputs a high-level signal to the gate of the first switch tube, so that the first switch tube is conducted;
when the analog output control signal line inputs a control signal to the grid electrode of the second switch tube, the second switch tube is conducted, the output end of the error bit counting module outputs a middle level signal, and the middle level signal is sent to the analog error bit counting and accumulating module, so that the analog error bit counting and accumulating module compares the middle level signal with a reference level signal to complete counting.
5. The system of claim 1, wherein the memory cell array of the flash memory comprises a main cell array and a redundant cell array;
the block buffers comprise a first block buffer and a second block buffer, a page buffer in the first block buffer is connected with a bit line of each page storage unit in the main cell array, and a page buffer in the second block buffer is connected with a bit line of each page storage unit in the redundant cell array;
the error bit counting module comprises a first error bit counting module and a second error bit counting module, the first error bit counting module is connected with the page buffer in the first block buffer, and the second error bit counting module is connected with the page buffer in the second block buffer;
the block flag circuit comprises a first block flag circuit and a second block flag circuit, the first block flag circuit is connected with the first error bit counting module, and the second block flag circuit is connected with the second error bit counting module.
6. A method for detecting an erroneous bit count of a flash memory, comprising:
the ECC control module sends a logic address of a logic block which needs to be subjected to error bit counting to a block marking circuit;
the block marking circuit decodes the logic address of the logic block to obtain a physical address corresponding to the logic address of the logic block, and sends an address marking signal of the physical address to an error bit module which is arranged corresponding to a storage unit with the physical address;
the error bit module is used for generating an error bit according to the address mark signal sent by the block marking circuit and the error mark signal output by the page buffer,
and counting the memory cells with verification errors, and judging whether the programming verification is successful according to the counting result.
7. The method of claim 6, wherein the error bit module counts the memory cells having verification errors according to the address flag signal sent by the block flag circuit and the error flag signal output by the page buffer, and determining whether the program verification is successful according to the counting result comprises:
the error bit counting module outputs an intermediate level signal according to the address mark signal sent by the block marking circuit and the error mark signal output by the page buffer, and sends the intermediate level signal to the analog error bit counting and accumulating module;
and the analog error bit counting and accumulating module counts the memory cells with verification errors according to the intermediate level signal and judges whether the programming verification is successful according to the counting result.
8. The method of claim 7, wherein outputting an intermediate level signal by the error bit counting module according to the address flag signal sent by the block flag circuit and the error flag signal output by the page buffer comprises:
the error bit counting module outputs an intermediate level signal according to the address mark signal sent by the block marking circuit, the error mark signal output by the page buffer and the address replacement mark signal output by the mark latch.
9. The method of claim 8, wherein when the error bit counting module comprises a nor gate, a first switch tube, a second switch tube and the flag latch, the error bit counting module outputs an intermediate level signal according to the address flag signal transmitted from the block flag circuit, the error flag signal output from the page buffer and the address replacement flag signal output from the flag latch comprises:
the block marking circuit outputs a low-level address marking signal, the marking latch outputs a low-level address replacement marking signal and the page buffer outputs a low-level error marking signal, and the NOR gate inputs a high-level signal to the grid electrode of the first switch tube to enable the first switch tube to be conducted;
and the analog output control signal line of the analog error bit counting and accumulating module inputs a control signal to the grid electrode of the second switch tube, the second switch tube is conducted, and the output end of the error bit counting module outputs an intermediate level signal.
10. A flash memory comprising the error bit count detection system of any one of claims 1 to 5.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110366221.0A CN113051100B (en) | 2020-06-01 | 2020-06-01 | A flash memory and its error bit counting detection system |
| CN202010484571.2A CN111638994B (en) | 2020-06-01 | 2020-06-01 | A kind of flash memory and its error bit count detection method and system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010484571.2A CN111638994B (en) | 2020-06-01 | 2020-06-01 | A kind of flash memory and its error bit count detection method and system |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110366221.0A Division CN113051100B (en) | 2020-06-01 | 2020-06-01 | A flash memory and its error bit counting detection system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111638994A CN111638994A (en) | 2020-09-08 |
| CN111638994B true CN111638994B (en) | 2021-05-04 |
Family
ID=72330357
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010484571.2A Active CN111638994B (en) | 2020-06-01 | 2020-06-01 | A kind of flash memory and its error bit count detection method and system |
| CN202110366221.0A Active CN113051100B (en) | 2020-06-01 | 2020-06-01 | A flash memory and its error bit counting detection system |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110366221.0A Active CN113051100B (en) | 2020-06-01 | 2020-06-01 | A flash memory and its error bit counting detection system |
Country Status (1)
| Country | Link |
|---|---|
| CN (2) | CN111638994B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111638994B (en) * | 2020-06-01 | 2021-05-04 | 长江存储科技有限责任公司 | A kind of flash memory and its error bit count detection method and system |
| CN112331255B (en) * | 2020-10-21 | 2022-01-25 | 长江存储科技有限责任公司 | Verification statistical circuit and method of 3D NAND memory and 3D NAND memory |
| CN114566203B (en) * | 2022-02-21 | 2023-05-05 | 华中科技大学 | Flash rapid detection device and method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101876947A (en) * | 2009-04-30 | 2010-11-03 | 国际商业机器公司 | Method and system for storing data |
| CN102543204A (en) * | 2010-12-30 | 2012-07-04 | 海力士半导体有限公司 | Memory system and method of operating the same |
| CN110209522A (en) * | 2018-02-28 | 2019-09-06 | 英特尔公司 | Technology for the mistake detected and in correction data |
| CN110570892A (en) * | 2019-07-31 | 2019-12-13 | 联芸科技（杭州）有限公司 | method and device for controlling refreshing of memory and controller |
| CN110874282A (en) * | 2018-08-31 | 2020-03-10 | 群联电子股份有限公司 | Data access method, memory control circuit unit, and memory storage device |
Family Cites Families (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6701480B1 (en) * | 2000-03-08 | 2004-03-02 | Rockwell Automation Technologies, Inc. | System and method for providing error check and correction in memory systems |
| JP4237109B2 (en) * | 2004-06-18 | 2009-03-11 | エルピーダメモリ株式会社 | Semiconductor memory device and refresh cycle control method |
| KR100732628B1 (en) * | 2005-07-28 | 2007-06-27 | 삼성전자주식회사 | Flash memory device for storing multi-bit data and single-bit data |
| KR101015655B1 (en) * | 2009-05-29 | 2011-02-22 | 주식회사 하이닉스반도체 | Driving Method of Nonvolatile Memory Device |
| JP2013542533A (en) * | 2010-10-27 | 2013-11-21 | エルエスアイ コーポレーション | Adaptive ECC technology for flash memory based data storage |
| US8990667B2 (en) * | 2012-08-03 | 2015-03-24 | Samsung Electronics Co., Ltd. | Error check and correction circuit, method, and memory device |
| US20140115422A1 (en) * | 2012-10-24 | 2014-04-24 | Laurence H. Cooke | Non-volatile memory error correction |
| JP2014086062A (en) * | 2012-10-29 | 2014-05-12 | Sony Corp | Storage control device, storage, information processing system and storage control method |
| US9342401B2 (en) * | 2013-09-16 | 2016-05-17 | Sandisk Technologies Inc. | Selective in-situ retouching of data in nonvolatile memory |
| US9740558B2 (en) * | 2015-05-31 | 2017-08-22 | Intel Corporation | On-die ECC with error counter and internal address generation |
| CN105097049B (en) * | 2015-08-03 | 2017-11-10 | 西安紫光国芯半导体有限公司 | Statistical system in a kind of impairment unit piece for multipage storage array |
| TWI587304B (en) * | 2016-03-09 | 2017-06-11 | 群聯電子股份有限公司 | Memory managing method, memory control circuit unit and mempry storage apparatus |
| TWI599880B (en) * | 2016-03-22 | 2017-09-21 | 威盛電子股份有限公司 | Non-volatile memory apparatus and operating method thereof |
| US9904594B2 (en) * | 2016-04-15 | 2018-02-27 | Micron Technology, Inc. | Monitoring error correction operations performed in memory |
| US10558525B2 (en) * | 2016-06-30 | 2020-02-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of correcting errors in a memory array and a system for implementing the same |
| KR102716265B1 (en) * | 2016-12-20 | 2024-10-14 | 에스케이하이닉스 주식회사 | Memory controller, memory system including the same, and operating method thereof |
| KR20180094170A (en) * | 2017-02-13 | 2018-08-23 | 에스케이하이닉스 주식회사 | Memory device, memory controller, and operation method thereof for generating identifier |
| US10276259B2 (en) * | 2017-07-05 | 2019-04-30 | Winbond Electronics Corp. | Memory testing method and memory apparatus therefor |
| CN107562655B (en) * | 2017-08-31 | 2019-01-25 | 长江存储科技有限责任公司 | A kind of date storage method and device |
| JP6985915B2 (en) * | 2017-12-15 | 2021-12-22 | 日本放送協会 | Decoding error detection and estimation device, video decoding device, and their programs |
| CN111638994B (en) * | 2020-06-01 | 2021-05-04 | 长江存储科技有限责任公司 | A kind of flash memory and its error bit count detection method and system |
-
2020
- 2020-06-01 CN CN202010484571.2A patent/CN111638994B/en active Active
- 2020-06-01 CN CN202110366221.0A patent/CN113051100B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101876947A (en) * | 2009-04-30 | 2010-11-03 | 国际商业机器公司 | Method and system for storing data |
| CN102543204A (en) * | 2010-12-30 | 2012-07-04 | 海力士半导体有限公司 | Memory system and method of operating the same |
| CN110209522A (en) * | 2018-02-28 | 2019-09-06 | 英特尔公司 | Technology for the mistake detected and in correction data |
| CN110874282A (en) * | 2018-08-31 | 2020-03-10 | 群联电子股份有限公司 | Data access method, memory control circuit unit, and memory storage device |
| CN110570892A (en) * | 2019-07-31 | 2019-12-13 | 联芸科技（杭州）有限公司 | method and device for controlling refreshing of memory and controller |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113051100B (en) | 2024-05-17 |
| CN111638994A (en) | 2020-09-08 |
| CN113051100A (en) | 2021-06-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8286055B2 (en) | Nonvolatile memory device and method of operating the same | |
| US9047972B2 (en) | Methods, devices, and systems for data sensing | |
| CN101447227B (en) | Flash memory device and programming method thereof | |
| TWI474330B (en) | Method for performing memory access management, and associated memory device and controller thereof | |
| US8599613B2 (en) | Nonvolatile semiconductor memory | |
| US8898374B2 (en) | Flash memory device and method for managing flash memory device | |
| CN111638994B (en) | A kind of flash memory and its error bit count detection method and system | |
| US20200303016A1 (en) | Memory reading method and memory system | |
| CN101763904A (en) | Nonvolatile memory device and method of operating the same | |
| US8578245B2 (en) | Data reading method, memory storage apparatus, and controller thereof | |
| US9093154B2 (en) | Method, memory controller and system for reading data stored in flash memory | |
| CN103544073A (en) | Method for reading data of block in flash memory and related memory device | |
| CN104217761B (en) | Data storage device and error correction method thereof | |
| CN102543196B (en) | Data reading method, memory storage device and controller thereof | |
| CN104094237A (en) | Enhanced error correction in memory devices | |
| CN102693758A (en) | Data reading method, memory storage device and memory controller thereof | |
| KR20130102397A (en) | Flash memory and reading method of flash memory | |
| CN106158031B (en) | Semiconductor memory and data writing method | |
| CN102750188B (en) | Method for memory access management, storage device and controller thereof | |
| CN106297879B (en) | Memory device and method of operating the same | |
| CN117632579B (en) | Memory control method and memory storage device | |
| CN114724596A (en) | Reading voltage setting method, memory storage device, and memory controller |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |