CN111650988A - a voltage regulator - Google Patents

Abstract

The invention discloses a voltage stabilizer, which belongs to the field of electronics. The voltage stabilizer of the invention includes a bias circuit, a voltage stabilizer circuit and an output circuit; the voltage stabilizer can start to work and realize the voltage stabilization function when the power supply voltage exceeds the preset stable voltage of the chip; when the internal main power supply is normal When working, the voltage stabilizer can assist the output current of the main power supply. When the on-chip main power supply is abnormal, the voltage stabilizer provides a stable voltage to keep the data inside the chip from being lost. The voltage regulator can provide a continuous and stable voltage for some circuits when the main power supply inside the chip is not turned on, so as to avoid the situation that the chip loses power due to the internal main power supply abnormally or data is lost before startup.

Description

a voltage regulator

technical field

The invention relates to the field of electronics, in particular to a sub-microamp level voltage stabilizer.

Background technique

At present, most power management chips usually use a low dropout regulator (LDO) for voltage regulation. The traditional low dropout linear regulator is shown in Figure 1. Generally, the output terminal VOUT is fed back through a voltage divider resistor. The closed-loop control is completed at the input end of the back amplifier, and this LDO usually needs to consume a relatively large power consumption (for example: more than 5uA). However, in some application scenarios that require low power consumption (for example: electronic equipment is in a standby state), although the LDO does not need to work continuously, in order to prevent some modules from losing data due to power failure, an ultra-low power voltage regulator is still required. The module is continuously powered. Existing low dropout linear regulators cannot meet the needs of the above scenarios.

SUMMARY OF THE INVENTION

In view of the above problems, a voltage regulator is provided, which is designed to provide a continuous and stable voltage for some circuits under the condition of power consumption and when the main power supply inside the chip is not turned on.

The present invention provides a voltage stabilizer, comprising:

a bias circuit, including two first output terminals and a second output terminal, for converting the input voltage into a first bias voltage signal and a second bias voltage signal;

a voltage regulator circuit, comprising a first input end, a second input end and a third output end, the first input end is connected to the first output end, the second input end is connected to the second output end, the The voltage regulator circuit is configured to output a first voltage signal according to the input voltage, the first bias voltage signal and the second bias voltage signal;

an output circuit, comprising a third input terminal, a fourth input terminal and a fourth output terminal, the third input terminal is connected to the third output terminal, the fourth input terminal is connected to the second output terminal, and the output terminal The circuit is configured to generate a second voltage signal according to the input voltage, the first voltage signal and the second bias voltage signal, and output the second voltage signal.

Preferably, the bias circuit further includes:

a first PMOS tube, the source of the first PMOS tube is connected to the power supply terminal, and the gate of the first PMOS tube is connected to the drain of the first PMOS tube;

A second PMOS transistor, the source of the second PMOS transistor is connected to the source of the first PMOS transistor and the power supply terminal, and the gate of the second PMOS transistor is connected to the gate of the first PMOS transistor and the drain of the first PMOS transistor;

A first NMOS transistor, the drain of the first NMOS transistor is connected with the gate of the first PMOS transistor, the drain of the first PMOS transistor and the gate of the second PMOS transistor to form the bias set the first output terminal of the circuit;

The second NMOS transistor, the source of the second NMOS transistor is grounded, the gate of the second NMOS transistor and the drain of the second NMOS transistor, the gate of the first NMOS transistor and the second PMOS transistor The drains are connected together to form the second output terminal of the bias circuit;

A first resistor, one end of the first resistor is connected to the source of the first NMOS transistor, and the other end of the first resistor is connected to the source of the second NMOS transistor to ground.

Preferably, the voltage regulator circuit further includes:

a third PMOS tube, the gate of the third PMOS tube forms the first input end of the voltage regulator circuit, and the source electrode of the third PMOS tube is connected to the power supply terminal;

a third NMOS transistor, the drain of the third PMOS transistor is connected to the drain of the third PMOS transistor, and the source of the third PMOS transistor is grounded;

a fourth NMOS tube, the gate of the fourth NMOS tube forms the second input end of the voltage regulator circuit, and the source of the fourth NMOS tube is grounded;

a sixth NMOS transistor, the gate of the sixth NMOS transistor is connected to the drain of the third PMOS transistor and the drain of the third NMOS transistor, and the drain of the sixth NMOS transistor is connected to the third NMOS transistor The source connection of the PMOS tube;

A second resistor, one end of the second resistor is connected to the gate of the third NMOS transistor and the drain of the fourth NMOS transistor, and the other end of the second resistor is connected to the source of the sixth NMOS transistor The third output terminals are connected together to form the voltage stabilizing circuit.

Preferably, the output circuit further includes:

a fifth NMOS transistor, the gate of the fifth NMOS transistor forms the fourth input end of the output circuit, and the source of the fifth NMOS transistor is grounded;

A seventh NMOS transistor, the gate of the seventh NMOS transistor forms the third input terminal of the output circuit, the drain electrode of the seventh NMOS transistor is connected to the power supply terminal, and the source electrode of the seventh NMOS transistor is connected to the power supply terminal. The drain connection of the fifth NMOS transistor together forms a fourth output terminal of the output circuit.

The beneficial effects of the above technical solutions:

In this technical solution, the voltage stabilizer of the present invention includes a bias circuit, a voltage stabilizer circuit and an output circuit; the voltage stabilizer can start to work and realize the voltage stabilization function when the power supply voltage exceeds the preset stable voltage of the chip; When the internal main power supply is working normally, the regulator can assist the main power supply to output current. When the on-chip main power supply is abnormal, the regulator provides a stable voltage to keep the internal data of the chip from being lost. The voltage regulator can provide a continuous and stable voltage for some circuits when the main power supply inside the chip is not turned on, so as to avoid the situation that the chip loses power due to the internal main power supply abnormally or data is lost before startup.

Description of drawings

Fig. 1 is the circuit diagram of the existing low dropout linear regulator;

FIG. 2 is a circuit diagram of an embodiment of the bias circuit according to the present invention;

3 is a circuit diagram of an embodiment of the voltage regulator circuit of the present invention;

FIG. 4 is a circuit diagram of an embodiment of the voltage stabilizer according to the invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present invention.

It should be noted that the embodiments of the present invention and the features of the embodiments may be combined with each other under the condition of no conflict.

The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but it is not intended to limit the present invention.

As shown in FIG. 2 to FIG. 4 , the present invention provides a voltage stabilizer, comprising: a bias circuit 1, a voltage stabilizer circuit 2 and an output circuit 3; wherein,

A bias circuit 1, comprising two first output terminals VB1 and second output terminals VB2, for converting an input voltage into a first bias voltage signal and a second bias voltage signal;

Further, as shown in FIG. 2 and FIG. 4 , the bias circuit 1 may further include: a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, a second NMOS transistor MN2, and a first resistor R1;

a first PMOS transistor MP1, the source of the first PMOS transistor MP1 is connected to the power supply terminal VCC, and the gate of the first PMOS transistor MP1 is connected to the drain of the first PMOS transistor MP1;

The second PMOS transistor MP2, the source of the second PMOS transistor MP2 is connected to the source of the first PMOS transistor MP1 and the power supply terminal VCC, and the gate of the second PMOS transistor MP2 is connected to the first PMOS transistor MP2. The gate of the PMOS transistor MP1 and the drain of the first PMOS transistor MP1;

The first NMOS transistor MN1, the drain of the first NMOS transistor MN1 is connected to the gate of the first PMOS transistor MP1, the drain of the first PMOS transistor MP1 and the gate of the second PMOS transistor MP2 jointly form the first output terminal VB1 of the bias circuit 1;

The second NMOS transistor MN2, the source of the second NMOS transistor MN2 is grounded, the gate of the second NMOS transistor MN2 is connected to the drain of the second NMOS transistor MN2, and the gate of the first NMOS transistor MN1 is connected with the drain of the second PMOS transistor MP2 to form the second output terminal VB2 of the bias circuit 1;

A first resistor R1, one end of the first resistor R1 is connected to the source of the first NMOS transistor MN1, and the other end of the first resistor R1 is connected to the ground of the source of the second NMOS transistor MN2.

The voltage regulator circuit 2 includes a first input terminal, a second input terminal and a third output terminal VB3, the first input terminal is connected to the first output terminal VB1, and the second input terminal is connected to the second output terminal VB2, the voltage regulator circuit 2 is configured to output a first voltage signal according to the input voltage, the first bias voltage signal and the second bias voltage signal;

Further, as shown in FIG. 3 and FIG. 4 , the voltage regulator circuit 2 may further include: a third PMOS transistor MP3, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a sixth NMOS transistor MN6, and a second resistor RM;

The third PMOS transistor MP3, the gate of the third PMOS transistor MP3 forms the first input terminal of the voltage regulator circuit 2, and the source of the third PMOS transistor MP3 is connected to the power supply terminal VCC;

the third NMOS transistor MN3, the drain of the third PMOS transistor MP3 is connected to the drain of the third PMOS transistor MP3, and the source of the third PMOS transistor MP3 is grounded;

the fourth NMOS transistor MN4, the gate of the fourth NMOS transistor MN4 forms the second input terminal of the voltage regulator circuit 2, and the source of the fourth NMOS transistor MN4 is grounded;

A sixth NMOS transistor MN6, the gate of the sixth NMOS transistor MN6 is connected to the drain of the third PMOS transistor MP3 and the drain of the third NMOS transistor MN3, and the drain of the sixth NMOS transistor MN6 connected with the source of the third PMOS transistor MP3;

A second resistor RM, one end of the second resistor RM is connected to the gate of the third NMOS transistor MN3 and the drain of the fourth NMOS transistor MN4, and the other end of the second resistor RM is connected to the sixth NMOS transistor MN4. The source connection of the NMOS transistor MN6 together forms the third output terminal VB3 of the voltage regulator circuit 2 .

Wherein, the second resistor RM is a trimming resistor.

The output circuit 3 includes a third input terminal, a fourth input terminal and a fourth output terminal, the third input terminal is connected to the third output terminal VB3, the fourth input terminal is connected to the second output terminal VB2, The output circuit 3 is configured to generate a second voltage signal according to the input voltage, the first voltage signal and the second bias voltage signal, and output the second voltage signal.

Further, as shown in FIG. 3 and FIG. 4 , the output circuit 3 may further include: a fifth NMOS transistor MN5 and a seventh NMOS transistor MN7;

the fifth NMOS transistor MN5, the gate of the fifth NMOS transistor MN5 forms the fourth input terminal of the output circuit 3, and the source of the fifth NMOS transistor MN5 is grounded;

The seventh NMOS transistor MN7, the gate of the seventh NMOS transistor MN7 forms the third input terminal of the output circuit 3, the drain of the seventh NMOS transistor MN7 is connected to the power supply terminal VCC, and the seventh NMOS transistor MN7 The source of MN7 is connected with the drain of the fifth NMOS transistor MN5 to form a fourth output terminal of the output circuit 3 .

In the bias circuit 1, the current flowing through the first PMOS transistor MP1 is defined by the ratio of the gate-source voltage difference between the second NMOS transistor MN2 and the first NMOS transistor MN1 to the first resistor R1, and the first PMOS transistor MP1 passes the current The current value is mirrored to the third PMOS transistor MP3 in a mirror manner. As shown in FIG. 3, the gate static operating point of the sixth NMOS transistor MN6 is determined by the current flowing through the third PMOS transistor MP3, and the gate static operating point of the third NMOS transistor MN3 is determined by the current flowing through the fourth NMOS transistor MN4. At the same time, the third NMOS transistor MN3 and the sixth NMOS transistor MN6 form negative feedback. When the drain voltage of the third PMOS transistor MP3 rises, the gate-source voltage difference of the sixth NMOS transistor MN6 increases, so that the third NMOS transistor The gate voltage of the transistor MN3 is reduced, thereby pulling down the drain voltage of the third PMOS transistor MP3, so as to achieve the purpose of quickly stabilizing the operating point. Since the fourth NMOS transistor MN4 mirrors the drain current of the second NMOS transistor MN2 by means of a current mirror, adjusting the second resistor RM can effectively adjust the third NMOS transistor MN4 when the aspect ratio of the fourth NMOS transistor MN4 remains unchanged. The gates of the NMOS transistor MN3 and the sixth NMOS transistor MN6 are static operating points. As shown in Figure 4, there are: VOUT=V _G7 -V _GS7 , so the voltage regulation function can be realized under a small load current.

In this embodiment, the DC bias is generated by the first PMOS transistor MP1, the second PMOS transistor MP2, the first NMOS transistor MN1, the second NMOS transistor MN2, and the first resistor R1, and the first PMOS transistor RM is changed to stabilize the The static operating points of the three NMOS transistors MN3, the sixth NMOS transistor MN6, and the seventh NMOS transistor MN7, so as to realize the stability of the output voltage. The third PMOS transistor MP3, the sixth NMOS transistor MN6, and the third NMOS transistor MN3 form a negative feedback structure, which can quickly stabilize the operating point when the power supply voltage is abruptly changed. The circuit has the advantages of novel structure, adjustable output voltage, no need for capacitor compensation, small chip area occupation and cost saving.

In this embodiment, the voltage stabilizer can start to work and realize the voltage stabilization function when the power supply voltage exceeds the preset stable voltage of the chip; when the internal main power supply works normally, the voltage stabilizer can assist the main power supply Output current. When the on-chip main power supply is abnormal, the voltage stabilizer provides a stable voltage to maintain the internal data of the chip without loss. The voltage regulator can provide a continuous and stable voltage for some circuits when the main power supply inside the chip is not turned on, so as to avoid the situation that the chip loses power due to the internal main power supply abnormally or data is lost before startup. The voltage stabilizer of the invention has the advantages of novel structure, adjustable output voltage, no need for capacitance compensation, small occupied chip area, cost saving and the like.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the embodiments and protection scope of the present invention. For those skilled in the art, they should be able to realize that all equivalents made by using the description and illustrations of the present invention The solutions obtained by substitutions and obvious changes shall all be included in the protection scope of the present invention.

Claims (4)

1. a voltage stabilizer, is characterized in that, comprises: a bias circuit, including two first output terminals and a second output terminal, for converting the input voltage into a first bias voltage signal and a second bias voltage signal; a voltage regulator circuit, comprising a first input end, a second input end and a third output end, the first input end is connected to the first output end, the second input end is connected to the second output end, the The voltage regulator circuit is configured to output a first voltage signal according to the input voltage, the first bias voltage signal and the second bias voltage signal; an output circuit, comprising a third input terminal, a fourth input terminal and a fourth output terminal, the third input terminal is connected to the third output terminal, the fourth input terminal is connected to the second output terminal, and the output terminal The circuit is configured to generate a second voltage signal according to the input voltage, the first voltage signal and the second bias voltage signal, and output the second voltage signal. 2. The voltage regulator of claim 1, wherein the bias circuit further comprises: a first PMOS tube, the source of the first PMOS tube is connected to the power supply terminal, and the gate of the first PMOS tube is connected to the drain of the first PMOS tube; A second PMOS transistor, the source of the second PMOS transistor is connected to the source of the first PMOS transistor and the power supply terminal, and the gate of the second PMOS transistor is connected to the gate of the first PMOS transistor and the drain of the first PMOS transistor; A first NMOS transistor, the drain of the first NMOS transistor is connected with the gate of the first PMOS transistor, the drain of the first PMOS transistor and the gate of the second PMOS transistor to form the bias set the first output terminal of the circuit; The second NMOS transistor, the source of the second NMOS transistor is grounded, the gate of the second NMOS transistor and the drain of the second NMOS transistor, the gate of the first NMOS transistor and the second PMOS transistor The drains are connected together to form the second output terminal of the bias circuit; A first resistor, one end of the first resistor is connected to the source of the first NMOS transistor, and the other end of the first resistor is connected to the source of the second NMOS transistor to ground. 3. The voltage stabilizer according to claim 1, wherein the voltage stabilizer circuit further comprises: a third PMOS tube, the gate of the third PMOS tube forms the first input end of the voltage regulator circuit, and the source electrode of the third PMOS tube is connected to the power supply terminal; a third NMOS transistor, the drain of the third PMOS transistor is connected to the drain of the third PMOS transistor, and the source of the third PMOS transistor is grounded; a fourth NMOS tube, the gate of the fourth NMOS tube forms the second input end of the voltage regulator circuit, and the source of the fourth NMOS tube is grounded; a sixth NMOS transistor, the gate of the sixth NMOS transistor is connected to the drain of the third PMOS transistor and the drain of the third NMOS transistor, and the drain of the sixth NMOS transistor is connected to the third NMOS transistor The source connection of the PMOS tube; A second resistor, one end of the second resistor is connected to the gate of the third NMOS transistor and the drain of the fourth NMOS transistor, and the other end of the second resistor is connected to the source of the sixth NMOS transistor The third output terminals are connected together to form the voltage stabilizing circuit. 4. The voltage regulator according to claim 1, wherein the output circuit further comprises: a fifth NMOS transistor, the gate of the fifth NMOS transistor forms the fourth input end of the output circuit, and the source of the fifth NMOS transistor is grounded; A seventh NMOS transistor, the gate of the seventh NMOS transistor forms the third input terminal of the output circuit, the drain electrode of the seventh NMOS transistor is connected to the power supply terminal, and the source electrode of the seventh NMOS transistor is connected to the power supply terminal. The drain connection of the fifth NMOS transistor together forms a fourth output terminal of the output circuit.

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