CN111696462B - Output buffers and methods of operation - Google Patents

Abstract

An output buffer and method of operation thereof. The output buffer includes an input stage circuit, an output stage circuit, a rising control circuit and a falling control circuit. The input stage circuit correspondingly generates a first gate control voltage and a second gate control voltage according to the input voltage of the output buffer. The output stage circuit generates the output voltage of the output buffer correspondingly according to the first gating voltage and the second gating voltage. When the output voltage is to be pulled up, the rising control circuit pulls down the first gating voltage and the second gating voltage during the first transient period. When the output voltage is to be pulled down, the drop control circuit pulls up the first gating voltage and the second gating voltage during the second transient period.

Description

Output buffer and its method of operation

technical field

The present invention relates to an electronic circuit, and more particularly to an output buffer and its operating method.

Background technique

In general, a source driver is configured with an output buffer. In the source driver, the output buffer can gain the analog voltage of the digital-to-analog converter and output it to the data line (or source line) of the display panel. As the resolution and/or frame rate of the display panel becomes higher and higher, the charging time for one scan line becomes shorter and shorter. In order to drive (charge or discharge) a pixel in a short time, the output buffer needs a sufficiently high driving capability. That is, the output buffer needs a sufficiently high slew rate. In order to increase the slew rate, the known tail current of the output buffer is increased. An increase in tail current means an increase in power consumption.

Contents of the invention

The invention provides an output buffer and its operation method to increase the slew rate of the output voltage.

An embodiment of the invention provides an output buffer. The output buffer includes an input stage circuit, an output stage circuit, a rising control circuit and a falling control circuit. The input stage circuit is configured to receive an input voltage of the output buffer. The input stage circuit correspondingly generates a first gate control voltage and a second gate control voltage according to the input voltage. The output stage circuit is coupled to the input stage circuit to receive the first gating control voltage and the second gating control voltage. The output stage circuit is configured to correspondingly generate the output voltage of the output buffer according to the first gating voltage and the second gating voltage. The rising control circuit is configured to compare the input voltage and the output voltage to obtain a first comparison result. When the first comparison result indicates that the output voltage is to be pulled up, the rising control circuit pulls down the first gating voltage and the second gating voltage during the first transient period. The falling control circuit is configured to compare the input voltage and the output voltage to obtain a second comparison result. When the second comparison result indicates that the output voltage is about to be pulled down, the drop control circuit pulls up the first gating voltage and the second gating voltage during the second transient period.

An embodiment of the invention provides an operation method of an output buffer. The operation method includes: correspondingly generating a first gating voltage and a second gating voltage by the input stage circuit according to the input voltage of the output buffer; generating an output voltage of the output buffer by the output stage circuit correspondingly according to the first gating voltage and the second gating voltage; comparing the input voltage and the output voltage by the rising control circuit to obtain a first comparison result; when the first comparison result indicates that the output voltage is to be pulled up, the rising control circuit pulls down the first gating voltage and the second gating voltage during the first transient period; the falling control circuit compares the input voltage and the output voltage to obtain the second comparison result; And when the second comparison result indicates that the output voltage is to be pulled down, the drop control circuit pulls up the first gating voltage and the second gating voltage during the second transient period.

Based on the above, the output buffer and the operation method thereof according to the embodiments of the present invention can compare the input voltage and the output voltage. When the output voltage is going to be pulled up, both the first gating voltage and the second gating voltage of the output stage circuit of the output buffer are pulled down to increase the slew rate of the output voltage. When the output voltage is to be pulled down, both the first gating voltage and the second gating voltage of the output stage circuit of the output buffer are pulled up to increase the slew rate of the output voltage.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

FIG. 1 is a schematic diagram of a circuit block of an output buffer according to an embodiment of the present invention.

FIG. 2 is a schematic flowchart of an operation method of an output buffer according to an embodiment of the present invention.

FIG. 3 is a circuit block diagram illustrating the rising control circuit shown in FIG. 1 according to an embodiment of the present invention.

FIG. 4 is a circuit block diagram illustrating the rising control circuit shown in FIG. 1 according to another embodiment of the present invention.

FIG. 5 is a circuit block diagram illustrating the drop control circuit shown in FIG. 1 according to an embodiment of the present invention.

FIG. 6 is a circuit block diagram illustrating the droop control circuit shown in FIG. 1 according to another embodiment of the present invention.

[Description of Reference Signs]

100: output buffer

110: Input stage circuit

120: Output stage circuit

130: Rising control circuit

131: Comparison circuit

140: Down control circuit

141: Comparison circuit

310, 510: current mirror

EN, ENB: control signal

N1～N12, P1～P12: Transistor

NGATE, PGATE: Gating voltage

S210～S270: steps

VC1, VC2: control voltage

VDDA: system voltage

VIN: input voltage

VOUT: output voltage

VSSA: reference voltage

Detailed ways

As used throughout this specification (including the claims), the term "coupled (or connected)" may refer to any direct or indirect means of connection. For example, if it is described that a first device is coupled (or connected) to a second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be indirectly connected to the second device through other devices or some connection means. In addition, wherever possible, elements/components/steps using the same reference numerals in the drawings and the embodiments represent the same or similar parts. Elements/components/steps using the same reference numerals or using the same terms in different embodiments can refer to related descriptions.

FIG. 1 is a schematic diagram of a circuit block of an output buffer 100 according to an embodiment of the present invention. The first input terminal of the output buffer 100 receives the input voltage VIN from the previous circuit (not shown), and the output terminal of the output buffer 100 outputs the output voltage VOUT to the subsequent circuit (not shown). In the embodiment shown in FIG. 1 , the output voltage VOUT of the output buffer 100 is fed back to the second input end of the output buffer 100 . According to design requirements, in other embodiments, the output end of the output buffer 100 may be coupled to the second input end of the output buffer 100 via other elements/circuits (not shown), or the output end of the output buffer 100 may not be coupled to the second input end of the output buffer 100.

In the embodiment shown in FIG. 1 , the output buffer 100 includes an input stage circuit 110 , an output stage circuit 120 , a rising control circuit 130 and a falling control circuit 140 . According to design requirements, the input stage circuit 110 may include a differential input pair, a gain circuit and/or other input stage circuits. For example, the input stage circuit 110 may be an input stage circuit of a known operational amplifier or an input stage circuit and/or a gain stage circuit of other amplifiers. The first input terminal of the input stage circuit 110 is coupled to the first input terminal of the output buffer 100 to receive the input voltage VIN. The second input terminal of the input stage circuit 110 is coupled to the second input terminal of the output buffer 100 to receive the output voltage VOUT. The input stage circuit 110 can correspondingly generate the gating voltage PGATE and the gating voltage NGATE according to the input voltage VIN.

The first input terminal of the output stage circuit 120 is coupled to the first output terminal of the input stage circuit 110 to receive the gating voltage PGATE. The second input terminal of the output stage circuit 120 is coupled to the second output terminal of the input stage circuit 110 to receive the gating voltage NGATE. The output terminal of the output stage circuit 120 is coupled to the output terminal of the output buffer 100 . The output stage circuit 120 can correspondingly generate the output voltage VOUT of the output buffer 100 according to the gate control voltage PGATE and the gate control voltage NGATE.

In the embodiment shown in FIG. 1 , the output stage circuit 120 includes a transistor P1 and a transistor N1 . A control terminal (eg gate) of the transistor P1 is coupled to the first output terminal of the input stage circuit 110 to receive the gate control voltage PGATE. A first end (for example, a source) of the transistor P1 is coupled to the system voltage VDDA. The level of the system voltage VDDA can be determined according to design requirements. A second terminal (for example, a drain) of the transistor P1 is coupled to the output terminal of the output stage circuit 120 , wherein the output terminal of the output stage circuit 120 outputs the output voltage VOUT. A control terminal (eg gate) of the transistor N1 is coupled to the second output terminal of the input stage circuit 110 to receive the gate control voltage NGATE. A first end (for example, a source) of the transistor N1 is coupled to a reference voltage VSSA. The level of the reference voltage VSSA can be determined according to design requirements. The second terminal (eg, the drain) of the transistor N1 is coupled to the output terminal of the output stage circuit 120 and the second terminal of the transistor P1 .

The output stage circuit 120 shown in FIG. 1 is an example. In any case, the implementation of the output stage circuit 120 should not be limited to the embodiment shown in FIG. 1 . According to design requirements, the output stage circuit 120 may include any type of output circuit. For example, in other embodiments, the output stage circuit 120 may be an output stage circuit of a known operational amplifier or an output stage circuit of other amplifiers.

FIG. 2 is a schematic flowchart of an operation method of an output buffer according to an embodiment of the present invention. Please refer to Figure 1 and Figure 2. In step S210 , the input stage circuit 110 correspondingly generates a gating voltage PGATE and a gating voltage NGATE according to the input voltage VIN of the output buffer 100 . In step S220 , the output stage circuit 120 correspondingly generates the output voltage VOUT of the output buffer 100 according to the gate control voltage PGATE and the gate control voltage NGATE. In step S230 , the rising control circuit 130 compares the input voltage VIN and the output voltage VOUT to obtain a first comparison result, and the falling control circuit 140 compares the input voltage VIN and the output voltage VOUT to obtain a second comparison result.

When the first comparison result indicates that the output voltage VOUT is to be pulled up ("to be pulled up" in step S240), the rising control circuit 130 may pull down the gating voltages PGATE and NGATE during the transient period (step S250). When the rising control circuit 130 pulls down the gate control voltage NGATE, the turn-off state of the transistor N1 can be ensured to avoid short-circuit current. When the rising control circuit 130 pulls down the gate control voltage PGATE, the current flowing through the transistor P1 can be temporarily increased to speed up pulling up the output voltage VOUT. Therefore, the slew rate (Slew Rate) of the output voltage VOUT can be increased.

According to design requirements, in some embodiments, step S250 may include the following operations. When the input voltage VIN is greater than the output voltage VOUT, the rising control circuit 130 can pull down the gate control voltage PGATE and the gate control voltage NGATE. When the input voltage VIN is less than or equal to the output voltage VOUT, the rising control circuit 130 may not adjust the gate control voltage PGATE and the gate control voltage NGATE.

When both the first comparison result and the second comparison result indicate that the output voltage VOUT will not be changed (“no change” in step S240), the rising control circuit 130 and the falling control circuit 140 may not adjust the gate control voltage PGATE and the gate control voltage NGATE (step S260). When the rising control circuit 130 and the falling control circuit 140 do not interfere with the gate voltage PGATE and the gate voltage NGATE, the levels of the gate voltage PGATE and the gate voltage NGATE are determined by the input stage circuit 110 .

When the second comparison result indicates that the output voltage VOUT is about to be pulled down (“to be pulled down” in step S240 ), the down control circuit 140 may pull up the gating voltages PGATE and NGATE during the transient period (step S270 ). When the down control circuit 140 pulls up the gate control voltage PGATE, the turn off state of the transistor P1 can be ensured to avoid short-circuit current. When the drop control circuit 140 pulls up the gate control voltage NGATE, the current flowing through the transistor N1 can be temporarily increased to speed up pulling down the output voltage VOUT. Therefore, the slew rate of the output voltage VOUT can be increased.

According to design requirements, in some embodiments, step S270 may include the following operations. When the input voltage VIN is lower than the output voltage VOUT, the drop control circuit 140 can pull up the gate control voltage PGATE and the gate control voltage NGATE. When the input voltage VIN is greater than or equal to the output voltage VOUT, the drop control circuit 140 may not adjust the gate control voltage PGATE and the gate control voltage NGATE.

According to different design requirements, the blocks of the rising control circuit 130 and/or the falling control circuit 140 may be implemented in the form of hardware, firmware, software, or a combination of the above three. In terms of hardware, the above-mentioned blocks of the rising control circuit 130 and/or the falling control circuit 140 may be implemented as logic circuits on an integrated circuit. The relevant functions of the above-mentioned rising control circuit 130 and/or the falling control circuit 140 can be implemented as hardware by using hardware description languages (such as Verilog HDL or VHDL) or other suitable programming languages. For example, related functions of the above-mentioned rising control circuit 130 and/or falling control circuit 140 may be implemented in one or more controllers, microcontrollers, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (digital signal processors, DSPs), field programmable gate arrays (Field Programmable Gate Arrays, FPGAs) and/or various logic blocks, modules and circuits in other processing units.

FIG. 3 is a schematic circuit block diagram illustrating the rising control circuit 130 shown in FIG. 1 according to an embodiment of the present invention. In the embodiment shown in FIG. 3 , the rising control circuit 130 includes a comparison circuit 131 , a transistor N2 and a transistor N3 . The comparison circuit 131 can compare the input voltage VIN and the output voltage VOUT to generate the control voltage VC1 as the first comparison result. A control terminal (eg gate) of the transistor N2 is coupled to the output terminal of the comparison circuit 131 to receive the control voltage VC1 . A first end (for example, a source) of the transistor N2 is coupled to the reference voltage VSSA. A second terminal (for example, a drain) of the transistor N2 is coupled to the first input terminal of the output stage circuit 120 to receive the gating voltage PGATE. A control terminal (eg gate) of the transistor N3 is coupled to the output terminal of the comparison circuit 131 to receive the control voltage VC1 . A first end (for example, a source) of the transistor N3 is coupled to the reference voltage VSSA. A second terminal (for example, a drain) of the transistor N3 is coupled to the second input terminal of the output stage circuit 120 to receive the gate control voltage NGATE.

When the input voltage VIN is greater than the output voltage VOUT, the comparison circuit 131 can turn on the transistor N2 and the transistor N3 by controlling the voltage VC1 to pull down the gate voltage PGATE and the gate voltage NGATE. When the input voltage VIN is less than or equal to the output voltage VOUT, the comparison circuit 131 can turn off the transistor N2 and the transistor N3 by controlling the voltage VC1, so the rising control circuit 130 does not interfere with (not adjust) the gate control voltage PGATE and the gate control voltage NGATE.

In the embodiment shown in FIG. 3 , the comparison circuit 131 includes a transistor N4 , a transistor N5 and a current mirror 310 . A control terminal (eg gate) of the transistor N4 is coupled to the input voltage VIN. A first end (for example, a source) of the transistor N4 is coupled to the output voltage VOUT. The main current terminal of the current mirror 310 is coupled to the second terminal (eg, the drain) of the transistor N4. The slave current terminal of the current mirror 310 is coupled to the output terminal of the comparison circuit 131 , wherein the output terminal of the comparison circuit 131 can provide the control voltage VC1 to the transistor N2 and the transistor N3 . A control terminal (eg gate) of the transistor N5 is coupled to the output terminal of the comparison circuit 131 . A first end (for example, a source) of the transistor N5 is coupled to the reference voltage VSSA. The second terminal (for example, the drain) of the transistor N5 is coupled to the slave current terminal of the current mirror 310 and the control terminal of the transistor N5 .

In the embodiment shown in FIG. 3 , the current mirror 310 includes a transistor P2 and a transistor P3 . A first terminal (for example, a source) of the transistor P2 is coupled to the system voltage VDDA. A second terminal (such as a drain) and a control terminal (such as a gate) of the transistor P2 are coupled to the main current terminal of the current mirror 310 . A first terminal (for example, a source) of the transistor P3 is coupled to the system voltage VDDA. A second terminal (for example, a drain) of the transistor P3 is coupled to the slave current terminal of the current mirror 310 . A control terminal (eg, a gate) of the transistor P3 is coupled to a control terminal of the transistor P2 .

FIG. 4 is a schematic circuit block diagram illustrating the rising control circuit 130 shown in FIG. 1 according to another embodiment of the present invention. In the embodiment shown in FIG. 4 , the rising control circuit 130 includes a comparison circuit 132 , a transistor N2 and a transistor N3 . The comparison circuit 132 , the transistor N2 and the transistor N3 shown in FIG. 4 can be analogized with reference to the relevant descriptions of the comparison circuit 131 , the transistor N2 and the transistor N3 shown in FIG. 3 , so details are not repeated here.

In the embodiment shown in FIG. 4 , the comparison circuit 132 includes a transistor N6 , a transistor N7 , a transistor N8 , a transistor N9 , a transistor P4 and a current mirror 310 . A control terminal (eg gate) of the transistor N6 is coupled to the input voltage VIN. A first end (for example, a source) of the transistor N6 is coupled to the output voltage VOUT. The control terminal (eg gate) of the transistor N7 is controlled by the control signal EN. A first terminal (such as a source) of the transistor N7 is coupled to a second terminal (such as a drain) of the transistor N6.

The main current terminal of the current mirror 310 is coupled to the second terminal (eg, the drain) of the transistor N7. The slave current terminal of the current mirror 310 is coupled to the output terminal of the comparison circuit 132 , wherein the output terminal of the comparison circuit 132 can provide the control voltage VC1 to the transistor N2 and the transistor N3 . The current mirror 310 shown in FIG. 4 can be deduced with reference to the relevant description of the current mirror 310 shown in FIG. 3 , so details are not repeated here.

The control terminal (eg gate) of the transistor P4 is controlled by the control signal EN. A first terminal (for example, a source) of the transistor P4 is coupled to the system voltage VDDA. A second terminal (for example, a drain) of the transistor P4 is coupled to an enable terminal of the current mirror 310 . That is, the second terminal of the transistor P4 is coupled to the control terminal of the transistor P2 and the control terminal of the transistor P3 . A control terminal (eg gate) of the transistor N8 is coupled to the output terminal of the comparison circuit 132 . A first terminal (for example, a source) of the transistor N8 is coupled to the reference voltage VSSA. The second terminal (for example, the drain) of the transistor N8 is coupled to the slave current terminal of the current mirror 310 and the control terminal of the transistor N8 . The control terminal (eg gate) of the transistor N9 is controlled by the control signal ENB. The control signal ENB is an inverted signal of the control signal EN. A first end (for example, a source) of the transistor N9 is coupled to the reference voltage VSSA. A second terminal (for example, a drain) of the transistor N9 is coupled to a control terminal of the transistor N8.

When the control signal EN is at a high voltage level (such as the level of the system voltage VDDA or other levels), that is, when the control signal ENB is at a low voltage level (such as the level of the reference voltage VSSA or other levels), the transistor N7 is turned on, and the transistors P4 and transistor N9 are turned off. At this time, the operation of the comparison circuit 132 shown in FIG. 4 is similar to the operation of the comparison circuit 131 shown in FIG. 3 . When the control signal EN is at a low voltage level (that is, the control signal ENB is at a high voltage level), the transistor N7 is turned off, and the transistor P4 and the transistor N9 are turned on. At this time, the comparison circuit 132 shown in FIG. 4 is disabled, and the control voltage VC1 is pulled down to a low voltage level. When the control voltage VC1 is pulled down to a low voltage level, the transistor N2 and the transistor N3 are turned off. Therefore, when the control signal EN (control signal ENB) disables the boost control circuit 130 , the boost control circuit 130 may not interfere (not adjust) the gating voltages PGATE and NGATE.

In some application scenarios, after the output voltage VOUT is pulled down, the output voltage VOUT may be lower (less than) the input voltage VIN for a specific period, and then the level of the output voltage VOUT returns to be consistent with the input voltage VIN after the specific period ends. Generally, the specified period is short. Controlled by the control signal EN (control signal ENB), the rising control circuit 130 can be disabled during the specified period and enabled outside the specified period. Therefore, malfunction of the rise control circuit 130 during the specific period can be avoided.

FIG. 5 is a circuit block diagram illustrating the drop control circuit 140 shown in FIG. 1 according to an embodiment of the present invention. In the embodiment shown in FIG. 5 , the falling control circuit 140 includes a comparison circuit 141 , a transistor P5 and a transistor P6 . The comparison circuit 141 can compare the input voltage VIN and the output voltage VOUT to generate the control voltage VC2 as the second comparison result. A control terminal (eg gate) of the transistor P5 is coupled to the output terminal of the comparison circuit 141 to receive the control voltage VC2 . A first end (for example, a source) of the transistor P5 is coupled to the system voltage VDDA. A second terminal (for example, a drain) of the transistor P5 is coupled to the first input terminal of the output stage circuit 120 to receive the gating voltage PGATE. A control terminal (eg gate) of the transistor P6 is coupled to the output terminal of the comparison circuit 141 to receive the control voltage VC2 . A first terminal (for example, a source) of the transistor P6 is coupled to the system voltage VDDA. A second terminal (for example, a drain) of the transistor P6 is coupled to the second input terminal of the output stage circuit 120 to receive the gate control voltage NGATE.

When the input voltage VIN is lower than the output voltage VOUT, the comparison circuit 141 can turn on the transistor P5 and the transistor P6 by controlling the voltage VC2 to pull up the gate voltage PGATE and the gate voltage NGATE. When the input voltage VIN is greater than or equal to the output voltage VOUT, the comparison circuit 141 can turn off the transistor P5 and the transistor P6 through the control voltage VC2, so the drop control circuit 140 does not interfere with (not adjust) the gate control voltage PGATE and the gate control voltage NGATE.

In the embodiment shown in FIG. 5 , the comparison circuit 141 includes a transistor P7 , a transistor P8 and a current mirror 510 . A control terminal (eg gate) of the transistor P7 is coupled to the input voltage VIN. A first end (for example, a source) of the transistor P7 is coupled to the output voltage VOUT. The main current terminal of the current mirror 510 is coupled to the second terminal (eg, the drain) of the transistor P7. The slave current terminal of the current mirror 510 is coupled to the output terminal of the comparison circuit 141 , wherein the output terminal of the comparison circuit 141 can provide the control voltage VC2 to the transistor P5 and the transistor P6 . A control terminal (eg gate) of the transistor P8 is coupled to the output terminal of the comparison circuit 141 . A first terminal (for example, a source) of the transistor P8 is coupled to the system voltage VDDA. The second terminal (for example, the drain) of the transistor P8 is coupled to the slave current terminal of the current mirror 510 and the control terminal of the transistor P8 .

In the embodiment shown in FIG. 5 , the current mirror 510 includes a transistor N10 and a transistor N11 . A first end (for example, a source) of the transistor N10 is coupled to the reference voltage VSSA. A second terminal (such as a drain) and a control terminal (such as a gate) of the transistor N10 are coupled to the main current terminal of the current mirror 510 . A first end (for example, a source) of the transistor N11 is coupled to the reference voltage VSSA. A second terminal (for example, a drain) of the transistor N11 is coupled to the slave current terminal of the current mirror 510 . A control terminal (eg, a gate) of the transistor N11 is coupled to a control terminal of the transistor N10 .

FIG. 6 is a circuit block diagram illustrating the droop control circuit 140 shown in FIG. 1 according to another embodiment of the present invention. In the embodiment shown in FIG. 6 , the falling control circuit 140 includes a comparison circuit 142 , a transistor P5 and a transistor P6 . The comparison circuit 142 , transistor P5 and transistor P6 shown in FIG. 6 can be analogized with reference to the descriptions of the comparison circuit 141 , transistor P5 and transistor P6 shown in FIG. 5 , so details are not repeated here.

In the embodiment shown in FIG. 6 , the comparison circuit 142 includes a transistor P9 , a transistor P10 , a transistor P11 , a transistor P12 , a transistor N12 and a current mirror 510 . A control terminal (eg gate) of the transistor P9 is coupled to the input voltage VIN. A first end (for example, a source) of the transistor P9 is coupled to the output voltage VOUT. The control terminal (eg gate) of the transistor P10 is controlled by the control signal ENB. A first terminal (such as a source) of the transistor P10 is coupled to a second terminal (such as a drain) of the transistor P9.

The main current terminal of the current mirror 510 is coupled to the second terminal (eg, the drain) of the transistor P10 . The slave current terminal of the current mirror 510 is coupled to the output terminal of the comparison circuit 142 , wherein the output terminal of the comparison circuit 142 can provide the control voltage VC2 to the transistor P5 and the transistor P6 . The current mirror 510 shown in FIG. 6 can be deduced by referring to the relevant description of the current mirror 510 shown in FIG. 5 , so details are not repeated here.

The control terminal (eg gate) of the transistor N12 is controlled by the control signal ENB. A first end (for example, a source) of the transistor N12 is coupled to the reference voltage VSSA. A second terminal (for example, a drain) of the transistor N12 is coupled to an enable terminal of the current mirror 510 . That is, the second terminal of the transistor N12 is coupled to the control terminal of the transistor N10 and the control terminal of the transistor N11 . A control terminal (eg gate) of the transistor P11 is coupled to the output terminal of the comparison circuit 142 . A first end (for example, a source) of the transistor P11 is coupled to the system voltage VDDA. The second terminal (for example, the drain) of the transistor P11 is coupled to the slave current terminal of the current mirror 510 and the control terminal of the transistor P11 . The control terminal (eg gate) of the transistor P12 is controlled by the control signal EN. The control signal EN is an inverted signal of the control signal ENB. A first end (for example, a source) of the transistor P12 is coupled to the system voltage VDDA. The second terminal (for example, the drain) of the transistor P12 is coupled to the control terminal of the transistor P11.

When the control signal EN is at a high voltage level (such as the level of the system voltage VDDA or other levels), that is, when the control signal ENB is at a low voltage level (such as the level of the reference voltage VSSA or other levels), the transistor P10 is turned on, and the transistors N12 and P12 are turned off. At this time, the operation of the comparison circuit 142 shown in FIG. 6 is similar to the operation of the comparison circuit 141 shown in FIG. 5 . When the control signal EN is at a low voltage level (that is, the control signal ENB is at a high voltage level), the transistor P10 is turned off, and the transistor N12 and the transistor P12 are turned on. At this time, the comparison circuit 142 shown in FIG. 6 is disabled, and the control voltage VC2 is pulled up to a high voltage level. When the control voltage VC2 is pulled up to a high voltage level, the transistor P5 and the transistor P6 are turned off. Therefore, when the control signal EN (control signal ENB) disables the down control circuit 140 , the down control circuit 140 may not interfere (not adjust) the gating voltages PGATE and NGATE.

In some application scenarios, after the output voltage VOUT is pulled up, the output voltage VOUT may exceed (greater than) the input voltage VIN for a specific period, and then the level of the output voltage VOUT returns to be consistent with the input voltage VIN after the specific period ends. Generally, the specified period is short. Controlled by the control signal EN (control signal ENB), the drop control circuit 140 can be disabled during the specified period, and enabled (enable) outside the specified period. Therefore, malfunction of the drop control circuit 140 during the specific period can be avoided.

To sum up, the output buffer 100 and its operation method according to various embodiments of the present invention can compare the input voltage VIN and the output voltage VOUT. When the output voltage VOUT is to be pulled up, both the gating voltage PGATE and the gating voltage NGATE of the output stage circuit 120 of the output buffer 100 are pulled down to increase the slew rate of the output voltage VOUT. When the output voltage VOUT is to be pulled down, both the gate control voltage PGATE and the gate control voltage NGATE of the output stage circuit 120 of the output buffer 100 are pulled up to increase the slew rate of the output voltage VOUT.

Although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be as defined by the appended claims.

Claims (15)

1. An output buffer, comprising:

an input stage circuit configured to receive an input voltage of the output buffer and to generate a first gating voltage and a second gating voltage according to the input voltage, respectively;

an output stage circuit coupled to the input stage circuit for receiving the first and second gate voltages, and configured to generate an output voltage of the output buffer according to the first and second gate voltages, respectively;

a boost control circuit configured to compare the input voltage with the output voltage to obtain a first comparison result, wherein the boost control circuit pulls down the first and second gating voltages during a first transient when the first comparison result indicates that the output voltage is to be pulled up; and

a droop control circuit configured to compare the input voltage with the output voltage to obtain a second comparison result, wherein the droop control circuit pulls up the first and second gating voltages during a second transient when the second comparison result indicates that the output voltage is to be pulled down.

2. The output buffer of claim 1 wherein the output stage circuit comprises:

a first transistor having a control terminal coupled to the input stage circuit for receiving the first gate voltage, wherein a first terminal of the first transistor is coupled to a system voltage, a second terminal of the first transistor is coupled to an output terminal of the output stage circuit, and an output terminal of the output stage circuit outputs the output voltage of the output buffer; and

a second transistor having a control terminal coupled to the input stage circuit for receiving the second gate voltage, wherein a first terminal of the second transistor is coupled to a reference voltage, and a second terminal of the second transistor is coupled to the output terminal of the output stage circuit.

3. The output buffer of claim 1,

when the input voltage is greater than the output voltage, the rising control circuit pulls down the first and second gate voltages, and

when the input voltage is less than or equal to the output voltage, the rising control circuit does not adjust the first gate voltage and the second gate voltage.

4. The output buffer of claim 1 wherein the rise control circuit comprises:

a comparison circuit configured to compare the input voltage with the output voltage to generate a control voltage as the first comparison result;

a first transistor having a control terminal coupled to an output terminal of the comparison circuit for receiving the control voltage, wherein a first terminal of the first transistor is coupled to a reference voltage, and a second terminal of the first transistor is coupled to a first input terminal of the output stage circuit for receiving the first gate voltage; and

a second transistor having a control terminal coupled to the output terminal of the comparison circuit for receiving the control voltage, wherein a first terminal of the second transistor is coupled to the reference voltage, and a second terminal of the second transistor is coupled to a second input terminal of the output stage circuit for receiving the second gate voltage.

5. The output buffer of claim 4 wherein the comparison circuit comprises:

a third transistor having a control terminal coupled to the input voltage, wherein a first terminal of the third transistor is coupled to the output voltage;

a current mirror having a master current terminal coupled to a second terminal of the third transistor, wherein a slave current terminal of the current mirror is coupled to the output terminal of the comparison circuit; and

a fourth transistor having a control terminal coupled to the output terminal of the comparing circuit, wherein a first terminal of the fourth transistor is coupled to the reference voltage, and a second terminal of the fourth transistor is coupled to the slave current terminal of the current mirror.

6. The output buffer of claim 4 wherein the comparison circuit comprises:

a third transistor having a control terminal coupled to the input voltage, wherein a first terminal of the third transistor is coupled to the output voltage;

a fourth transistor having a control terminal controlled by a first control signal, wherein a first terminal of the fourth transistor is coupled to a second terminal of the third transistor;

a current mirror having a master current terminal coupled to a second terminal of the fourth transistor, wherein a slave current terminal of the current mirror is coupled to the output terminal of the comparison circuit;

a fifth transistor having a control terminal controlled by the first control signal, wherein a first terminal of the fifth transistor is coupled to a system voltage, and a second terminal of the fifth transistor is coupled to an enable terminal of the current mirror; and

a sixth transistor having a control terminal coupled to the output terminal of the comparing circuit, wherein a first terminal of the sixth transistor is coupled to the reference voltage, and a second terminal of the sixth transistor is coupled to the slave current terminal of the current mirror.

7. The output buffer of claim 6 wherein the comparison circuit further comprises:

a seventh transistor having a control terminal controlled by a second control signal, wherein a first terminal of the seventh transistor is coupled to the reference voltage and a second terminal of the seventh transistor is coupled to the control terminal of the sixth transistor.

8. The output buffer of claim 1,

when the input voltage is smaller than the output voltage, the falling control circuit pulls up the first and second gate voltages, and

when the input voltage is greater than or equal to the output voltage, the drop control circuit does not adjust the first gate voltage and the second gate voltage.

9. The output buffer of claim 1 wherein the droop control circuit comprises:

a comparison circuit configured to compare the input voltage with the output voltage to generate a control voltage as the second comparison result;

a first transistor having a control terminal coupled to an output terminal of the comparison circuit for receiving the control voltage, wherein a first terminal of the first transistor is coupled to a system voltage, and a second terminal of the first transistor is coupled to a first input terminal of the output stage circuit for receiving the first gate voltage; and

a second transistor having a control terminal coupled to the output terminal of the comparison circuit for receiving the control voltage, wherein a first terminal of the second transistor is coupled to the system voltage, and a second terminal of the second transistor is coupled to a second input terminal of the output stage circuit for receiving the second gate voltage.

10. The output buffer of claim 9 wherein the comparison circuit comprises:

a third transistor having a control terminal coupled to the input voltage, wherein a first terminal of the third transistor is coupled to the output voltage;

a current mirror having a master current terminal coupled to a second terminal of the third transistor, wherein a slave current terminal of the current mirror is coupled to the output terminal of the comparison circuit; and

a fourth transistor having a control terminal coupled to the output terminal of the comparing circuit, wherein a first terminal of the fourth transistor is coupled to the system voltage, and a second terminal of the fourth transistor is coupled to the slave current terminal of the current mirror.

11. The output buffer of claim 9 wherein the comparison circuit comprises:

a third transistor having a control terminal coupled to the input voltage, wherein a first terminal of the third transistor is coupled to the output voltage;

a fourth transistor having a control terminal controlled by a first control signal, wherein a first terminal of the fourth transistor is coupled to a second terminal of the third transistor;

a current mirror having a master current terminal coupled to a second terminal of the fourth transistor, wherein a slave current terminal of the current mirror is coupled to the output terminal of the comparison circuit;

a fifth transistor having a control terminal controlled by the first control signal, wherein a first terminal of the fifth transistor is coupled to a reference voltage, and a second terminal of the fifth transistor is coupled to an enable terminal of the current mirror; and

a sixth transistor having a control terminal coupled to the output terminal of the comparing circuit, wherein a first terminal of the sixth transistor is coupled to the system voltage, and a second terminal of the sixth transistor is coupled to the slave current terminal of the current mirror.

12. The output buffer of claim 11 wherein the comparison circuit further comprises:

a seventh transistor having a control terminal controlled by a second control signal, wherein a first terminal of the seventh transistor is coupled to the system voltage and a second terminal of the seventh transistor is coupled to the control terminal of the sixth transistor.

13. A method of operation of an output buffer, comprising:

generating a first gate voltage and a second gate voltage by an input stage circuit according to an input voltage of the output buffer;

generating an output voltage of the output buffer by an output stage circuit according to the first gating voltage and the second gating voltage correspondingly;

comparing the input voltage with the output voltage by a rising control circuit to obtain a first comparison result;

when the first comparison result indicates that the output voltage is to be pulled up, the first gate voltage and the second gate voltage are pulled down by the rising control circuit during a first transient period;

comparing the input voltage with the output voltage by a falling control circuit to obtain a second comparison result; and

when the second comparison result indicates that the output voltage is to be pulled down, the first gate voltage and the second gate voltage are pulled up by the falling control circuit during a second transient period.

14. The method of operation of claim 13, wherein the step of pulling down the first and second gating voltages comprises:

when the input voltage is larger than the output voltage, the rising control circuit pulls down the first gating voltage and the second gating voltage; and

when the input voltage is less than or equal to the output voltage, the first gate voltage and the second gate voltage are not adjusted by the rising control circuit.

15. The method of operation of claim 13, wherein the step of pulling up the first and second gating voltages comprises:

when the input voltage is smaller than the output voltage, the first and second gate voltages are pulled up by the down control circuit, and

when the input voltage is greater than or equal to the output voltage, the first gate voltage and the second gate voltage are not adjusted by the falling control circuit.