CN111722265B - Satellite-borne single particle monitor - Google Patents

Abstract

The invention belongs to the technical field of space particle measuring devices, and particularly relates to a satellite-borne single particle monitor, which comprises: the device comprises a first semiconductor detector (1), a second semiconductor detector (2), a third semiconductor detector (3), a device to be tested (4), a printed board (5), a preamplification circuit board (6), a first aluminum shielding box (7), a second aluminum shielding box (8), a third aluminum shielding box (9) and an FPGA processing circuit; a device to be tested (4) is welded and installed on one side of the printed board (5), a second aluminum shielding box (8) is installed on the printed board, and a first semiconductor detector (1) and a second semiconductor detector (2) are correspondingly installed at the top and the bottom of the printed board; and a third aluminum shielding box (9) is fixed on the other side of the printed board (5) through a second mounting hole (14), each semiconductor detector is respectively connected with the FGPA processing circuit through respective detection branch circuits, and the device to be tested (5) is connected with the FPGA processing circuit through a monitoring circuit arranged on the device to be tested.

Description

A spaceborne single particle monitor

technical field

The invention belongs to the technical field of space particle measurement devices, in particular to a spaceborne single particle monitor.

Background technique

When the satellite is in orbit, the space environment is complex and harsh, and a large number of charged particles existing in the orbital space can threaten the safety of the spacecraft in orbit through various radiation effects, including single event effect, displacement damage effect, total dose effect, and charge-discharge effect. performance. Among them, the single event effect is one of the most harmful radiation effects to the spacecraft electronic system, which can cause changes in the logic state of electronic devices used in satellites, circuit logic disorders, errors in computer-processed data, errors in instructions, and program "running". "flying", the computer is paralyzed, the bulk silicon CMOS devices and power devices are burned by the large current induced by them, so that the satellite is abnormal and malfunctioning, and even the satellite is in a catastrophic situation.

Single-event effect detection generally includes two aspects: space radiation LET (Linear Energy Transfer, also known as Linear Energy Transfer Density) spectrum and device single-event overturning events; using silicon detection technology, on-orbit detection of space radiation LET spectrum, and measurement of space radiation LET spectra, and statistical analysis of single-event overturn events of onboard devices. Through the measurement of the space radiation LET spectrum, effective and accurate space environment effect parameters are obtained, which are used to evaluate the characteristics of the device on-orbit single-event effect; through the actual measurement of the device's single-event overturning event, the probability record of the device's on-orbit single-event overturning event is obtained.

At present, my country's space particle radiation effect detection technology is in its infancy, and there is still a big gap between the detection technology and the international one. The existing particle radiation measurement devices basically use a set of sensors, generally only measure the particle radiation LET spectrum, and cannot monitor the single-particle flip of the key components of the spaceborne equipment, and have a single function.

The problems existing in the existing technology mainly include:

The current particle radiation LET spectrum detectors are all radiation effect measurement devices with single function, which cannot simultaneously realize the integration of single-particle overturn monitoring of the key core components of the spacecraft. Specifically, on the one hand, the particle radiation effect measurement devices currently installed on domestic satellites are all "three-in-one" products, which are only used for the measurement of space particle LET spectrum, and have a single function. Simultaneous measurement of particle flipping; on the other hand, due to the limitations of previous detection devices in terms of system integration and satellite power consumption requirements, it is difficult to achieve the above two measurement goals while meeting the requirements of high integration and low power consumption.

SUMMARY OF THE INVENTION

In order to solve the above-mentioned defects in the prior art, the present invention proposes a spaceborne single-particle monitor, in particular to a detection device capable of simultaneously measuring the particle space radiation LET spectrum and the single-particle turnover times of the device under test, which overcomes the current The radiation LET spectrum measurement device only uses a set of sensors to measure the particle space radiation LET spectrum, and cannot monitor the single-particle flip of the device at the same time, and measure defects with a single function.

The spaceborne single particle monitor includes: a first semiconductor detector, a second semiconductor detector, a third semiconductor detector, a device to be tested, a printed board, a preamplifier circuit board, a first aluminum shielding box, a third The second aluminum shielding box, the third aluminum shielding box and the FPGA processing circuit;

The device to be tested is welded and installed on one side of the printed board; a second aluminum shielding box is installed on the device to be tested, and the top and bottom of the second aluminum shielding box are respectively installed with the first semiconductor detector and the second semiconductor detector device;

A first aluminum shielding box is provided on one side of the second aluminum shielding box in the extending direction, and a common wall provided with a first pin is shared between the first aluminum shielding box and the second aluminum shielding box. Through the first pins, it is connected to the preamplifier circuit board arranged in the first aluminum shielding box; the preamplifier circuit board is fixed on the four first mounting holes located at the four corners of the first aluminum shielding box;

The third aluminum shielding box is fixed on the other side of the printed board through the second mounting hole, and the third semiconductor detector is fixedly installed in the third aluminum shielding box, and the third aluminum shielding box is provided with a second pin , connected with the preamplifier circuit board arranged in the first aluminum shielding box;

The first semiconductor detector, the second semiconductor detector and the third semiconductor detector are respectively connected to the FGPA processing circuit through their respective detection branches, and the device to be tested is connected to the FPGA processing circuit through the monitoring circuit provided thereon.

As one of the improvements of the above technical solutions, a first preamplifier, a second preamplifier and a third preamplifier are respectively provided on the preamplifier circuit board, respectively corresponding to the first semiconductor detector, the second preamplifier and the third preamplifier. The semiconductor detector and the third semiconductor detector are connected, respectively amplify and convert the charge signal collected by the first semiconductor detector, the charge signal collected by the second semiconductor detector, and the charge signal collected by the third semiconductor detector to obtain the corresponding The amplified converted voltage pulse signal.

As one of the improvements of the above technical solutions, the first semiconductor detector and the first preamplifier, the shaping circuit, the main amplifier, the peak holder and the ADC acquisition circuit arranged on the corresponding detection branch are connected in sequence;

The second semiconductor detector is sequentially connected with the first preamplifier, the shaping circuit, the main amplifier, the peak holder, and the ADC acquisition circuit provided on the corresponding detection branch;

The third semiconductor detector is sequentially connected with the first preamplifier, the shaping circuit, the main amplifier, the peak holder, and the ADC acquisition circuit provided on the corresponding detection branch;

The above three detection branches are all connected with the FPGA processing circuit, and the FPGA processing circuit is connected with the satellite through the interface circuit and the satellite interface.

As one of the improvements of the above technical solutions, a noise detection circuit is added between the main amplifier and the peak hold in each detection branch, so as to perform amplification processing and analog-to-digital conversion according to the received noise signal, and convert the obtained The digital signal is input to the FPGA processing circuit.

As one of the improvements of the above technical solutions, the instrument noise detection circuit includes: an amplifier and an ADC acquisition circuit;

The output end of the amplifier is connected to the input end of the ADC acquisition circuit, and the output end of the ADC acquisition circuit is connected to the input end of the FPGA processing circuit.

As one of the improvements of the above technical solutions, the FPGA processing circuit includes:

a first data receiving module, configured to receive the converted digital signal obtained by each semiconductor detector through the corresponding detection branch;

The first data processing module is used for performing amplitude analysis and data processing according to the obtained three converted digital signals to obtain the LET spectrum of the space charged particles;

The second data receiving module is used to receive the inversion information generated after the space high-energy charged particles are incident on the sensitive area of the SRAM chip;

The second data processing module is used to perform data processing on the flip information to obtain the single-particle flip times of the device under test;

The third data receiving module is used for receiving the digital signal output by the noise detection circuit;

The third data processing module is used for processing according to the received digital signal output by the noise detection circuit to detect the working condition of each detection branch.

As one of the improvements of the above technical solutions, the monitor further includes: an output interface circuit for performing data communication with the satellite bus.

The beneficial effects of the present invention compared with the prior art are:

The detection device of the invention can simultaneously measure the particle space radiation LET spectrum and the single-particle turnover times of the device to be measured, especially the LET spectrum of high-energy protons and heavy ions, and the single-particle turnover times of the device to be measured; realize the above two measurements At the same time, it can meet the requirements of high integration and low power consumption; when it is used for the LET spectrum measurement of space charged particle radiation, the working status of each detection branch can be learned in time, and the signal-to-noise ratio is improved.

Description of drawings

Fig. 1 is the circuit connection block diagram of a kind of spaceborne single particle monitor of the present invention;

Fig. 2 is the structure diagram of a kind of spaceborne single particle monitor of the present invention;

3 is a three-dimensional structural diagram of a spaceborne single particle monitor of the present invention without a preamplifier circuit board installed;

FIG. 4 is a processing flow chart of an FPGA processing circuit of a spaceborne single particle monitor of the present invention.

Reference number:

1. The first semiconductor detector 2. The second semiconductor detector

3. The third semiconductor detector 4. The device under test

5. Printed board 6. Preamplifier circuit board

7. The first aluminum shielding box 8. The second aluminum shielding box

9. The third aluminum shielding box 10. The first mounting hole

11. The first pin 12. The second pin

13. Common wall 14. Second mounting hole

Detailed ways

The present invention will now be further described with reference to the accompanying drawings.

The present invention provides a spaceborne single particle monitor, which is a space particle radiation effect measurement device. The monitor is in a sandwich structure, and the device to be measured 4 is sandwiched between the second semiconductor detector 2 and the third semiconductor detector. 3, and the first semiconductor detector 1 is arranged on the second semiconductor detector 2, and each semiconductor detector and the corresponding preamplifier are arranged in the corresponding aluminum shielding box to reduce noise interference and improve anti-interference ability. .

Specifically, as shown in FIGS. 1 and 2 , the spaceborne single particle monitor includes: a first semiconductor detector 1 , a second semiconductor detector 2 , a third semiconductor detector 3 , a device under test 4 , and a printed board 5. The preamplifier circuit board 6, the first aluminum shielding box 7, the second aluminum shielding box 8 and the third aluminum shielding box 9;

The device under test 4 is fixedly installed on one side of the printed board 5 and is connected to the device under test 4; a second aluminum shielding box 8 is installed on the device under test 4, and the top of the second aluminum shielding box 8 is A first semiconductor detector 1 and a second semiconductor detector 2 are respectively installed at the bottom, and the second semiconductor detector 2 is installed on the device under test 4;

One side of the second aluminum shielding box 8 is provided with the first aluminum shielding box 7 , and the first aluminum shielding box 7 and the second aluminum shielding box 8 share a common wall 13 . 13 is provided with a first pin 11 for connecting with the preamplifier circuit board 6 arranged in the first aluminum shielding box 7; the four corners of the first aluminum shielding box 7 are respectively provided with first mounting holes 10 , the preamplifier circuit board 6 is fixed on the four first mounting holes 10 at the four corners of the first aluminum shielding box 7 by screws;

The third aluminum shielding box 9 is fixed on the other side of the printed board 5 through the second mounting hole 14 , and the third semiconductor detector 3 is fixedly installed in the third aluminum shielding box 9 . A second pin is provided for connecting with the preamplifier circuit board 6 arranged in the first aluminum shielding box 7;

The first semiconductor detector 1 , the second semiconductor detector 2 and the third semiconductor detector 3 are respectively connected to the FGPA processing circuit through their respective detection branches, and the device under test 4 is connected to the FPGA processing circuit through the monitoring circuit provided on it. connect.

The monitor further includes an output interface circuit for data communication with the satellite bus.

The first semiconductor detector 1 , the second semiconductor detector 2 and the third semiconductor detector 3 are all ion implantation detectors with a thickness of 300um, a diameter of Φ20mm, and a sensitive area of 8mm in diameter.

The preamplifier circuit board 7 is respectively provided with a first preamplifier, a second preamplifier and a third preamplifier, which correspond to the first semiconductor detector 1, the second semiconductor detector 2 and the The third semiconductor detector 3 is connected to amplify and convert the charge signal collected by the first semiconductor detector 1, the charge signal collected by the second semiconductor detector 2, and the charge signal collected by the third semiconductor detector 3, respectively, to obtain corresponding The amplified converted voltage pulse signal.

Wherein, the first preamplifier, the second preamplifier and the third preamplifier all adopt an integrated operational amplifier capacitor feedback mode.

The first semiconductor detector 1 is sequentially connected with the first preamplifier, the shaping circuit, the main amplifier, the peak holder, and the ADC acquisition circuit provided on the corresponding detection branch;

The second semiconductor detector 2 is sequentially connected with the first preamplifier, the shaping circuit, the main amplifier, the peak holder, and the ADC acquisition circuit provided on the corresponding detection branch;

The third semiconductor detector 3 is sequentially connected with the first preamplifier, the shaping circuit, the main amplifier, the peak holder, and the ADC acquisition circuit provided on the corresponding detection branch;

The above three detection branches are all connected with the FPGA processing circuit, and the FPGA processing circuit is connected with the satellite through the interface circuit and the satellite interface.

Specifically, as shown in Figure 1, the output end of the preamplifier corresponding to each semiconductor detector is respectively connected to the input end of the corresponding main amplifier, and the output end of each main amplifier is respectively connected to the input end of the corresponding peak holder , the output end of each peak holder is respectively connected with the input end of the corresponding ADC acquisition circuit, the ADC acquisition circuit is connected to the input end of the FPGA processing circuit, and the output end of the ADC acquisition circuit after the analog-to-digital conversion of the collected signal is connected to the input end of the FPGA processing circuit. The output end of each main amplifier is respectively connected with an instrument noise detection circuit for detecting the working condition of each detection branch. The instrument noise detection circuit includes an amplifier for amplifying noise signals and an ADC acquisition circuit; the output end of the amplifier is connected to the input end of the ADC acquisition circuit, and the output end of the ADC acquisition circuit is connected to the input end of the FPGA processing circuit.

A noise detection circuit is added between the main amplifier and the peak holder in each detection branch to perform amplification processing and analog-to-digital conversion according to the received noise signal, and input the obtained digital signal to the FPGA processing circuit. The processing result of the processing circuit detects the working status of each device on the corresponding detection branch, which avoids the reliability and accuracy of the detection result being affected by the failure of the monitor of the present invention during the spatial detection process.

The instrument noise detection circuit includes: an amplifier for amplifying noise signals and an ADC acquisition circuit; the output end of the amplifier is connected to the input end of the ADC acquisition circuit, and the output end of the ADC acquisition circuit is connected to the input end of the FPGA processing circuit.

The device under test 4 is connected to the FPGA processing circuit through a monitoring circuit provided thereon, and is used for inputting the inversion information generated on the device under test 4 scanned periodically to the FPGA processing circuit.

Among them, the device to be tested 4 is composed of one or more of CPU, FPGA, SRAM, SDARM, and FLASH, and its single-particle flip times are monitored by the FPGA processing circuit. In this embodiment, the device under test 4 is an SRAM chip.

The printed board 5 is a circuit board.

Since the weak charge signal output by each semiconductor detector needs to be amplified and processed by the corresponding preamplifier, each semiconductor detector should be as close as possible to the corresponding preamplifier. It needs to be installed in the corresponding aluminum shielding box to achieve the purpose of reducing noise interference.

The working principle of the single particle monitor is as follows:

When space high-energy charged particles are incident on each semiconductor detector, different energy losses will be generated in the corresponding semiconductor detectors, and the output of each semiconductor detector reflects the charge signal of the energy relationship of the incident particles, that is, each semiconductor detector The detector outputs a charge signal; the charge signal amplifies and converts the charge signal that reflects the charge energy output by the semiconductor detector through a preamplifier corresponding to the semiconductor detector, to obtain a voltage pulse signal, which is input to the input of the main amplifier The amplified signal is input to the input terminal of the peak hold device and the pulse peak value is held to obtain the signal of pulse peak hold, and the signal is input to the ADC acquisition circuit for analog-to-digital conversion, and the converted digital signal is obtained. Input to the FPGA processing circuit, perform amplitude analysis and data processing, and obtain the amplitude of space charged particles. Different amplitudes represent charged particles with different energies. According to the obtained amplitudes of space charged particles, combined with the known thickness of the semiconductor detector, The LET spectrum of the space charged particle can be obtained.

The space high-energy charged particles are incident on the sensitive area of the SRAM chip, causing single-event flipping of the memory cells on the SRAM chip, that is, the content changes from 0 to 1, or from 1 to 0, which is recorded as a single-particle flip once digital signal, and Taking it as flip information, the flip information is input to the monitoring circuit for recording, and input to the FPGA processing circuit for data processing to obtain the single-event flip times of the device under test.

Among them, the processing process of the FPGA processing circuit is as follows, as shown in Figure 4:

Step S3-1, any time a reset signal arrives, re-initialize;

Step S3-2, judging whether the transmission of the data packet is completed; if the transmission of the data packet is completed, then the storage unit on the SRAM chip is cleared for 1 second; the data packet is the space charged particle LET spectrum processed by the FPGA processing circuit And the number of single event flips, time information, packet header, packet tail and identification of the device under test.

Step S3-3, when there is a time correction command, perform time code correction;

Step S3-4, when there is instruction injection, perform instruction parsing;

Step S3-5, when there is a trigger signal, start the ADC acquisition and conversion, and perform threshold comparison and cache on the ADC conversion result;

Step S3-6, judging whether the collection time is a predetermined time, in the present embodiment, the predetermined time can be set to 1 second, if it is, the engineering parameters are collected and written into the SRAM memory;

Step S3-7, determine whether there is a data request command, if so, send the completed data packet; when no data packet is completed, wait for the current data packet to be completed before sending; after the transmission is completed, format the memory RAM and start New packaging process.

The FPGA processing circuit includes:

a first data receiving module, configured to receive the converted digital signal obtained by each semiconductor detector through the corresponding detection branch;

The first data processing module is used for performing amplitude analysis and data processing according to the obtained three converted digital signals to obtain the LET spectrum of the space charged particles;

Specifically, for the obtained three converted digital signals, the existing amplitude comparison method is used to obtain the amplitudes of the corresponding space charged particles, that is, three amplitude values, and the corresponding three different threshold values obtained through theoretical calculation The voltages are compared, and according to the comparison results, combined with the known thickness of each semiconductor detector, the LET spectrum of the space-charged particles is obtained.

The second data receiving module is used to receive the inversion information generated after the space high-energy charged particles are incident on the sensitive area of the SRAM chip;

The second data processing module is used to perform data processing on the flip information to obtain the single-particle flip times of the device under test;

Specifically, the space high-energy charged particles are incident on the sensitive area of the device under test 4, and a single-particle flip occurs, that is, the content changes from 0 to 1, or from 1 to 0, which is recorded as a single-particle flip once digital signal, and it is As the inversion information, the inversion information is input to the monitoring circuit for recording, the monitoring circuit performs regular scanning, and the scanned inversion information is input to the second data processing module for data processing to obtain the single-event inversion times of the device under test.

The third data receiving module is used for receiving the digital signal output by the noise detection circuit;

The third data processing module is used for processing according to the received digital signal output by the noise detection circuit to detect the working condition of each detection branch.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the embodiments, those of ordinary skill in the art should understand that any modification or equivalent replacement of the technical solutions of the present invention will not depart from the spirit and scope of the technical solutions of the present invention, and should be included in the present invention. within the scope of the claims.

Claims (7)

1. An on-board single particle monitor, comprising: the device comprises a first semiconductor detector (1), a second semiconductor detector (2), a third semiconductor detector (3), a device to be detected (4), a printed board (5), a preamplification circuit board (6), a first aluminum shielding box (7), a second aluminum shielding box (8), a third aluminum shielding box (9) and an FPGA processing circuit;

a device to be tested (4) is welded and mounted on one side of the printed board (5); a second aluminum shielding box (8) is arranged on the device to be tested (4), and the top and the bottom of the second aluminum shielding box (8) are respectively provided with a first semiconductor detector (1) and a second semiconductor detector (2) correspondingly;

a first aluminum shielding box (7) is arranged in the extending direction of one side of the second aluminum shielding box (8), a common wall (13) provided with a first pin (11) is shared between the first aluminum shielding box (7) and the second aluminum shielding box (8), and the first aluminum shielding box is connected with a front amplification circuit board (6) arranged in the first aluminum shielding box (7) through the first pin (11); the preamplification circuit board (6) is fixed on four first mounting holes (10) positioned at four corners of the first aluminum shielding box (7);

a third aluminum shielding box (9) is fixed on the other side of the printed board (5) through a second mounting hole (14), a third semiconductor detector (3) is fixedly mounted in the third aluminum shielding box (9), and a second pin (12) is arranged on the third aluminum shielding box (9) and connected with a preamplification circuit board (6) arranged in the first aluminum shielding box (7);

the first semiconductor detector (1), the second semiconductor detector (2) and the third semiconductor detector (3) are respectively connected with the FGPA processing circuit through respective detection branches, and the device to be tested (5) is connected with the FPGA processing circuit through a monitoring circuit arranged on the device to be tested.

2. The spaceborne single particle monitor according to claim 1, wherein the preamplification circuit board (6) is respectively provided with a first preamplifier, a second preamplifier and a third preamplifier, which are respectively and correspondingly connected with the first semiconductor detector (1), the second semiconductor detector (2) and the third semiconductor detector (3), and respectively amplify and convert the charge signal collected by the first semiconductor detector (1), the charge signal collected by the second semiconductor detector (2) and the charge signal collected by the third semiconductor detector (3) to obtain corresponding amplified and converted voltage pulse signals.

3. The on-board single particle monitor according to claim 2, wherein the first semiconductor detector (1) is connected with a first preamplifier, a shaping circuit, a main amplifier, a peak value holder and an ADC (analog to digital converter) acquisition circuit arranged on a corresponding detection branch in sequence;

the second semiconductor detector (2) is connected with a first preamplifier, a forming circuit, a main amplifier, a peak value retainer and an ADC acquisition circuit which are arranged on a detection branch corresponding to the second semiconductor detector in sequence;

the third semiconductor detector (3) is connected with a first preamplifier, a forming circuit, a main amplifier, a peak value retainer and an ADC acquisition circuit which are arranged on a detection branch corresponding to the third semiconductor detector in sequence;

the three detection branches are all connected with an FPGA processing circuit, and the FPGA processing circuit is connected with a satellite through an interface circuit and a satellite interface.

4. The on-board single event monitor of claim 3, wherein a noise detection circuit is added between the main amplifier and the peak value holder in each detection branch for performing amplification processing and analog-to-digital conversion according to the received noise signal, and inputting the obtained digital signal to the FPGA processing circuit.

5. The on-board single event monitor of claim 4, wherein the noise detection circuit comprises: an amplifier and an ADC acquisition circuit;

the output end of the amplifier is connected with the input end of the ADC acquisition circuit, and the output end of the ADC acquisition circuit is connected with the input end of the FPGA processing circuit.

6. The on-board single particle monitor of claim 1, wherein the FPGA processing circuit comprises:

the first data receiving module is used for receiving the converted digital signals obtained by each semiconductor detector through the corresponding detection branch;

the first data processing module is used for carrying out amplitude analysis and data processing according to the obtained three converted digital signals to obtain an LET spectrum of the space charged particles;

the second data receiving module is used for receiving overturning information generated after the high-energy charged particles in the space are incident to a sensitive area of the SRAM chip;

the second data processing module is used for carrying out data processing on the overturning information to obtain the single-particle overturning times of the device to be tested;

the third data receiving module is used for receiving the digital signal output by the noise detection circuit;

and the third data processing module is used for processing according to the received digital signal output by the noise detection circuit and detecting the working condition of each detection branch.

7. The on-board single particle monitor of claim 1, further comprising: and the output interface circuit is used for carrying out data communication with the satellite bus.

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