CN111755511B - VDMOSFET and its preparation method and semiconductor device - Google Patents

Abstract

The present application provides a VDMOSFET, a preparation method thereof, and a semiconductor device. The VDMOSFET includes a first conductivity type heavily doped substrate, a first conductivity type lightly doped drift layer, a second conductivity type lightly doped well region, and a second conductivity type lightly doped well region. A heavily doped contact region, a heavily doped source region of the first conductivity type, a lightly doped region of the second conductivity type, a lightly doped region of the first conductivity type, a gate oxide layer, a gate electrode, a source electrode and a drain electrode. The second conductive type lightly doped region and the first conductive type lightly doped region are introduced into the VDMOSFET to form alternate PN columns (super junction structure), which can greatly reduce the on-resistance without reducing the breakdown voltage. At the same time, the gate oxide layer can be effectively protected from being broken down, and the reliability of the device can be improved.

Description

VDMOSFET and its preparation method and semiconductor device

technical field

The present application relates to the field of semiconductor technology, and in particular, to a VDMOSFET, a preparation method thereof, and a semiconductor device.

Background technique

SIC MOSFET has the advantages of high input impedance, high switching speed stability, and low on-resistance, and is currently the most concerned SIC switching device. Among SICMOSFETs, VDMOSFET (Vertical Conduction DoubleScattering Metal Oxide Semiconductor) is the fastest developing power device; it has unique high input impedance, low driving power, high switching speed, superior frequency characteristics, low noise and good thermal performance. It has the characteristics of stability, radiation resistance and simple manufacturing process; it is widely used in various fields such as AC drive, variable frequency power supply, switching regulated power supply, etc., and has achieved good results.

In the related art, the VDMOSFET structure is shown in FIG. 1 : it includes an N+ substrate layer 10, an N-type drift region 20, a P- well region (pwell) 30, a P+ contact region 40, an N+ source region 50, a source electrode 60, a gate electrode 70 , drain 80 , JFET region 90 , gate oxide 100 . The lateral channel device structure has the following disadvantages: First, there is a JFET region, which will increase the on-resistance of the device (ie, the on-state loss during application). The method of reducing the resistance of the JFET region in the related art is to increase the distance between pwells or N-injection is performed in the JFET region, but it is easy to cause short channel effect (the device is turned on in advance) and the carrier concentration under the gate oxide layer is large, so that the gate oxide layer bears a large voltage, which will lead to early breakdown of the gate oxide, The withstand voltage of the device is reduced; second, the on-resistance of the device is inversely proportional to the withstand voltage value. If the on-resistance is to be reduced by increasing the concentration of the N-drift layer 20, a part of the device withstand voltage will be lost, and it is impossible to reduce the on-resistance of the device. The on-resistance ensures the withstand voltage of the device; thirdly, due to the existence of C element, the interface state density of SiC/ _SiO2 material is about three times that of Si, and the high interface state density leads to low channel mobility; fourthly, due to The higher interface state density of SiC/SiO ₂ material, the gate oxide layer is easier to break down earlier than the silicon device, so that the actual withstand voltage value of the device is much lower than the calculated value.

Therefore, the current VDMOSFET related technology still needs to be improved.

SUMMARY OF THE INVENTION

The present application aims to solve one of the technical problems in the related art at least to a certain extent. Therefore, the purpose of the present application is to provide a VDMOSFET that can effectively reduce the on-resistance of the device while improving the withstand voltage capability of the device, effectively improving the electron mobility in the channel, or effectively protecting the gate oxide layer from breakdown.

In one aspect of the present application, the present application provides a VDMOSFET. According to an embodiment of the present application, the VDMOSFET includes: a heavily doped substrate of a first conductivity type; a lightly doped drift layer of a first conductivity type, and the first conductivity type lightly doped drift layer is disposed on the first conductivity type on the upper surface of the heavily doped substrate; a functional doped layer, the functional doped layer is disposed on the upper surface of the first conductive type lightly doped drift layer, and includes a first doped region and a A second doped region outside the doped region, wherein the second doped region includes a second conductivity type lightly doped well region, a second conductivity type heavily doped contact region and a first conductivity type heavily doped source electrode region, the second conductive type heavily doped contact region and the first conductive type heavily doped source region are arranged on the part of the upper surface of the second conductive type lightly doped well region located on the outer side, the The second conductivity type heavily doped contact region is located outside the first conductivity type heavily doped source region, and the upper surface of the second conductivity type heavily doped contact region, the first conductivity type heavily doped The upper surface of the source region is flush with the upper surface of the lightly doped well region of the second conductivity type not covered by the heavily doped contact region of the second conductivity type and the heavily doped source region of the first conductivity type ; The first doped region includes a second conductive type lightly doped region and a first conductive type lightly doped region, and the first conductive type lightly doped region is disposed in the second conductive type lightly doped region Outside; gate oxide layer, the gate oxide layer is arranged on the upper surface of the functional doping layer, and covers the upper surface of the first doping region, and the lightly doped well region of the second conductivity type is not The second conductive type heavily doped contact region and the upper surface covered by the first conductive type heavily doped source region and part of the upper surface gate of the first conductive type heavily doped source region, the a gate electrode is arranged on the upper surface of the gate oxide layer; a source electrode is arranged on the upper surface of the functional doped layer and covers the upper surface of the second conductive type heavily doped contact region and a part of the upper surface of the heavily doped source region of the second conductivity type; a drain, which is disposed on the lower surface of the substrate. The second conductive type lightly doped region and the first conductive type lightly doped region are introduced into the VDMOSFET to form alternate PN columns (super junction structure), when the device is in reverse bias, the PN columns in the super junction appear In the reverse bias phenomenon, the charges of the two columns compensate each other, and a depletion layer is formed between them. At this time, the excess carriers are laterally depleted, and a part of the reverse bias voltage is borne by the depletion region (equivalent to resistance), which can be The withstand voltage of the device is greatly improved, and since the excess carriers can be laterally depleted at this time, the doping concentration of the device drift layer can be greatly increased, which greatly reduces the on-resistance without reducing the breakdown voltage. A depletion layer (resistance region) can be formed under the gate oxide layer to bear the reverse voltage, which can effectively protect the gate oxide layer from being broken down, thereby effectively reducing the on-resistance of the device and improving the withstand voltage of the device, and can improve the device reliability. Further, by adjusting the width of the PN column and the doping concentration, the superjunction can reach the optimal state, that is, the charge is completely depleted just before the superjunction enters the breakdown, so that the device has better performance. Withstand voltage performance, anti-breakdown performance and on-resistance, greatly improve the performance and reliability.

In another aspect of the present application, the present application provides a method of making the aforementioned VDMOSFET. According to an embodiment of the present application, the method includes: forming a lightly doped layer of a first conductivity type on an upper surface of a heavily doped substrate of a first conductivity type; performing ion implantation on the lightly doped layer of the first conductivity type, forming a functional doped layer and a first conductive type lightly doped drift layer, the functional doped layer is disposed on the upper surface of the first conductive type lightly doped drift layer; on a part of the upper surface of the functional doped layer forming a gate oxide layer on the upper surface of the gate oxide layer; forming a gate electrode on the upper surface of the gate oxide layer; forming a source electrode on a part of the upper surface of the functional doping layer; forming a drain electrode on the lower surface of the substrate; wherein , the step of forming the functional doped layer includes: performing a first ion implantation on the first conductivity type lightly doped layer to form a second conductivity type lightly doped well region; lightly doping the first conductivity type performing a second ion implantation on the first conductivity type lightly doped layer to form a lightly doped region of the second conductivity type; performing a third ion implantation on the first conductivity type lightly doped layer to form a lightly doped region of the first conductivity type; The fourth ion implantation is performed on the lightly doped layer of the first conductivity type to form a heavily doped source region of the first conductivity type; the fifth ion implantation is performed on the lightly doped layer of the first conductivity type to form a heavily doped contact region of the second conductivity type ; annealing the product obtained after the fifth ion implantation. The method can quickly and effectively prepare and obtain the VDMOSFET mentioned above, with simple steps, convenient operation, and easy realization of industrialized production.

In yet another aspect of the present application, the present application provides a semiconductor device. According to an embodiment of the present application, the semiconductor device includes the aforementioned VDMOSFET. The semiconductor device includes all the features and advantages of the VDMOSFET described above, and will not be repeated here.

Description of drawings

FIG. 1 is a schematic cross-sectional structure diagram of a VDMOSFET in the related art.

FIG. 2 is a schematic cross-sectional structure diagram of a VDMOSFET according to an embodiment of the present application.

FIG. 3 is a schematic cross-sectional structure diagram of a VDMOSFET according to another embodiment of the present application.

FIG. 4 is a schematic flowchart of a method for manufacturing a VDMOSFET according to an embodiment of the present application.

FIG. 5 is a partial cross-sectional structural schematic diagram of a VDMOSFET according to another embodiment of the present application.

FIG. 6 is a partial cross-sectional structural schematic diagram of a VDMOSFET according to another embodiment of the present application.

FIG. 7 is a partial cross-sectional structural schematic diagram of a VDMOSFET according to another embodiment of the present application.

Detailed ways

Embodiments of the present application are described in detail below. The embodiments described below are exemplary, only used to explain the present application, and should not be construed as a limitation to the present application. If no specific technique or condition is indicated in the examples, the technique or condition described in the literature in the field or the product specification is used. The reagents or instruments used without the manufacturer's indication are conventional products that can be purchased in the market.

In one aspect of the present application, the present application provides a VDMOSFET. According to an embodiment of the present application, referring to FIG. 2 , the VDMOSFET includes: a first conductivity type heavily doped substrate 1 ; a first conductivity type lightly doped drift layer 2 , the first conductivity type lightly doped drift layer 2 is provided On the upper surface of the first conductive type heavily doped substrate 1; a functional doped layer 3, the functional doped layer 3 is disposed on the upper surface of the first conductive type lightly doped drift layer 2, and It includes a first doped region 32 and a second doped region 34 located outside the first doped region, wherein the second doped region 34 includes a second conductive type lightly doped well region 342, a second conductive Type heavily doped contact region 344 and first conductivity type heavily doped source region 346, the second conductivity type heavily doped contact region 344 and the first conductivity type heavily doped source region 346 are disposed in the The second conductivity type lightly doped well region 342 is located on a part of the upper surface of the outer side, the second conductivity type heavily doped contact region 344 is located on the outer side of the first conductivity type heavily doped source region 346 , and the The upper surface of the second conductivity type heavily doped contact region 344 , the upper surface of the first conductivity type heavily doped source region 346 and the second conductivity type lightly doped well region 342 are not covered by the second conductivity type The heavily doped contact region 344 of the first conductivity type is flush with the upper surface covered by the heavily doped source region 346 of the first conductivity type; the first doped region 32 includes the lightly doped region 322 of the second conductivity type and the first conductivity type Type lightly doped region 324, the first conductivity type lightly doped region 324 is arranged on the outside of the second conductivity type lightly doped region 322; gate oxide layer 4, the gate oxide layer 4 is arranged on the function On the upper surface of the doped layer 3 and covering the upper surface of the first doped region 32, the second conductivity type lightly doped well region 342 is not heavily doped by the second conductivity type contact region 344 and The upper surface covered by the first conductive type heavily doped source region 346 and part of the upper surface gate 5 of the first conductive type heavily doped source region 346, the gate 5 is arranged on the gate oxide On the upper surface of the layer 4; the source electrode 6, the source electrode 6 is arranged on the upper surface of the functional doped layer 3, and covers the upper surface and part of the second conductive type heavily doped contact region 344. The upper surface of the second conductive type heavily doped source region 346 ; the drain 7 , the drain 7 is disposed on the lower surface of the substrate 1 . The second conductive type lightly doped region 322 and the first conductive type lightly doped region 324 are introduced into the VDMOSFET to form alternate PN columns (super junction structure), when the device is in reverse bias, the PN in the super junction The column is reverse biased, the charges of the two columns compensate each other, and a depletion layer is formed between them. At this time, the excess carriers are laterally depleted, and a part of the reverse bias voltage is borne by the depletion region (equivalent to resistance). , which can greatly improve the withstand voltage of the device, and because the excess carriers can be laterally depleted at this time, the doping concentration of the device drift layer can be greatly increased, which greatly reduces the on-resistance without reducing the breakdown voltage. At the same time, a depletion layer (resistance region) can be formed under the gate oxide layer to bear the reverse voltage, which can effectively protect the gate oxide layer from being broken down, thereby effectively reducing the on-resistance of the device and improving the voltage withstand capability of the device, and The reliability of the device can be improved. Further, by adjusting the width of the PN column and the doping concentration, the superjunction can reach the optimal state, that is, the charge is completely depleted just before the superjunction enters the breakdown, so that the device has better performance. Withstand voltage performance, anti-breakdown performance and on-resistance, greatly improve the performance and reliability.

It should be noted that one of the description methods "first conductivity type" and "second conductivity type" used in this document is n-type conductivity, that is, electronic conductivity, "first conductivity type" and "second conductivity type" The other one is p-type conduction, ie hole conduction. In some specific embodiments, the first conductivity type is n-type conductivity, and the second conductivity type is p-type conductivity.

According to the embodiment of the present application, the material of the heavily doped substrate 1 of the first conductivity type is doped silicon carbide (SiC), and the specific doping concentration can be flexibly selected according to actual needs. In some specific embodiments, the heavily doped substrate of the first conductivity type may be an n-type heavily doped SiC substrate, the doping impurity may be nitrogen (N) or phosphorus (P), and the specific doping concentration is 1×10 ¹⁸ cm ^-3 - 1×10 ¹⁹ cm ^-3 (specifically 1×10 ¹⁸ cm ^-3 , 2×10 ¹⁸ cm ^-3 , 3×10 ¹⁸ cm ^-3 , 4×10 ¹⁸ cm ^-3 , 5× 10 ¹⁸ cm ^-3 , 6×10 ¹⁸ cm ^-3 , 7×10 ¹⁸ cm ^-3 , 8×10 ¹⁸ cm ^-3 , 9×10 ¹⁸ cm ^-3 , 1.0×10 ¹⁹ cm ^-3 , etc.). Therefore, the concentration of heavy doping is beneficial to reduce the substrate resistance, thereby reducing the device resistance. Compared with the above concentration range, if the concentration is too low, the device resistance will be relatively large, and if the doping concentration is too high, the carrier will be The mobility is relatively decreased.

According to the embodiment of the present application, the lightly doped drift layer 2 of the first conductivity type may be doped silicon carbide, and the specific thickness and doping concentration may be flexibly selected according to actual needs. In some specific embodiments, the lightly doped drift layer of the first conductivity type is n-type doped silicon carbide, the doping impurity may be nitrogen (N) or phosphorus (P), and the thickness may be 10-12 microns (specifically, 10 microns). , 10.5 microns, 11 microns, 11.5 microns, 12 microns, etc.), the specific doping concentration can be 1.0×10 ¹⁵ cm ^-3 to 1.0×10 ¹⁶ cm ^-3 ; (specifically, such as 1.0×10 ¹⁵ cm ^-3 , 2 ×10 ¹⁵ cm ^-3 , 3×10 ¹⁵ cm ^-3 , 4×10 ¹⁵ cm ^-3 , 5×10 ¹⁵ cm ^-3 , 6×10 ¹⁵ cm ^-3 , 7×10 ¹⁵ cm ^-3 , 8×10 ¹⁵ cm ^-3 , 9×10 ¹⁵ cm ^-3 , 1.0×10 ¹⁶ cm ^-3 , etc.). Therefore, within this doping concentration range, the device can have both better resistance and withstand voltage performance, and better meet the functional requirements. Compared with the above doping concentration range, if the doping concentration is too low, the device The resistance will increase relatively; if the doping concentration is too high, the withstand voltage performance will be relatively poor.

According to the embodiment of the present application, the lightly doped well region 342 of the second conductivity type may be p-type doping, the doping impurity may be aluminum (Al) or boron (B), and the specific doping concentration may be 2.0× 10 ¹³ cm ^-3 ～3.0×10 ¹³ cm ^-3 (specifically, 2.0×10 ¹³ cm ^-3 , 2.1×10 ¹³ cm ^-3 , 2.2×10 ¹³ cm ^-3 , 2.3×10 ¹³ cm ^-3 , 2.4× 10 ¹³ cm ^-3 , 2.5×10 ¹³ cm ^-3 , 2.6×10 ¹³ cm ^-3 , 2.7×10 ¹³ cm ^-3 , 2.8×10 ¹³ cm ^-3 , 2.9×10 ¹³ cm ^-3 , 3.0×10 ¹³ cm ^-3 , etc.). Therefore, within the above-mentioned doping concentration range, the device can have a suitable turn-on voltage. Compared with the above-mentioned doping concentration range, if the doping concentration is too high, the inversion layer cannot be formed, and the device is difficult to turn on; If the concentration is too low, the turn-on voltage is relatively low, which may cause the device to be turned on without applying voltage to the gate, thereby causing the device to fail.

According to the embodiment of the present application, the second conductive type heavily doped contact region 344 may be p-type doped, the doping impurity may be aluminum (Al) or boron (B), and the specific doping concentration may be 1.0× 10 ¹⁶ cm ^-3 ～2.0×10 ¹⁶ cm ^-3 (1.0×10 ¹⁶ cm ^-3 , 1.1×10 ¹⁶ cm ^-3 , 1.2×10 ¹⁶ cm ^-3 , 1.3×10 ¹⁶ cm ^-3 , 1.4×10 ¹⁶ cm ^-3 , 1.5×10 ¹⁶ cm ^-3 , 1.6×10 ¹⁶ cm ^-3 , 1.7×10 ¹⁶ cm ^-3 , 1.8×10 ¹⁶ cm ^-3 , 1.9×10 ¹⁶ cm ^-3 , 2.0×10 ¹⁶ cm ^{-3 3} and so on). In this way, it can ensure that the second conductive type heavily doped contact region forms a good ohmic contact with the source electrode without increasing the on-resistance of the device; compared with the above-mentioned doping concentration range, if the concentration is too high, it will relatively increase Large device on-resistance, if the concentration is too low, ohmic contact may not be formed, affecting the performance of the device.

According to the embodiment of the present application, the heavily doped source region of the first conductivity type may be n-type doping, the doping impurity may be nitrogen (N) or phosphorus (P), and the specific doping concentration may be 2.0×10 ¹⁵ cm ^-3 ～4.0×10 ¹⁵ cm ^-3 (specifically, 2.0×10 ¹⁵ cm ^-3 , 2.1×10 ¹⁵ cm ^-3 , 2.2×10 ¹⁵ cm ^-3 , 2.3×10 ¹⁵ cm ^-3 , 2.4×10 ¹⁵ cm ^-3 , 2.5 x 10 ¹⁵ cm ^-3 , 2.6 x 10 ¹⁵ cm ^-3 , 2.7 x 10 ¹⁵ cm ^-3 , 2.8 x 10 ¹⁵ cm ^-3 , 2.9 x 10 ¹⁵ cm ^-3 , 3.0 x 10 ¹⁵ cm ^-3 , 3.1×10 ¹⁵ cm ^-3 , 3.2×10 ¹⁵ cm ^-3 , 3.3×10 ¹⁵ cm ^-3 , 3.4×10 ¹⁵ cm ^-3 , 3.5×10 ¹⁵ cm ^-3 , 3.6×10 ¹⁵ cm ^-3 , 3.7×10 ¹⁵ cm ⁻³ , 3.8×10 ¹⁵ cm ⁻³ , 3.9×10 ¹⁵ cm ⁻³ , 4.0×10 ¹⁵ cm ⁻³ , etc.). Therefore, the heavily doped source region of the first conductivity type, which is an important region for current flow, can be made to have a sufficiently low resistance and a better flow channel. Compared with the above-mentioned doping concentration range, if the doping concentration is too low, It is beneficial to current flow; if the doping concentration is too high, the device performance will not be significantly improved, but the cost will be relatively increased.

According to the embodiment of the present application, the lightly doped region of the second conductivity type may be p-type doped, the specific doping impurity may be aluminum (Al) or boron (B), and the specific doping concentration may be 2×10 ¹³ cm ^-3 ～3×10 ¹³ cm ^-3 (specifically, 2×10 ¹³ cm ^-3 , 2.1×10 ¹³ cm ^-3 , 2.2×10 ¹³ cm ^-3 , 2.3×10 ¹³ cm ^-3 , 2.4×10 ¹³ cm ^-3 , 2.5×10 ¹³ cm ^-3 , 2.6×10 ¹³ cm ^-3 , 2.7×10 ¹³ cm ^-3 , 2.8×10 ¹³ cm ^-3 , 2.9×10 ¹³ cm ^-3 , 3.0×10 ¹³ cm ^{-3 3} , etc.); and the first conductive type lightly doped region can be n-type doped, the doping impurity is nitrogen (N) or phosphorus (P), and the specific doping concentration can be 1.5×10 ¹³ cm ^{− 3} to 2.5×10 ¹³ cm ^-3 (specifically, 1.5×10 ¹³ cm ^-3 , 1.6×10 ¹³ cm ^-3 , 1.7×10 ¹³ cm ^-3 , 1.8×10 ¹³ cm ^-3 , 1.9×10 ¹³ cm ^-3 , ³ , 2.0×10 ¹³ cm ^-3 , 2.1×10 ¹³ cm ^-3 , 2.2×10 ¹³ cm ^-3 , 2.3×10 ¹³ cm ^-3 , 2.4×10 ¹³ cm ^-3 , 2.5×10 ¹³ cm ^-3 , etc. Wait). Therefore, the alternately arranged lightly doped regions of the second conductivity type and the lightly doped regions of the first conductivity type can form PN columns (super junction structures), and the above-mentioned doping concentration range can make the super junction structure reach the optimum state, that is, in the Just before the superjunction enters the breakdown, the charge is completely depleted, so the excess carriers are completely depleted laterally, and a part of the reverse bias voltage is borne by the depletion region, which can greatly improve the withstand voltage of the device, and because of this When the excess carriers can be depleted laterally, the doping concentration of the drift layer can be greatly increased, which greatly reduces the on-resistance without causing the breakdown voltage to drop. voltage, so as to effectively protect the gate oxide layer from being broken down and improve the reliability of the device.

According to an embodiment of the present application, referring to FIG. 3 , the functional doping layer 3 further includes: an overlapping region 36 , and the overlapping region 36 is disposed between the first doping region 32 and the second doping region 34 In between, the first doped region 32 and the second doped region 34 are formed by overlapping. Therefore, the first doping region 32 and the second doping region 34 are partially overlapped, and the carrier injection in the channel region can effectively increase the carrier concentration, thereby improving the channel mobility and improving the performance of the device. .

According to the embodiment of the present application, the width W1 of the overlapping region 36 may be 0.5-0.8 microns (specifically, such as 0.5 microns, 0.55 microns, 0.6 microns, 0.65 microns, 0.7 microns, 0.75 microns, 0.8 microns, etc.). Therefore, within this width range, the device can have suitable turn-on voltage and loss at the same time. Compared with the above width range, if the width is too small, the device may be turned on in advance, affecting the basic switching function of the device; if the width is too small If it is large, the turn-on voltage will increase relatively, and the loss will increase relatively.

According to the embodiment of the present application, when the device structure does not include the overlapping region, the portion between the first conductive type heavily doped source region 346 and the first doped region 32 constitutes the channel of the VDMOSFET, and when the device structure includes the overlapping region 36, the overlapping region 36 constitutes the channel of the VDMOSFET. According to some embodiments of the present application, the channel length L may be 0.5-0.8 microns (specifically, such as 0.5 microns, 0.55 microns, 0.6 microns, 0.65 microns, 0.7 microns, 0.75 microns, 0.8 microns, etc.). As a result, the channel length in the device is suitable, which will not cause a short channel effect (the device is turned on in advance), and the carrier concentration under the gate oxide layer will not be too large, so that the gate oxide layer bears a large voltage, and then This leads to the early breakdown of the gate oxide layer and the reduction of the device withstand voltage.

Those skilled in the art can understand that for the VDMOSFET, when it is turned on, the JFET effect will occur, that is, the parasitic JFET (junction field effect transistor) in the VDMOSFET will generate a partial on-resistance, thereby increasing the on-resistance of the VDMOSFET. . According to the embodiments of the present application, using the above-mentioned device structure of the present application, the first doped region 32 constitutes a JFET region. In some embodiments, the width W2 of the first doped region 32 (ie, the JFET region) may be 2˜5 microns (specifically, 2 microns, 2.5 microns, 3 microns, 3.5 microns, 4 microns, 4.5 microns, 5 microns, etc.). Therefore, while ensuring the breakdown resistance of the gate oxide layer, it can have lower on-resistance. Compared with the above-mentioned width range, if the JFET width is too large, the voltage will be concentrated in the gate oxide layer area, resulting in gate oxidation. The layer breaks down in advance; if the width of the JFET is too small, the on-resistance of the device will increase relatively.

According to the embodiment of the present application, the specific material of the gate oxide layer may be silicon oxide, silicon nitride, etc., and the thickness of the gate oxide layer may be 0.05 μm. Therefore, it has higher withstand voltage performance and better breakdown resistance performance, which is beneficial to improve the use performance and reliability of the device.

In another aspect of the present application, the present application provides a method of making the aforementioned VDMOSFET. According to an embodiment of the present application, referring to FIG. 4 , the method includes the following steps:

S1 : forming the first conductive type lightly doped layer 8 on the upper surface of the first conductive type heavily doped substrate 1 , the schematic diagram of which is shown in FIG. 5 .

According to an embodiment of the present application, the first conductive type lightly doped layer may be formed by an epitaxy method. Specifically, the epitaxy method can be formed by a deposition method, for example, including but not limited to chemical vapor deposition, etc., specifically, metal organic compound chemical vapor deposition (MOCVD) and the like. Therefore, the process is mature, the operation is simple and convenient, and the doping concentration distribution in the formed lightly doped layer of the first conductivity type is more uniform, and the device performance is better.

S2: Perform ion implantation on the first conductive type lightly doped layer 8 to form a functionally doped layer 3 and a first conductive type lightly doped drift layer 2, the functionally doped layer 3 is disposed on the first conductive type lightly doped layer 2 On the upper surface of the type lightly doped drift layer 2, refer to FIG. 6 for a schematic structural diagram.

According to the embodiment of the present application, the specific steps of forming the functional doped layer 3 may include:

S21 : performing first ion implantation on the first conductive type lightly doped layer 8 to form a second conductive type lightly doped well region 342 .

According to the embodiment of the present application, the specific step of the first ion implantation may be to form a mask on the upper surface of the lightly doped layer 8 of the first conductivity type, and specifically may be to form a whole layer of photoresist in advance, and then perform the photolithography The glue is exposed and developed to obtain a patterned photoresist (ie, a mask), and then ion implantation is performed on the upper surface of the first conductive type lightly doped layer 8. The specific implantation dose, implantation energy, etc. can be determined according to the doping concentration. , the depth of the lightly doped well region of the second conductivity type, etc.

S22: Perform second ion implantation on the lightly doped layer 8 of the first conductivity type to form a lightly doped region 322 of the second conductivity type.

According to the embodiment of the present application, the specific steps of the second ion implantation may be the same as those of the first ion implantation, which will not be repeated here.

According to the embodiment of the present application, both the first ion implantation and the second ion implantation are the first conductivity type impurity implantation, and the doping concentration of the second conductivity type lightly doped region and the second conductivity type lightly doped well region may be the same , at this time, the first ion implantation and the second ion implantation can be completed by one ion implantation, that is, the second conductive type lightly doped region and the second conductive type lightly doped well region are formed by one ion implantation in one step. Thus, the preparation process can be saved and the production cost can be reduced.

S23: Perform third ion implantation on the first conductive type lightly doped layer 8 to form a first conductive type lightly doped region 324.

S24 : performing fourth ion implantation on the lightly doped layer 8 of the first conductivity type to form a heavily doped source region 346 of the first conductivity type.

S25: Perform fifth ion implantation on the lightly doped layer 8 of the first conductivity type to form a heavily doped contact region 344 of the second conductivity type.

According to the embodiment of the present application, the specific steps of the third ion implantation, the fourth ion implantation, and the fifth ion implantation may be the same as those of the first ion implantation, which will not be repeated here.

According to the embodiment of the present application, when the third ion implantation is performed, the ion implantation region may partially overlap with the lightly doped well region of the second conductivity type, thereby forming the overlapping region 36 . Refer to FIG. 7 for a schematic diagram of the structure.

S26: Perform annealing treatment on the product obtained after the fifth ion implantation.

According to embodiments of the present application, the annealing temperature may be in the range of 1600 degrees Celsius to 1700 degrees Celsius, such as 1600 degrees Celsius, 1610 degrees Celsius, 1620 degrees Celsius, 1630 degrees Celsius, 1640 degrees Celsius, 1650 degrees Celsius, 1660 degrees Celsius, 1670 degrees Celsius, 1680 degrees Celsius, 1690 degrees Celsius, 1700 degrees Celsius, etc. Therefore, the distribution of doping ions is relatively uniform, which is beneficial to improve the performance of the device.

S3 : forming a gate oxide layer 4 on a part of the upper surface of the functional doping layer 3 . Refer to FIG. 2 or FIG. 3 for a schematic view of the structure.

According to the embodiments of the present application, in this step, the gate oxide layer may be formed by thermal oxidation growth (such as dry oxidation method or wet oxidation method, etc.), PECVD, etc. The specific oxidation conditions and parameters can be used by those skilled in the art according to actual needs. Flexible options are not repeated here.

S4 : forming a gate electrode 5 on the upper surface of the gate oxide layer 4 . Refer to FIG. 2 or FIG. 3 for a schematic diagram of the structure.

According to the embodiments of the present application, in this step, the gate can be formed by a first deposition method, such as chemical vapor deposition (eg, evaporation, sputtering, etc.), physical vapor deposition, etc., and the specific parameter conditions are those skilled in the art It can be selected flexibly according to needs, and will not be repeated here.

S5 : forming a source electrode 6 on a part of the upper surface of the functional doped layer 3 , refer to FIG. 2 or FIG. 3 for a schematic view of the structure.

According to the embodiments of the present application, in this step, the source electrode may be formed by a second deposition method, such as chemical vapor deposition (eg, evaporation, sputtering, etc.), physical vapor deposition, etc., and the specific parameter conditions are those skilled in the art It can be selected flexibly according to needs, and will not be repeated here.

S6 : forming a drain 7 on the lower surface of the substrate 1 . Refer to FIG. 2 or FIG. 3 for a schematic diagram of the structure.

According to the embodiments of the present application, the drain electrode can also be formed by a second deposition method in this step, such as chemical vapor deposition (eg, evaporation, sputtering, etc.), physical vapor deposition, etc., and the specific parameter conditions are skilled in the art Personnel can choose flexibly according to their needs, and they will not be repeated here.

The method can quickly and effectively prepare and obtain the VDMOSFET mentioned above, with simple steps, convenient operation, and easy realization of industrialized production.

In yet another aspect of the present application, the present application provides a semiconductor device. According to an embodiment of the present application, the semiconductor device includes the aforementioned VDMOSFET. The semiconductor device includes all the features and advantages of the VDMOSFET described above, and will not be repeated here.

According to the embodiment of the present application, the specific type of the semiconductor device may be MOSFET (Metal-Oxide Semiconductor Field Effect Transistor), IGBT (Insulated Gate Bipolar Transistor), and those skilled in the art can understand that, in addition to the aforementioned In addition to the VDMOSFET, and including the necessary structures and components of conventional devices, they will not be repeated here.

Embodiments of the present application are described in detail below.

Example 1:

Step 1: epitaxially form an N-type SIC doped layer 8 on the heavily doped N+ type SIC substrate 1, the concentration is 1×10 ¹⁵ cm ^-3 , the thickness is 10 microns, and the doping impurity is nitrogen (N);

Step 2: Perform ion implantation on the N-type SIC doped layer 8 to form a P-well region and a P-doped region of a superjunction structure, the implantation concentration is 2×10 ¹³ cm ^-3 , and the doping impurity is aluminum (Al) ;

Step 3: perform ion implantation on the N-type SIC doped layer 8 to form an N-doped region of the superjunction structure, and the implantation concentration is 1.5×10 ¹³ cm ⁻³ ;

Step 4: Photolithography and implantation are performed on the N-type SIC doped layer 8 to form a source region and a contact region; the doping concentration of the source region is 2×10 ¹⁵ cm ⁻³ , and the doping concentration of the contact region is 1×10 ¹⁶ cm ^{− 3} ; and perform high-temperature annealing after implantation, and the annealing temperature is 1600°C;

Step 5: forming a gate oxide layer by PECVD or thermal oxygen oxidation;

Step 6: depositing to form a polysilicon gate;

Step 7: depositing metal Ni/Au to form a source electrode and a drain electrode, and a schematic diagram of the obtained VDMOSFET structure is shown in FIG. 2 .

Example 2:

Step 1: Epitaxially forming an N-type SIC doped layer 8 on the heavily doped N+ type SIC substrate 1 with a concentration of 1×10 ¹⁵ cm ^-3 , a thickness of 10 microns, and a doping impurity of nitrogen (N);

Step 2: Perform ion implantation on the N-type SIC doped layer 8 to form a P-well region and a P-doped region of a superjunction structure, the implantation concentration is 2×10 ¹³ cm ^-3 , and the doping impurity is aluminum (Al) ;

Step 3: perform ion implantation on the N-type SIC doped layer 8 to form an N-doped region of the superjunction structure, and the implantation concentration is 1.5×10 ¹³ cm ⁻³ ; the overlap width with the P-well region is 0.5 microns;

Step 4: Photolithography and implantation are performed on the N-type SIC doped layer 8 to form a source region and a contact region; the doping concentration of the source region is 2×10 ¹⁵ cm ⁻³ , and the doping concentration of the contact region is 1×10 ¹⁶ cm ^{− 3} ; and perform high-temperature annealing after implantation, and the annealing temperature is 1600°C;

Step 5: forming a gate oxide layer by PECVD or thermal oxygen oxidation;

Step 6: depositing to form a polysilicon gate;

Step 7: depositing metal Ni/Au to form the source electrode and the drain electrode, the schematic diagram of the obtained VDMOSFET structure is shown in FIG. 3 .

Example 3:

Step 1: epitaxially form an N-type SIC doping layer 8 on the heavily doped N+ type SIC substrate 1; the doping concentration is 1×10 ¹⁶ cm ^-3 , the thickness is 12 microns, and the doping impurity is nitrogen (N);

Step 2: Perform ion implantation on the N-type SIC doped layer 8 to form a P-well region and a P-doped region of a superjunction structure, the implantation concentration is 3×10 ¹³ cm ^-3 , and the doping impurity is aluminum (Al) ;

Step 3: ion implantation is performed on the N-type SIC doped layer 8 to form an N-doped region of the superjunction structure, and the implantation concentration is 2.5×10 ¹³ cm ⁻³ ; the overlap width with the P-well region is 0.5 μm respectively ;

Step 4: Photolithography and implantation are performed on the N-type SIC doped layer 8 to form a source region and a contact region. The doping concentration of the source region is 4× ^{10 15} cm ⁻³ , and the doping concentration of the contact region is 2×10 ¹⁶ cm ^{− 3} ; and perform high-temperature annealing after implantation, and the annealing temperature is 1700°C;

Step 5: forming a gate oxide layer by PECVD or thermal oxygen oxidation;

Step 6: depositing to form a polysilicon gate;

Step 7: depositing metal Ni/Au to form the source electrode and the drain electrode, the schematic diagram of the obtained VDMOSFET structure is shown in FIG. 3 .

Comparative Example 1

Step 1: epitaxially forming an N-type SIC doping layer 20 on the heavily doped N+ type SIC substrate 10; the doping concentration is 1×10 ¹⁶ cm ⁻³ , the thickness is 12 μm, and the doping impurity is nitrogen (N);

Step 2: performing ion implantation on the N-type SIC doped layer 20 to form a P-well region 30, the implantation concentration is 3×10 ¹³ cm ⁻³ , and the doping impurity is aluminum (Al);

Step 3: Photolithography and implantation are performed on the N-type SIC doped layer 20 to form a source region and a contact region, the doping concentration of the source region is 4× ^{10 15} cm ⁻³ , and the doping concentration of the contact region is 2×10 ¹⁶ cm ^{− 3} ; and perform high-temperature annealing after implantation, and the annealing temperature is 1700°C;

Step 4: forming a gate oxide layer by PECVD or thermal oxygen oxidation;

Step 5: depositing to form a polysilicon gate;

Step 6: depositing metal Ni/Au to form a source electrode and a drain electrode, and a schematic diagram of the obtained VDMOSFET structure is shown in FIG. 1 .

Performance Testing

Test the VGS, Rdson and BVdss of the silicon carbide VDMOSFET obtained in the above-mentioned embodiments and comparative examples, and the test conditions are as follows:

VGS(th) (ie, Vth): Turn-on voltage (threshold voltage), with negative temperature characteristics. Test conditions: VGS=VDS, ID=10mA;

RDS(ON) (ie Rdson): Under the conditions of a specific VGS and drain current (generally 1/2Rated ID), the resistance between the drain and the source when the MOSFET is turned on has a positive temperature characteristic. Test conditions: VGS=20V, ID=40A;

V(BR)DSS (ie BVdss): Drain-source (D-S) breakdown voltage with positive temperature characteristics. Test conditions: VGS=0, ID=100μA;

The test results are shown in Table 1.

Table 1

parameter Comparative Example 1 Example 1 Example 2 Example 3 Vth 2.75 2.53 2.38 2.47 Rdson(mR) 85 60 42 38 BVdss(V) 1380 1532 1690 1547

It can be seen from the above test results that, compared with Comparative Example 1, the turn-on voltage Vth of the devices obtained in Examples 1-3 is basically the same, but the resistance Rdson between the drain and source decreases significantly (that is, the on-resistance decreases) during turn-on, and At the same time, the breakdown voltage BVdss is significantly increased (that is, the withstand voltage is better). It can be seen that under the same process conditions, the device of the present application can improve the withstand voltage of the device and reduce the on-resistance.

In the description of the present application, it should be understood that the terms "first" and "second" are only used for description purposes, and cannot be interpreted as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, a feature defined as "first" or "second" may expressly or implicitly include one or more of that feature. In the description of the present application, "plurality" means two or more, unless otherwise expressly and specifically defined.

In the description of this specification, description with reference to the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples", etc., mean specific features described in connection with the embodiment or example , structure, material or feature is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, those skilled in the art may combine and combine the different embodiments or examples described in this specification, as well as the features of the different embodiments or examples, without conflicting each other.

Although the embodiments of the present application have been shown and described above, it should be understood that the above embodiments are exemplary and should not be construed as limitations to the present application. Embodiments are subject to variations, modifications, substitutions and variations.

Claims (11)

1. A VDMOSFET, comprising:

a first conductive type heavily doped substrate;

a first-conductivity-type lightly-doped drift layer disposed on an upper surface of the first-conductivity-type heavily-doped substrate;

a functional doping layer disposed on an upper surface of the first conductive type lightly doped drift layer and including a first doping region and a second doping region located outside the first doping region, wherein the second doping region includes a second conductive type lightly doped well region, a second conductive type heavily doped contact region and a first conductive type heavily doped source region, the second conductive type heavily doped contact region and the first conductive type heavily doped source region are disposed on a portion of an upper surface of the second conductive type lightly doped well region located outside, the second conductive type heavily doped contact region is located outside the first conductive type heavily doped source region, and the upper surface of the second conductive type contact region, the upper surface of the first conductive type heavily doped source region and the heavily doped well region of the second conductive type lightly doped well region are not covered by the second conductive type contact region and the first conductive type source region The upper surface is flush; the first doping area comprises a second conductive type lightly doped area and a first conductive type lightly doped area, and the first conductive type lightly doped area is arranged on the outer side of the second conductive type lightly doped area;

the gate oxide layer is arranged on the upper surface of the functional doping layer and covers the upper surface of the first doping region, the upper surface of the second conduction type lightly doped well region which is not covered by the second conduction type heavily doped contact region and the first conduction type heavily doped source region and the upper surface of part of the first conduction type heavily doped source region;

the grid electrode is arranged on the upper surface of the gate oxide layer;

the source electrode is arranged on the upper surface of the functional doping layer and covers the upper surface of the second conductive type heavily doped contact region and the upper surface of part of the second conductive type heavily doped source region;

a drain disposed on a lower surface of the substrate;

the doping concentration of the second conductive type lightly doped region is 2x10¹³cm^-3～3×10¹³cm^-3；

The doping concentration of the first conductive type lightly doped region is 1.5 multiplied by 10¹³cm^-3～2.5×10¹³cm^-3。

2. The VDMOSFET of claim 1, wherein the functionally doped layer further comprises:

an overlap region disposed between the first doped region and the second doped region and formed by the first doped region and the second doped region overlapping.

3. The VDMOSFET of claim 2, wherein the overlap region has a width of 0.5-0.8 μm.

4. The VDMOSFET of claim 1, wherein the channel length is between 0.5 and 0.8 microns.

5. The VDMOSFET of claim 1, wherein the first doped region has a width of 2-5 μm.

6. The VDMOSFET of claim 1, wherein at least one of the following conditions is satisfied:

the doping concentration of the first conductive type heavily doped substrate is 1.0 multiplied by 10¹⁸cm^-3～1.0×10¹⁹cm^-3；

The doping concentration of the first conductive type lightly doped drift layer is 1.0 multiplied by 10¹⁵cm^-3～1.0×10¹⁶cm^-3；

The thickness of the first conductive type lightly doped drift layer is 10-12 microns;

the doping concentration of the second conductive type lightly doped well region is 2.0 multiplied by 10¹³cm^-3～3.0×10¹³cm^-3；

The doping concentration of the second conductive type heavily doped contact region is 1.0 multiplied by 10¹⁶cm^-3～2.0×10¹⁶cm^-3；

The doping concentration of the first conductive type heavily doped source region is 2.0 multiplied by 10¹⁵cm^-3～4.0×10¹⁵cm^-3；

The thickness of the gate oxide layer is 0.045-0.08 micrometer.

7. A method of making the VDMOSFET of any one of claims 1-6, comprising:

forming a first conductive type lightly doped layer on an upper surface of the first conductive type heavily doped substrate;

performing ion implantation on the first conductive type lightly doped layer to form a functional doped layer and a first conductive type lightly doped drift layer, wherein the functional doped layer is arranged on the upper surface of the first conductive type lightly doped drift layer;

forming a gate oxide layer on a part of the upper surface of the functional doping layer;

forming a grid on the upper surface of the gate oxide layer;

forming a source electrode on a part of the upper surface of the functional doping layer;

forming a drain electrode on a lower surface of the substrate;

wherein the step of forming the functional doping layer comprises:

performing first ion implantation on the first conductive type lightly doped layer to form a second conductive type lightly doped well region;

performing second ion implantation on the first conductive type lightly doped layer to form a second conductive type lightly doped region;

performing third ion implantation on the first conductive type lightly doped layer to form a first conductive type lightly doped region;

performing fourth ion implantation on the first conductive type lightly doped layer to form a first conductive type heavily doped source region;

performing fifth ion implantation on the first conductive type lightly doped layer to form a second conductive type heavily doped contact region;

and annealing the product obtained after the fifth ion implantation.

8. The method of claim 7, wherein the first ion implantation and the second ion implantation are performed by a one-step ion implantation.

9. The method of claim 7, wherein the annealing temperature is 1600-1700 ℃.

10. The method of claim 7, wherein at least one of the following conditions is satisfied:

the gate oxide layer is formed by a PECVD or thermal oxidation method;

the gate electrode is formed by a first deposition method;

the source electrode and the drain electrode are formed by a second deposition method.

11. A semiconductor device characterized by comprising the VDMOSFET of any one of claims 1-6.

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