CN111835339B - Frequency dividing unit and multi-mode frequency divider - Google Patents
Frequency dividing unit and multi-mode frequency divider Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K21/00—Details of pulse counters or frequency dividers
- H03K21/08—Output circuits
- H03K21/10—Output circuits comprising logic circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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Abstract
The invention provides a frequency dividing unit and a multi-mode frequency divider, wherein the frequency dividing unit comprises a first latch, a second latch, a first trigger, a first NAND gate, a second NAND gate, a third NAND gate, a first inverter and a second inverter; the first latch is provided with a normal phase input end and is used for receiving a frequency division input signal, and when the frequency division input signal is a low level signal, the first latch is conducted, and the normal phase output end of the first latch starts to output the signal received by the signal input end of the first latch and is output through the first inverter so as to form a carry output signal. The multi-mode frequency divider formed by the frequency dividing unit has higher frequency dividing accuracy and frequency dividing efficiency, lower power consumption, higher processing speed, smaller delay, simple structure, extremely small occupied area and higher portability.
Description
Technical Field
The present invention relates to the field of electronic circuits, and in particular, to a frequency dividing unit and a multi-mode frequency divider.
Background
The multi-mode frequency divider is generally formed by cascading multiple stages of frequency dividing units, wherein each stage of frequency dividing unit can divide a signal, and therefore an input signal can be generated into output signals with different frequencies according to multiple frequency dividing ratios through cascading the multiple stages of frequency dividing units.
Fig. 1 is a schematic diagram of a multi-mode frequency divider provided in the related art, as shown in fig. 1, the multi-mode frequency divider includes n-stage dividing units (n is a positive integer) formed by cascading, each of the n-stage dividing units has a positive signal input terminal CI, a positive signal output terminal CO, a carry input terminal MODIN, a carry output terminal MODOUT, and a frequency division control terminal P. The CI end of each stage of frequency dividing unit behind the first stage of frequency dividing unit is connected with the CO end of the previous stage of frequency dividing unit, and the MODIN end of each stage of frequency dividing unit in front of the nth stage of frequency dividing unit is connected with the MODOUT end of the next stage of frequency dividing unit. And, the carry input MODIN of each stage of the frequency dividing unit is used for receiving the carry input signal MODIN < i >, the carry output MODOUT is used for outputting the carry output signal MODOUT < i >, the frequency dividing control terminal P is used for receiving the frequency dividing control signal P < i >, the positive signal input CI is used for receiving the frequency dividing input signal CI < i >, and the positive signal output CO is used for outputting the frequency dividing output signal CO < i >. And, each stage of frequency dividing unit divides the frequency of the frequency division input signal CI < i > received by the CI terminal based on the carry input signal MODIN < i > received by the MODIN terminal and the frequency division control signal P < i > received by the P terminal to obtain the frequency division output signal CO < i >, and outputs the frequency division output signal CO < i > through the CO terminal.
In the related art, each frequency dividing unit in the multi-mode frequency divider generally adopts a dual D flip-flop or four D latch structure, wherein fig. 2 and 3 are schematic diagrams of the dual D flip-flop and four D latches in the related art, respectively, and as shown in fig. 2, the dual D flip-flop structure includes a flip-flop DFF (a), a flip-flop DFF (b), an and gate ANDa, an and gate ANAb, a nand gate NANDa, and an inverter INVa. The four-D Latch structure includes Latch D Latch (a), latch D Latch (b), latch D Latch (c), latch D Latch (D), AND gate ANDc, AND gate ANAd, NAND gate NANDb, and inverter INVb. However, it should be noted that, when each frequency dividing unit in the multi-modulus frequency divider adopts four D-latch structures, the processing speed is slower, the delay is higher, so that the frequency dividing efficiency is lower, and the occupation area of the four D-latch structures is larger. And, when each frequency division unit in the multi-mode frequency divider adopts a dual D flip-flop structure, there is a delay between the edge of the carry output signal MODOUT < i > output by the carry output end MODOUT of each stage of frequency division unit and the rising edge of the frequency division input signal CI < i > received by the same, so that there is a glitch in the carry output signal MODOUT < i > output by the carry output end MODOUT of the other stage of frequency division unit, and the multi-mode frequency divider cannot divide the signal correctly.
Disclosure of Invention
The invention aims to provide a frequency dividing unit and a multi-mode frequency divider, which are used for solving the technical problems that the multi-mode frequency divider in the related art cannot divide frequency correctly, and has slower processing speed, higher delay, lower frequency dividing efficiency and larger occupied area.
In order to achieve the above technical problem, in a first aspect, the present invention provides a frequency dividing unit, which includes a first latch, a second latch, a first flip-flop, a first nand gate, a second nand gate, a third nand gate, a first inverter, and a second inverter;
The first input end of the second NAND gate is connected with the inverting output end of the first latch, the second input end of the second NAND gate is used for receiving a frequency division control signal, and the output end of the second NAND gate is connected with the signal input end of the second latch; the non-inverting output end of the second latch is connected with the first input end of the first NAND gate; the second input end of the first NAND gate is connected with the output end of the second inverter, and the output end of the first NAND gate is connected with the signal input end of the first trigger; the inverting output end of the first trigger is connected with the input end of the second inverter and the first input end of the third NAND gate, the inverting output end of the first trigger is used for outputting a frequency division output signal, the second input end of the third NAND gate is used for receiving a carry input signal, and the output end of the third NAND gate is connected with the signal input end of the first latch; the non-inverting output end of the first latch is connected with the input end of the first inverter and outputs a carry output signal through the output end of the first inverter;
The first latch is provided with a normal phase input end and is used for receiving a frequency division input signal, and when the frequency division input signal is a low level signal, the first latch is conducted, and the normal phase output end of the first latch starts to output the signal received by the signal input end of the first latch and is output through the first inverter so as to form a carry output signal.
Optionally, the first latch further has a negative phase input terminal for receiving an inverted signal of the frequency-divided input signal;
The second latch is provided with a positive phase input end and a negative phase input end, and the positive phase input end of the second latch is used for receiving a frequency division input signal; the negative phase input end of the second latch is used for receiving an inverted signal of the frequency division input signal, wherein when the frequency division input signal is a high level signal, the second latch is conducted;
the first flip-flop is provided with a non-inverting input terminal for receiving a frequency-divided input signal, wherein the first flip-flop is turned on when the frequency-divided input signal changes from a low level signal to a high level signal.
Optionally, the first latch includes a first clocked transmission gate, a first clocked inverter, and a third inverter;
The first input end of the first clock control transmission gate is connected with the output end of the third NAND gate, the output end of the first clock control transmission gate is respectively connected with the input end of the first inverter, the input end of the third inverter and the output end of the first clock control inverter, and the output end of the third inverter is respectively connected with the first input end of the second NAND gate and the first input end of the first clock control inverter;
The first clock transmission gate is provided with a second input end and a third input end, wherein the second input end of the first clock transmission gate is used as a positive phase input end of the first latch and is used for receiving a frequency division input signal, and the third input end of the first clock transmission gate is used as a negative phase input end of the first latch and is used for receiving an inverse signal of the frequency division input signal;
The first clocked inverter is provided with a second input end and a third input end, wherein the second input end of the first clocked inverter is used as a negative phase input end of the first latch and is used for receiving an inverted signal of a frequency division input signal, and the third input end of the first clocked inverter is used as a positive phase input end of the first latch and is used for receiving the frequency division input signal;
and when the frequency division input signal is a low level signal, the first clock control transmission gate is conducted; when the frequency division input signal is a high level signal, the first clocked inverter is turned on.
Optionally, the second latch includes a second clocked transmission gate, a second clocked inverter, and a fourth inverter;
The first input end of the second clock control transmission gate is connected with the output end of the second NAND gate, the output end of the second clock control transmission gate is respectively connected with the first input end of the first NAND gate, the input end of the fourth inverter and the output end of the second clock control inverter, and the output end of the fourth inverter is connected with the first input end of the second clock control inverter;
the second clock transmission gate is further provided with a second input end and a third input end, wherein the second input end of the second clock transmission gate is used as a negative phase input end of the second latch and is used for receiving an inverted signal of a frequency division input signal, and the third input end of the second clock transmission gate is used as a positive phase input end of the second latch and is used for receiving the frequency division input signal;
the second clocked inverter is further provided with a second input end and a third input end, wherein the second input end of the second clocked inverter is used as a positive phase input end of the second latch and is used for receiving a frequency division input signal, and the third input end of the second clocked inverter is used as a negative phase input end of the second latch and is used for receiving an inversion signal of the frequency division input signal;
And when the frequency division input signal is a high level signal, the second clock control transmission gate is conducted; when the frequency division input signal is a low level signal, the second clocked inverter is turned on.
Optionally, the frequency dividing unit further includes a first differential circuit, where the first differential circuit has a positive phase output end and a negative phase output end;
The input end of the first differential circuit is connected with the output end of the second inverter, so that the frequency division output signal provided by the inverted output end of the first trigger is received through the second inverter, the frequency division output signal is output through the positive phase output end of the first differential circuit, and the inverted signal of the frequency division output signal is output through the negative phase output end of the first differential circuit.
The invention also provides a multi-mode frequency divider, which is formed by cascading a plurality of frequency dividing units;
The frequency dividing units of the first aspect are included in other frequency dividing units of the multi-mode frequency divider except the first frequency dividing unit;
The first-stage frequency dividing unit of the multi-mode frequency divider comprises a second trigger, a third trigger, a fourth NAND gate, a fifth NAND gate, a sixth NAND gate, a fifth inverter and a sixth inverter;
The first input end of the fourth NAND gate is connected with the inverting output end of the third trigger, the second input end of the fourth NAND gate is used for receiving a frequency division control signal, and the output end of the fourth NAND gate is connected with the first input end of the sixth NAND gate; the second input end of the sixth NAND gate is connected with the output end of the fifth inverter, the output end of the sixth NAND gate is connected with the signal input end of the second trigger, the inverting output end of the second trigger is connected with the input end of the fifth inverter, the inverting output end of the second trigger is used for outputting a frequency division output signal, and the inverting output end of the second trigger is also connected with the first input end of the fifth NAND gate; the second input end of the fifth NAND gate is used for receiving a carry input signal, and the output end of the fifth NAND gate is connected with the input end of the sixth inverter so as to output a carry output signal through the sixth inverter; and the output end of the fifth NAND gate is also connected with the signal input end of the third trigger.
Optionally, the second flip-flop and the third flip-flop each have a non-inverting input terminal for receiving a frequency-divided input signal, and the second flip-flop and the third flip-flop are turned on when the frequency-divided input signal changes from a low level signal to a high level signal.
Optionally, the frequency dividing unit further includes a second differential circuit, where the second differential circuit has a positive phase output end and a negative phase output end;
The input end of the second differential circuit is connected with the output end of the fifth inverter, so that the frequency division output signal provided by the inverting output end of the second trigger is received through the fifth inverter, the frequency division output signal is output through the positive phase output end of the second differential circuit, and the inverted signal of the frequency division output signal is output through the negative phase output end of the second differential circuit.
Optionally, the first stage frequency dividing unit includes:
a positive signal input for receiving a divided input signal;
The carry input end is used for receiving a carry input signal;
the carry output end is used for outputting a carry output signal;
the frequency division control end is used for receiving the frequency division control signal;
the positive signal output end is used for outputting a frequency division output signal, and the frequency division output signal is a frequency division signal corresponding to the frequency division input signal;
the negative signal output end is used for outputting an inverted signal of the frequency division output signal;
The positive input end of the second trigger and the positive input end of the third trigger in the first-stage frequency dividing unit are used as positive signal input ends of the first-stage frequency dividing unit; the second input end of the fifth NAND gate is used as the carry input end of the first-stage frequency dividing unit; the second input end of the fourth NAND gate is used as a frequency division control end of the first-stage frequency division unit; the output end of the sixth inverter is used as the carry output end of the first-stage frequency dividing unit; the positive phase output end of the second differential circuit is used as the positive signal output end of the first-stage frequency dividing unit; the negative phase output end of the second differential circuit is used as the negative signal output end of the first-stage frequency dividing unit.
Optionally, the other frequency division unit includes:
a positive signal input for receiving a divided input signal;
a negative signal input for receiving an inverse of the divided input signal;
The carry input end is used for receiving a carry input signal;
the carry output end is used for outputting a carry output signal;
the frequency division control end is used for receiving the frequency division control signal;
the positive signal output end is used for outputting a frequency division output signal, and the frequency division output signal is a frequency division signal corresponding to the frequency division input signal;
the negative signal output end is used for outputting an inverted signal of the frequency division output signal;
The positive input end of the first latch, the positive input end of the second latch and the positive input end of the first trigger in the other frequency dividing units serve as positive signal input ends of the other frequency dividing units; the negative phase input end of the first latch and the negative phase input end of the second latch are used as negative signal input ends of the other frequency division units; the second input end of the second NAND gate is used as a frequency division control end of the other-stage frequency division unit; the second input end of the third NAND gate is used as the carry input end of the other-stage frequency dividing unit; the output end of the first inverter is used as the carry output end of the other-stage frequency dividing unit; the positive phase output end of the first differential circuit in the other frequency dividing unit is used as the positive signal output end of the other frequency dividing unit; the negative phase output end of the first differential circuit is used as the negative signal output end of the other-stage frequency dividing unit.
Optionally, the positive signal input end of the first stage frequency dividing unit is used for receiving an initial frequency dividing input signal, the positive signal input end of each stage frequency dividing unit after the first stage frequency dividing unit is connected with the positive signal output end of the previous stage frequency dividing unit, and the negative signal input end of each stage frequency dividing unit after the first stage frequency dividing unit is connected with the negative signal output end of the previous stage frequency dividing unit;
and the carry input end of the last stage frequency dividing unit is used for receiving an initial carry input signal, and the carry input end of each stage frequency dividing unit before the last stage frequency dividing unit is connected with the carry output end of the next stage frequency dividing unit.
Optionally, the divided input signal comprises a clock signal.
In summary, in the frequency dividing unit and the multi-mode frequency divider provided by the present invention, each stage of the frequency dividing unit of the multi-mode frequency divider except the first stage of the frequency dividing unit includes the frequency dividing unit provided by the present invention, that is, the first latch and the first inverter, and in the present invention, the first latch starts to be turned on and outputs the signal input by the signal input end to the first inverter when the frequency dividing input signal received by the non-inverting input end is a low level signal, so that the first inverter inverts the signal and outputs the signal as a carry output signal. Thus in the present invention, the frequency dividing unit provided in the present invention simply causes a delay between the edges (e.g. rising and falling edges) in the carry output signal it outputs and the falling edge of the frequency divided input signal it receives, even though there is some delay in the output of the signal from the first latch. Based on the above, when the frequency dividing unit provided by the invention is used in each stage of frequency dividing units except the first stage of frequency dividing unit of the multi-mode frequency divider, no burr signal exists in carry output signals output by each stage of frequency dividing unit, the multi-mode frequency divider can be ensured to correctly divide the signals, the pulse width of the output carry output signals can be ensured, the phenomenon that the pulse width of the carry output signals is narrower is avoided, and the frequency dividing accuracy is further ensured.
In addition, the first stage frequency dividing unit of the multi-mode frequency divider comprises the second trigger and the third trigger, the second trigger and the third trigger are of a double-D trigger structure, the processing speed is high, the processing efficiency is high, and the carry output signal of the first stage frequency dividing unit cannot be input into other stage frequency dividing units, so that even if the carry output signal of the first stage frequency dividing unit is output in error due to the double-D trigger structure, the frequency dividing accuracy of other stage frequency dividing units cannot be affected.
Therefore, the multi-mode frequency divider provided by the invention ensures the frequency dividing efficiency and the frequency dividing accuracy.
Meanwhile, the triggers (namely the first trigger, the second trigger and the third trigger) in the multi-mode frequency divider provided by the invention are TSPC type D triggers, the circuit structure is simple, the delay is low, the power consumption is low, the occupied area is small, and the portability of the multi-mode frequency divider provided by the invention is high.
Drawings
FIG. 1 is a schematic diagram of a multi-modulus divider according to the related art;
FIGS. 2 and 3 are schematic diagrams of a dual D flip-flop and four D latches, respectively, according to the related art;
FIG. 4 is a timing diagram of the frequency divided input signal CI < i > received by the DFF (b) of FIG. 2, the carry output signal MODOUT < i > output, and the CI < i > and MODOUT < i > phases and subsequent signals, as desired;
FIG. 5 is a timing diagram of the frequency divided input signal CI < i > received by the DFF (b) of FIG. 2, the carry output signal MODOUT < i > output, and the CI < i > and MODOUT < i > phases and the subsequent signals;
Fig. 6 is a schematic structural diagram of a frequency dividing unit according to a first embodiment of the present invention;
fig. 7 is a schematic diagram of a first clocked inverter INVa according to a first embodiment of the present invention;
FIG. 8 is a timing diagram of the frequency division input signal CI < i >, the carry output signal MODOUT < i >, and the CI < i > and MODOUT < i > phases of the frequency division unit of FIG. 6 according to one embodiment of the present invention;
fig. 9 is a schematic diagram of a second clocked inverter INVb according to a first embodiment of the present invention;
Fig. 10 is a schematic diagram of a first flip-flop DFF1 according to an embodiment of the invention;
fig. 11 is a schematic structural diagram of a frequency dividing unit according to a second embodiment of the present invention;
fig. 12 is a schematic diagram of a multi-mode frequency divider according to an embodiment of the present invention.
Reference numerals:
D Latch 1-first Latch; d Latch 2-second Latch; DFF 1-first flip-flop; NAND 1-a first NAND gate; NAND 2-second NAND gate; NAND 3-third NAND gate; INV 1-a first inverter; INV 2-a second inverter; TG 1-first clocked transmission gate; INVa-a first clocked inverter; INV 3-third inverter; p1-a first PMOS tube; p2-a second PMOS tube; n1-a first NMOS tube; n2-a second NMOS tube; TG 2-second clocked transmission gate; INVb-a second clocked inverter; INV 4-fourth inverter; p3-a third PMOS tube; p4-a fourth PMOS tube; p5-a fifth PMOS tube; p6-sixth PMOS tube; n3-third NMOS tube; n4-a fourth NMOS tube; n5-a fifth NMOS tube; n6-sixth NMOS tube; n7-seventh NMOS tube; INV 7-seventh inverter; INV 8-eighth inverter; INV 9-ninth inverter; INV 10-tenth inverter; TG 3-third clock transmission gate; DFF 2-second flip-flop; DFF 3-third flip-flop; NAND 4-fourth NAND gate; NAND 5-fifth NAND gate; NAND 6-sixth NAND gate; INV 5-fifth inverter; INV 6-sixth inverter; INV 11-eleventh inverter; INV 12-twelfth inverter; INV 13-thirteenth inverter; INV 14-fourteenth inverter; TG 4-fourth clocked transmission gate.
Detailed Description
As described in the background art, when each frequency dividing unit in the multi-mode frequency divider adopts the dual D flip-flop structure, the carry output signal MODOUT < i > outputted from the carry output end MODOUT of each stage of frequency dividing unit generates a glitch signal. Among them, the inventors found that the cause of the glitch signal is mainly as follows:
Referring to fig. 2, a first input terminal of the and gate ANDb is used as a carry input terminal MODIN of the frequency dividing unit to receive a carry input signal MODIN < i >, a positive phase output terminal Q of the DFF (b) is used as a carry output terminal MODOUT of the frequency dividing unit to output a carry output signal MODOUT < i >, a first input terminal of the nand gate NANDa is used as a frequency dividing control terminal P of the frequency dividing unit to receive a frequency dividing control signal P < i >, positive phase input terminals CK of the DFF (a) and the DFF (b) are used as positive signal input terminals of the frequency dividing unit to receive a frequency dividing input signal CI < i >, and a positive phase output terminal Q of the DFF (a) is used as a positive signal output terminal of the frequency dividing unit to output a frequency dividing output signal CO < i >, which is a signal obtained by dividing the frequency dividing input signal CI < i >. Wherein, when the frequency-divided input signal CI < i > is changed from a low level signal to a high level signal, the DFF (a) and the DFF (b) are turned on, and the positive signal output terminals Q of the DFF (a) and the DFF (b) output the signal inputted from the signal input terminal D thereof.
Referring further to fig. 2, wherein the and gate ANDb is configured to and-process the frequency-divided output signal CO < i > and the carry input signal MODIN < i >, and input the processed signals to the signal input terminal D of the DFF (b) to be output through the DFF (b) as the carry output signal MODOUT < i >. It should be noted that DFF (b) is turned on when the divided input signal CI < i > changes from a low level signal to a high level signal, wherein, for the flip-flop and/or latch, when it is turned on, the signal output by the normal phase output terminal Q is the signal input by the signal input terminal D thereof, and when it is turned off, the normal phase output terminal Q maintains the current output signal unchanged until the next time of conduction, and the output of the signal input by the signal input terminal D thereof is restarted. It can be determined that, ideally, the time point at which the signal output by DFF (b) changes should coincide with the time point at which the positive input terminal CK thereof collects the rising edge of the divided input signal CI < i >, that is, ideally, the edge (e.g., the falling edge or the rising edge) of the carry output signal MODOUT < i > output by DFF (b) is at the same time point as the rising edge of the divided input signal CI < i > received by the positive input terminal CK thereof. In the ideal case, fig. 4 is a timing diagram of the frequency-divided input signal CI < i > received by the DFF (b) in fig. 2, a timing diagram of the carry output signal MODOUT < i > outputted, and a timing diagram of the signals CI < i > and MODOUT < i > and thereafter obtained. As shown in fig. 4, the edge of carry output signal MODOUT < i > output by DFF (b) is at the same point in time as the rising edge of divided input signal CI < i > it receives.
However, it should be noted that in practical situations, since a certain time is required for the signal to pass through the trigger, after the signal input end of the trigger receives the signal, a certain period of time is required for the signal output end to start outputting the signal. This causes a delay of D flip-flop between the edge of carry out signal MODOUT < i > output by DFF (b) and the rising edge of divided input signal CI < i > it receives. And FIG. 5 is a timing diagram of the frequency divided input signal CI < i > received by the DFF (b) of FIG. 2, a timing diagram of the carry out signal MODOUT < i > output, and a timing diagram of CI < i > and MODOUT < i > and the resulting signals after that. As shown in fig. 5, there is a delay between the edge of carry output signal MODOUT < i > output by DFF (b) and the rising edge of divided input signal CI < i > it receives. This causes carry out signals MODOUT < i > of other divided frequency dividing units to be glitched.
Specifically, as can be seen from fig. 1 and 2, the positive signal output terminal CO of each stage of frequency dividing unit after the first stage of frequency dividing unit is connected to the positive signal input terminal CI of the next stage of frequency dividing unit, and the carry input terminal MODIN of each stage of frequency dividing unit before the nth stage of frequency dividing unit is connected to the carry output terminal MODOUT of the next stage of frequency dividing unit. Thus, the frequency division input signal CI < i > of each stage of frequency division unit is substantially the frequency division output signal CO < i-1> of the previous stage of frequency division unit, and the carry output signal MODOUT < i > of each stage of frequency division unit is substantially the carry input signal MODIN < i-1> of the previous stage of frequency division unit. Based on this, when there is a delay of one flip-flop between the edge of the carry output signal MODOUT < i > outputted by the DFF (b) of each stage of the frequency dividing unit and the rising edge of the frequency dividing input signal CI < i > received by it, there is a delay of one flip-flop between the edge of the carry input signal MODIN < i-1> received by the stage of the frequency dividing unit and the rising edge of the frequency dividing output signal CO < i-1> outputted by it. At this time, referring to fig. 2, since the and gates ANDb of each stage of frequency dividing units need to perform and processing on the frequency dividing output signal CO < i > and the carry input signal MODIN < i > received by the and gates ANDb of each stage of frequency dividing units to obtain the carry output signal MODOUT < i > of the current stage of frequency dividing unit, if there is a delay between the edge of the carry input signal MODIN < i > of each stage of frequency dividing units and the rising edge of the frequency dividing output signal CO < i >, after performing and processing on MODIN < i > and CO < i >, the and processed signal has a glitch, so that the finally obtained carry output signal MODOUT < i > has a glitch. For example, fig. 4 and fig. 5 may be compared, and the presence of the glitch signal F in the phase-followed signal in fig. 5 is obvious, so that the multi-modulus divider cannot divide the signal correctly.
To solve the above problems, the present invention provides a frequency dividing unit and a multi-mode frequency divider. The frequency dividing unit and the multi-mode frequency divider according to the present invention are described in further detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
Example 1
Fig. 6 is a schematic structural diagram of a frequency dividing unit according to the first embodiment of the present invention, and as shown in fig. 6, the frequency dividing unit may include a first Latch D Latch1, a second Latch D Latch2, a first flip-flop DFF1, a first NAND gate NAND1, a second NAND gate NAND2, a third NAND gate NAND3, a first inverter INV1 and a second inverter INV2.
The first input end of the second NAND gate NAND2 is connected to the inverting output end of the first Latch D Latch1, the second input end of the second NAND gate NAND2 is used as the frequency division control end P of the frequency division unit to receive the frequency division control signal P < i >, and the output end of the second NAND gate NAND2 is connected to the signal input end of the second Latch D Latch 2. The non-inverting output terminal of the second Latch D Latch2 is connected to the first input terminal of the first NAND gate NAND 1. The second input end of the first NAND gate NAND1 is connected to the output end of the second inverter INV2, and the output end of the first NAND gate NAND1 is connected to the signal input end D of the first flip-flop DFF 1. The inverted output end-Q of the first flip-flop DFF1 is connected to the input end of the second inverter INV2 and the first input end of the third NAND gate NAND3, the inverted output end-Q of the first flip-flop DFF1 is used for outputting a frequency division output signal CO < i >, the second input end of the third NAND gate NAND3 is used as a carry input end MODIN of the frequency division unit to receive a carry input signal MODIN < i >, and the output end of the third NAND gate NAND3 is connected to the signal input end of the first Latch D Latch 1. The non-inverting output terminal of the first Latch D Latch1 is connected to the input terminal of the first inverter INV1, and outputs a carry output signal MODOUT < i > through the output terminal of the first inverter INV 1.
The first Latch D Latch1 has a non-inverting input terminal for receiving the frequency division input signal CI < i >, and when the frequency division input signal CI < i > is a low level signal, the first Latch turns on D Latch1, and the non-inverting output terminal of the first Latch D Latch1 starts to output the signal received by the signal input terminal of the first Latch D Latch1 and outputs the signal through the first inverter INV1 to form a carry output signal MODOUT < i >.
The following describes in detail the structure of each component of the frequency dividing unit in the first embodiment:
First, as for the first Latch D Latch1, referring to fig. 6, the first Latch D Latch1 may include a first clocked transmission gate TG1, a first clocked inverter INVa, and a third inverter INV3.
The first input end of the first clocked transmission gate TG1 is used as a signal input end of the first Latch D Latch1 and is connected with an output end of the third NAND gate NAND3, the output end of the first clocked transmission gate TG1 is used as a normal phase output end of the first Latch D Latch1 and is connected with an input end of the first inverter INV1, meanwhile, the output end of the first clocked transmission gate TG1 is also respectively connected with an input end of the third inverter INV3 and an output end of the first clocked inverter INVa, the output end of the third inverter INV3 is used as an inverting output end of the first Latch D Latch1 and is connected with a first input end of the second NAND gate NAND2, and the output end of the third inverter INV3 is also connected with a first input end of the first clocked inverter INVa.
The first clock transmission gate TG1 further has a second input terminal CI and a third input terminal CIB, where the second input terminal CI of the first clock transmission gate TG1 is used as a positive input terminal of the first Latch D Latch1 and is used for receiving a frequency division input signal CI < i >, the frequency division input signal CI < i > may be, for example, a clock signal, and the third input terminal CIB of the first clock transmission gate TG1 is used as a negative input terminal of the first Latch D Latch1 and is used for receiving an inverse signal CIB < i > of the frequency division input signal.
And, for the first clock transmission gate TG1, when the frequency division input signal CI < i > is at a low level, the first clock transmission gate TG1 is turned on, and the output terminal thereof outputs the signal inputted from the first input terminal thereof; when the frequency-divided input signal CI < i > is high, the first clocked transmission gate TG1 is turned off.
The first clocked inverter INVa also has a second input terminal CIB and a third input terminal CI, the second input terminal CIB of the first clocked inverter INVa is used as a negative phase input terminal of the first Latch D Latch1 for receiving the inverted signal CIB < i > of the frequency-divided input signal, and the third input terminal CI of the first clocked inverter INVa is used as a positive phase input terminal of the first Latch D Latch1 for receiving the frequency-divided input signal CI < i >.
Specifically, fig. 7 is a schematic structural diagram of a first clocked inverter INVa according to a first embodiment of the present invention, as shown in fig. 7, the first clocked inverter INVa may specifically include: the first PMOS tube P1, the second PMOS tube P2, the first NMOS tube N1 and the second NMOS tube N2.
And, as shown in fig. 6 and 7, the gate of the first PMOS transistor P1 and the gate of the second NMOS transistor are used as the first input end of the first clocked inverter INVa, and are connected to the output end of the third NAND gate NAND3, the source of the first PMOS transistor P1 is connected to the voltage source VDD, the drain of the first PMOS transistor P1 is connected to the source of the second PMOS transistor, the drain of the second PMOS transistor is connected to the first node a, the first node a is used as the output end of the first clocked inverter INVa and is connected to the input end of the third inverter INV3, the first node a is further connected to the drain of the first NMOS transistor, the source of the first NMOS transistor is connected to the drain of the second NMOS transistor, and the source of the second NMOS transistor is grounded. The gate of the second PMOS transistor is used as the second input terminal CIB of the first clocked inverter INVa for receiving the inverted signal CIB < i > of the frequency-divided input signal, and the gate of the first NMOS transistor is used as the third input terminal CI of the first clocked inverter INVa for receiving the frequency-divided input signal CI < i >.
Wherein, for the first clocked inverter INVa, when the divided input signal CI < i > is a low level signal, the first clocked inverter INVa is turned off. When the frequency-divided input signal CI < i > is a high level signal, the first clocked inverter INVa is turned off and implements an inverting function, and the specific principle thereof is as follows:
When the frequency division input signal CI < i > is at a low level, the inversion signal CIB < i > of the frequency division input signal is at a high level, the gate of the first NMOS transistor N1 receives the low level signal, the gate of the second PMOS transistor P2 receives the high level signal, both the second PMOS transistor P2 and the first NMOS transistor N1 are turned off, and the first clocked inverter INVa is turned off.
When the frequency division input signal CI < i > is at a high level, the inversion signal CIB < i > of the frequency division input signal is at a low level, the gate of the first NMOS transistor N1 receives the high level signal, the gate of the second PMOS transistor P2 receives the low level signal, and both the second PMOS transistor P2 and the first NMOS transistor N1 are turned on. At this time, if the first input end of the first clocked inverter INVa (i.e., the gate of the first PMOS transistor P1 and the gate of the second NMOS transistor N2) receives the high-level signal, the first PMOS transistor P1 is turned off, and the second NMOS transistor N2 is turned on, the first NMOS transistor N1 and the second NMOS transistor N2 pull down the potential of the first node a to the low level, so that the output end of the first clocked inverter INVa (i.e., the first node a) outputs the low-level signal opposite to the high-level signal input by the first input end thereof. And if the first input end of the first clocked inverter INVa receives the low-level signal, the first PMOS transistor P1 is turned on, and the second NMOS transistor N2 is turned off, the first PMOS transistor P1 and the second PMOS transistor P2 pull up the potential of the first node a to a high level, so that the output end of the first clocked inverter INVa outputs a high-level signal that is inverted from the low-level signal input by the first input end thereof, and the first clocked inverter INVa realizes an inverting function.
As can be seen from the above description and fig. 6, in the first embodiment, when the frequency division input signal CI < i > is a low level signal, the first clocked transmission gate TG1 in the first Latch D Latch1 is turned on, the first clocked inverter INVa is turned off, and at this time, the signal output from the output end of the third NAND gate NAND3 passes through the first clocked transmission gate TG1 and then is output to the first inverter INV1 through the non-inverting output end of the first Latch D Latch1 (i.e. the output end of the first clocked transmission gate TG 1), so that the first inverter INV1 inverts the signal output from the non-inverting output end of the first Latch D Latch1 and outputs the signal as the carry output signal MODOUT < i >; meanwhile, the signal output by the output end of the third NAND gate NAND3 is inverted by the third inverter INV3 after passing through the first clocked transmission gate TG1, and then is output by the inverted output end of the first Latch D Latch1 (i.e. the output end of the third inverter INV 3). Thus, when the frequency-divided input signal CI < i > is a low level signal, the inverting output terminal of the first Latch D Latch1 outputs an inverted signal of the signal received by the first input terminal thereof (i.e., the first input terminal of the first clocked transmission gate TG 1), and the non-inverting output terminal of the first Latch D Latch1 outputs the signal received by the first input terminal thereof.
And, when the frequency division input signal CI < i > is at a low level, the signal output by the output terminal of the third NAND gate NAND3 is further transmitted to the input terminal of the first clocked inverter INVa through the first clocked transmission gate TG1 and the third inverter INV3, and at this time, in view of the first clocked inverter INVa being turned off, the signal output by the third NAND gate NAND3 is latched to the input terminal of the first clocked inverter INVa.
Then, when the frequency-divided input signal is a high level signal, the first clocked transmission gate TG1 in the first Latch D Latch1 is turned off, the first clocked inverter INVa is turned on, and at this time, the first clocked inverter INVa outputs the signal latched by its input end to the input end of the first inverter INV1 and the input end of the third inverter INV3, so that the non-inverting output end and the inverting output end of the first Latch D Latch1 will maintain outputting the signal output when they are turned on immediately before.
That is, in this embodiment, when the divided input signal CI < i > received by the non-inverting input terminal of the first Latch D Latch1 is a low level signal, the non-inverting output terminal thereof outputs the signal input by the signal input terminal thereof, and outputs the signal as the carry output signal through the first inverter INV1, and the inverting output terminal thereof outputs the inverted signal of the signal input by the signal input terminal thereof. And when the frequency division input signal CI < i > received by the non-inverting input terminal of the first Latch D Latch1 is a high level signal, the first Latch D Latch1 is cut off, and the current signal output is maintained.
Based on this, since the first Latch D Latch1 is turned on when the divided input signal CI < i > received at the non-inverting input terminal thereof is a low level signal, even when there is a delay in the output signal of the first Latch D Latch1 in the actual situation, in the first embodiment, the edge (i.e., the rising edge and the falling edge) of the signal output at the non-inverting output terminal of the first Latch D Latch1 is delayed from the falling edge of the divided input signal CI < i > received by the first Latch D Latch1, in other words, there is a delay of one Latch between the edge of the carry output signal MODOUT < i > of the dividing unit and the falling edge of the divided input signal CI < i > received by the dividing unit. Fig. 8 is a timing chart of the frequency-divided input signal CI < i >, a timing chart of the carry-out signal MODOUT < i >, and timing charts of CI < i > and MODOUT < i > and signals obtained after the phase-shifting of the frequency-divided input signal CI < i > of the frequency-dividing unit in fig. 6 according to an embodiment of the present invention.
Further, referring to fig. 6, the second Latch D Latch2 includes a second clocked transmission gate TG2, a second clocked inverter INVb, and a fourth inverter INV4.
The first input end of the second clocked transmission gate TG2 is used as a signal input end of the second Latch D Latch2, and is connected to an output end of the second NAND gate NAND2, the output end of the second clocked transmission gate TG2 is used as a normal phase output end of the second Latch D Latch2, and is connected to a first input end of the first NAND gate NAND1, and at the same time, the output end of the second clocked transmission gate TG2 is also connected to an input end of the fourth inverter INV4 and an output end of the second clocked inverter INVb, and an output end of the fourth inverter INV4 is connected to a first input end of the second clocked inverter INVb.
The second clock transmission gate TG2 further has a second input terminal CIB and a third input terminal CI, wherein the second input terminal CIB of the second clock transmission gate TG2 is used as a negative phase input terminal of the second Latch D Latch2 and is used for receiving a frequency division input signal inverted signal CIB < i >, and the third input terminal CI of the second clock transmission gate TG2 is used as a positive phase input terminal of the second Latch D Latch2 and is used for receiving a frequency division input signal CI < i >.
And when the frequency division input signal CI < i > is a high level signal, the second clock control transmission gate TG2 is turned on, the output end outputs the signal input by the first input end, and when the frequency division input signal CI < i > is a low level signal, the second clock control transmission gate TG2 is turned off.
Further, the second clocked inverter INVb is also provided with a second input terminal CI and a third input terminal CIB, the second input terminal CI of the second clocked inverter INVb is used as a positive input terminal of the second Latch D Latch2 for receiving the frequency division input signal CI < i >, and the third input terminal CIB of the second clocked inverter INVb is used as a negative input terminal of the second Latch D Latch2 for receiving the inverse signal CIB < i >.
Specifically, fig. 9 is a schematic structural diagram of a second clocked inverter INVb according to the first embodiment of the present invention, and referring to fig. 7 and fig. 9, the second clocked inverter INVb has the same structure as the first clocked inverter INVa, and includes: the first PMOS tube P1, the second PMOS tube P2, the first NMOS tube N1 and the second NMOS tube N2 are connected in the same connection relationship.
However, it should be emphasized that, unlike the first clocked inverter INVa, in the second clocked inverter INVb, the gate of the second PMOS transistor P2 is used as the second input terminal CI of the second clocked inverter INVb for receiving the divided input signal CI < i >, the gate of the first NMOS transistor N1 is used as the third input terminal CIB of the second clocked inverter INVb for receiving the inverted signal CIB < i > of the divided input signal, and the gates of the first PMOS transistor P1 and the second NMOS transistor N2 are used as the first input terminals of the second clocked inverter INVb, and the first node a is used as the output terminal of the second clocked inverter INVb.
Also, for the second clocked inverter INVb, when the frequency-divided input signal CI < i > is a high level signal, the second clocked inverter INVb is turned off. When the frequency-divided input signal CI < i > is a low level signal, the second clocked inverter INVb is turned on and implements an inverting function.
The principle of turning on and off the second clocked inverter INVb is the same as that of the first clocked inverter INVa, and the principle of turning on and off the second clocked inverter INVb is the same as that of the first clocked inverter INVa, so the description of the principle of turning on and off the second clocked inverter INVb can be specifically referred to the above description of the principle of turning on and off the first clocked inverter INVa, and the description of this embodiment is omitted here.
Still further, the structure of the first flip-flop DFF1 in fig. 6 is specifically described, where the first flip-flop DFF1 may be, for example, a TSPC D flip-flop, and fig. 10 is a schematic structural diagram of the first flip-flop DFF1 provided in the first embodiment of the present invention, and as shown in fig. 10, the first flip-flop DFF1 may include: the third PMOS tube P3, the fourth PMOS tube P4, the fifth PMOS tube P5, the sixth PMOS tube P6, the third NMOS tube N3, the fourth NMOS tube N4, the fifth NMOS tube N5, the sixth NMOS tube N6 and the seventh NMOS tube N7.
Referring to fig. 6 and 10, the gates of the third PMOS transistor P3 and the fifth NMOS transistor N5 are used as the signal input end D of the first flip-flop DFF1, the source of the third PMOS transistor P3 is connected to the voltage source VDD, the drain of the third PMOS transistor P3 is connected to the source of the sixth PMOS transistor P6, the drain of the sixth PMOS transistor P6 is connected to the second node B, the second node B is connected to the drain of the fifth NMOS transistor N5, and the source of the fifth NMOS transistor N5 is grounded. The second node B is further connected to a gate of a third NMOS transistor N3, a drain of the third NMOS transistor N3 is connected to a third node C, the third node C is further connected to a drain of the fourth PMOS transistor P4, a source of the fourth PMOS transistor P4 is connected to a voltage source VDD, a source of the third NMOS transistor N3 is connected to a drain of the sixth NMOS transistor N6, a source of the sixth NMOS transistor N6 is grounded, the third node C is further connected to a fourth node E, the fourth node E is connected to a gate of the fifth PMOS transistor P5 and a gate of the seventh NMOS transistor N7, a source of the fifth PMOS transistor P5 is connected to a voltage source VDD, a drain of the fifth PMOS transistor P5 is connected to a drain of the fourth NMOS transistor N4, and is commonly used as an inverting output terminal Q of the first flip-flop DFF1, a source of the fourth NMOS transistor N4 is connected to a drain of the seventh NMOS transistor N7, and a source of the seventh NMOS transistor N7 is grounded.
The gate of the fourth PMOS transistor P4, the gate of the sixth PMOS transistor P6, the gate of the fourth NMOS transistor N4, and the gate of the sixth NMOS transistor N6 are all configured to serve as the non-inverting input terminal CK of the first flip-flop DFF1, and to receive the frequency division input signal CI < i >.
In the first embodiment, the conduction principle of the first flip-flop DFF1 is specifically as follows: when the frequency division input signal CI < i > is changed from a low level signal to a high level signal, the first flip-flop DFF1 is turned on, and the inverted output terminal-Q of the first flip-flop DFF1 outputs an inverted signal of the signal input terminal D thereof, when the frequency division input signal CI < i > is changed from a high level signal to a low level signal, the first flip-flop DFF1 is turned off, and the inverted output terminal-Q of the first flip-flop DFF1 maintains the current output signal output.
The conduction principle of the first flip-flop DFF1 is specifically described below with reference to fig. 10.
Referring to fig. 10, when the frequency division input signal CI < i > received by the non-inverting input terminal CK of the first flip-flop DFF1 is at a low level, the sixth PMOS transistor P6 and the fourth PMOS transistor P4 are turned on, and the fourth NMOS transistor N4 and the sixth NMOS transistor N6 are turned off. At this time, under the action of the fifth NMOS transistor N5 or the third PMOS transistor P3, the potential of the second node B is opposite to the potential of the signal input end D of the first flip-flop DFF1, specifically, if the signal input end D of the first flip-flop DFF1 inputs a high level signal, the third PMOS transistor P3 is turned off, the fifth NMOS transistor N5 is turned on, and the fifth NMOS transistor N5 will pull down the voltage at the second node B to a low potential; if the signal input end D of the first flip-flop DFF1 inputs a low level signal, the fifth NMOS transistor N5 is turned off, the third PMOS transistor P3 is turned on, and the third NMOS transistor P3 pulls up the voltage at the second node B to a high level.
Meanwhile, in view of the fact that the fourth PMOS transistor P4 is always turned on, the potential of the third node C is always high when the fourth PMOS transistor P4 is pulled up and pulled down, the potential of the fourth node E is also always high, the fifth PMOS transistor P5 is turned off, and meanwhile, the fourth NMOS transistor N4 is also turned off, the inverted output terminals Q will not output signals, that is, the first flip-flop DFF1 is turned off.
It can be seen from the above that when the frequency-divided input signal CI < i > is at a low level, the potential of the second node B in the first flip-flop DFF1 is opposite to the potential received at the signal input terminal D thereof, and the first flip-flop DFF1 is turned off.
Further, referring to fig. 10, when the frequency-divided input signal CI < i > is changed from a low level signal to a high level signal, the sixth PMOS transistor P6 and the fourth PMOS transistor P4 are turned off, the fourth NMOS transistor N4 and the sixth NMOS transistor N6 are turned on, and the potential at the second node B is opposite to the potential of the signal input terminal D of the first flip-flop DFF 1. And on the basis, under the action of the third NMOS transistor N3, the potential of the third node C is opposite to the potential of the second node B, that is, the potential of the third node C is equal to the potential of the signal input terminal D of the first flip-flop DFF 1. Specifically, when the potential of the second node B is high, the third NMOS transistor N3 is turned on, and the third NMOS transistor N3 pulls down the potential of the third node C to low potential; when the potential of the second node B is low, the third NMOS transistor N3 is turned off, so that the third node C maintains the original high potential.
And, based on the connection of the third node C to the fourth node E, the third node C should be identical to the potential of the fourth node E, i.e., the fourth node E is identical to the potential of the signal input D of the first flip-flop DFF. At this time, under the action of the fifth PMOS transistor P5 or the seventh NMOS transistor N7, the electric potential of the inverting output terminal to Q of the first flip-flop DFF is opposite to the electric potential of the fourth node E, that is, the electric potential of the inverting output terminal to Q of the first flip-flop DFF is opposite to the electric potential of the signal input terminal D of the first flip-flop DFF. Specifically, when the potential of the fourth node E is low, the seventh NMOS transistor N7 is turned off, the fifth PMOS transistor P5 is turned on, and the fifth PMOS transistor P5 pulls up the potential of the inverted output terminal to Q to high potential; when the potential of the fourth node E is high, the fifth PMOS transistor P5 is turned off, and the seventh NMOS transistor N7 is turned on, and at this time, based on the fourth NMOS transistor N4 being turned on, the fourth NMOS transistor N4 and the seventh NMOS transistor N7 pull down the potentials of the inverted output terminals Q to low.
It follows that when the frequency-divided input signal CI < i > changes from a low level signal to a high level signal, the signal output from the inverting output terminal Q of the first flip-flop DFF1 should be an inverted signal of the signal received at the signal input terminal D thereof.
Summarizing, for the first flip-flop DFF1 in the first embodiment, when the frequency-divided input signal CI < i > received by the non-inverting input terminal CK of the first flip-flop DFF1 is changed from a high level signal to a low level signal, the first flip-flop DFF1 is turned off, the signal output from the inverting output terminals Q of the first flip-flop DFF1 is not changed, and the signal potential received by the signal input terminal D of the first flip-flop DFF1 is opposite to the signal potential of the second node B. When the frequency-divided input signal CI < i > received at the non-inverting input terminal CK of the first flip-flop DFF1 is changed from a low level signal to a high level signal, the first flip-flop DFF1 is turned on, and the inverting output terminals Q thereof output the inverted signal of the signal received at the signal input terminal D thereof.
In addition, it should be noted that, from the structure of the first flip-flop DFF1 shown in fig. 10, it can be known that the flip-flop in the first embodiment of the present invention mainly adopts a nine-tube TSPC-D flip-flop, so that the structure is simple and the occupied area is small.
Further, referring again to fig. 6, the frequency dividing unit may further include a first differential circuit 01, and the first differential circuit 01 may include: the seventh inverter INV7, the eighth inverter INV8, the ninth inverter INV9, the tenth inverter INV10, and the third clock transmission gate TG3.
The input end of the seventh inverter INV7 is used as the input end of the first differential circuit 01 and is connected with the output end of the second inverter INV2, the output end of the seventh inverter INV7 is connected with the input end of the eighth inverter INV8, and the output end of the eighth inverter INV8 is connected with the input end of the ninth inverter INV 9.
The first input end of the third clock control transmission gate TG3 is connected to the output end of the seventh inverter INV7, the second input end of the third clock control transmission gate TG3 is connected to the voltage source VDD, the third input end of the third clock control transmission gate TG3 is grounded, wherein the third clock control transmission gate TG3 is always in an on state under the action of the voltage source VDD, and the output end of the third clock control transmission gate TG3 is connected to the input end of the tenth inverter INV 10.
Further, in the first embodiment, the first differential circuit 01 has a positive phase output terminal CO and a negative phase output terminal COB to output a divided output signal CO < i > and an inverted signal COB < i > of the divided output signal, respectively. Specifically, the output end of the ninth inverter INV9 is used as the non-inverting output end CO of the first differential circuit 01, and the output end of the tenth inverter INV10 is used as the inverting output end COB of the first differential circuit 01.
The input end of the first differential circuit 01 receives the frequency-divided output signal CO < i > provided by the inverting output end of the first flip-flop DFF1 through the second inverter INV2, and outputs the frequency-divided output signal CO < i > through the positive phase output end CO of the first differential circuit 01, and outputs the inverting signal COB < i > of the frequency-divided output signal through the negative phase output end COB of the first differential circuit 01.
It should be noted that the non-inverting input terminal of the first Latch D Latch1, the non-inverting input terminal of the second Latch D Latch2, and the non-inverting input terminal CK of the first flip-flop DFF1 mentioned above may be used as the positive signal input terminal of the frequency dividing unit shown in fig. 6 for receiving the frequency dividing input signal CI < i >. And, the negative phase input terminal of the first Latch D Latch1 and the negative phase input terminal of the second Latch D Latch2 may be used as the negative signal input terminal of the frequency dividing unit shown in fig. 6, for receiving the inverted signal CIB < i > of the frequency dividing input signal. Meanwhile, the positive phase output terminal CO of the first differential circuit 01 may be used as the positive signal output terminal of the frequency dividing unit shown in fig. 6 to output the frequency dividing output signal CO < i >, and the negative phase output terminal COB of the first differential circuit 01 may be used as the negative signal output terminal of the frequency dividing unit shown in fig. 6 to output the inverted signal COB < i > of the frequency dividing output signal. Wherein the frequency-divided output signal CO < i > is a signal obtained after the frequency-dividing operation is performed on the frequency-divided input signal CI < i >.
Further, the principle of the frequency dividing unit shown in fig. 6 will be described in detail in conjunction with the above. For the frequency dividing unit shown in fig. 6, when the frequency dividing control signal p=0, or when the frequency dividing control signal p=1, if the carry input signal is 0, the frequency dividing unit shown in fig. 6 may implement the frequency dividing function; when the frequency division control signal p=1 and the carry input signal is 1, the frequency division unit shown in fig. 6 can realize the frequency division by three functions.
Specifically, referring to fig. 6, when the frequency division control signal p=0 is received at the second input end of the second NAND gate NAND2, the output end of the second NAND gate NAND2 always outputs 1, and correspondingly, the signal input end of the second Latch D Latch2 always outputs 1, so that the first input end of the first NAND gate NAND1 always receives 1, and at this time, the result is the number itself based on 1 and any number of phases, so that the signal output by the output end of the first NAND gate NAND1 is related to the signal input by the second input end of the first NAND gate NAND1, and therefore, the frequency division output signal CO < i > output by the first flip-flop DFF1 is also related to the signal input by the second input end of the first NAND gate NAND 1. At this time, it can be determined that none of the third NAND gate NAND3, the first Latch D Latch1, the second NAND gate NAND2, and the second Latch D Latch2 should be equal to the frequency division output signal CO < i > outputted by the frequency division unit shown in fig. 6, and the third NAND gate NAND3, the first Latch D Latch1, the second NAND gate NAND2, and the second Latch D Latch2 can be omitted.
Based on this, the principle of the frequency dividing unit shown in fig. 6 to realize the frequency dividing function will be described:
Table 1 is a table of correspondence between the frequency-divided input signal and the received signal at the signal input terminal and the frequency-divided output signal at the negative phase output terminal of the first flip-flop DFF1 in the frequency dividing unit shown in fig. 6 when the frequency-divided control signal is 0.
TABLE 1
Referring to table 1, when the frequency dividing unit has not yet received the frequency dividing input signal CI < i >, the negative phase output end to Q output of the first flip-flop DFF1 is 0, the 0 output from the negative phase output end to Q of the first flip-flop DFF1 is inverted by the second inverter INV2 and then becomes 1 to be input to the second input end of the first NAND gate NAND1, and, based on the first input end of the first NAND gate NAND1 being always 1, the signal output from the output end of the first NAND gate should be an inverted signal of the signal output from the second input end thereof, that is, at this time, the signal output from the output end of the first NAND gate should be 0, and the signal received by the signal input end of the first flip-flop DFF1 should be 0. And when the frequency division unit starts to receive the frequency division input signal, if the frequency division input signal is 0, the first flip-flop DFF1 is disconnected, and the current output signal of the position is output, that is, the inverted output end of the first flip-flop DFF1 should still output 0 at this time, and the signal input end of the first flip-flop DFF1 should also receive 0. When the frequency-divided input signal is changed from 0 to 1, the first flip-flop turns on DFF1, and at this time, based on the signal received at the signal input terminal of the first flip-flop DFF1 being 0, the signal output at the inverting output terminal thereof should be 1, thereby causing the signal received at the signal input terminal of the first flip-flop DFF1 to also become 1. Next, if the frequency-divided input signal is changed from 1 to 0 again, the first flip-flop DFF1 is turned off, and at this time, the first flip-flop DFF1 maintains the output 1. Then, if the frequency-divided signal is changed from 0 to 1 again, the first flip-flop DFF1 is turned on again, and the signal output from the inverting output terminal thereof should be 0 based on the signal received at the signal input terminal thereof at the current time being 1.
Similarly, the correspondence shown in table 1 can be obtained, and it can be seen from table 1 that when the signal of the frequency division input signal CI < i > is 01010101, the frequency division output signal CO < i > output by the inverting output terminal of the first flip-flop DFF1 should be 001100110011, where the period of the frequency division output signal CO < i > is twice as long as the frequency division input signal CI < i >, and the frequency is half as long as the frequency division input signal CI < i >, thereby realizing the function of dividing by two.
Further, when the frequency division control signal p=1 and the carry input signal MODIN < i > is 0, the second input terminal of the third NAND gate NAND3 always receives 0, wherein, since the results of 0 and any number of phases and later are all 0, the output terminal of the third NAND gate NAND3 always outputs 1, and further, the inverted output terminal of the first Latch D Latch1 always outputs 0, the first input terminal of the second NAND gate NAND2 always receives 0, and thus, the input terminal of the second NAND gate NAND2 always receives 1, and thus, the situation is similar to the situation that the frequency division control signal is 0, and the frequency division unit realizes the frequency division function when referring to the description of "when the frequency division control signal is 0", it can be determined that when the frequency division control signal p=1 and the carry input signal is 0, the frequency division unit also realizes the frequency division function.
And when the frequency division control signal p=1 and the carry input signal is 1, the frequency division unit shown in fig. 6 implements the three frequency division function, and the specific principle is as follows:
For the first Latch D Latch1, when the frequency division input signal CI < i > is at a low level, the first Latch D Latch1 is turned on, and the inverting output terminal outputs an inverted signal of the signal received by the signal input terminal thereof, and when the frequency division input signal CI < i > is at a high level, the first Latch D Latch1 is turned off, and the inverting output terminal thereof maintains the current output signal unchanged. For the second Latch D Latch2, when the frequency division input signal CI < i > is at a high level, the second Latch D Latch2 is turned on, and the non-inverting output terminal outputs a signal received by the signal input terminal thereof, and when the frequency division input signal is at a low level, the second Latch D Latch2 is turned off, and the non-inverting output terminal thereof maintains the current output signal unchanged.
Thus, the expressions for the input and output signals for each device can be determined in conjunction with fig. 6 as:
D1＝～((～Q0)·MODIN<i>)＝Q0+～MODIN<i>＝Q0
D2＝～((～Q1)·P<i>)＝Q1+～P<i>＝Q1
D0＝～(Q2·Q0)
Wherein "+" represents an OR operation, "-" represents an AND operation, "-" represents an inverse operation, and D1 is a signal received by the signal input terminal of the first Latch Dlatch 1, -Q0 is a signal outputted by the inverting output terminal of the first flip-flop DFF1 to Q, that is, the frequency division output signal CO < i >, D2 is a signal received by the signal input terminal of the second Latch D Latch2, -Q1 is a signal outputted by the inverting output terminal of the first Latch D Latch1, D0 is a signal received by the signal input terminal D of the first flip-flop DFF, and Q2 is a signal outputted by the non-inverting output terminal of the second Latch D Latch 2.
Based on this, table 2 is a correspondence table among D0, Q0, D1, Q1, D2, Q2.
TABLE 2
Referring to table 2, when the frequency dividing unit just starts up and the frequency dividing input signal CI < i > has not been received, the first flip-flop Q0 outputs the high level signal 1, the first latch Q1 outputs the high level signal 1, the second latch Q2 outputs the low level signal 0, at this time, the first flip-flop D0 should be the high level signal 1, D0 is 1, D1 is 0, and D2 is 0. When the frequency division input signal CI < i > is 0, the first flip-flop DFF1 and the second Latch D Latch2 are turned off, the first Latch D Latch1 is turned on, and then-Q0 of the first flip-flop DFF1 should maintain the current output signal output 1, Q2 of the second Latch D Latch2 should also maintain the current output signal output 0, and-Q1 of the first Latch D Latch1 should output an inverted signal of D1, that is, should output 1, at this time, D2 should maintain 1. And, when the frequency-divided input signal CI < i > is switched from 0 to 1, the first flip-flop DFF1 and the second Latch D Latch2 are turned on, the first Latch D Latch1 is turned off, then-Q0 of the first flip-flop DFF1 should output an inverted signal of D0, then-Q0 should be 0, Q2 of the second Latch D Latch2 should also output D2, that is, Q2 should be 0, and the first Latch D Latch1 is turned off, then-Q1 of the first Latch D Latch1 should maintain an output of 1. In this case, D0 is 1, D1 is 1, and D2 is 0. And, when the frequency-divided input signal CI < i > is switched from 1 to 0 again, the first flip-flop DFF1 and the second Latch D Latch2 are turned off, the first Latch D Latch1 is turned on, and then Q0 of the first flip-flop DFF1 should maintain the current output signal output 0, Q2 of the second Latch D Latch2 should also maintain the current output signal output 0, and Q1 of the first Latch D Latch1 should output an inverted signal of D1, that is, should output 0.
Similarly, the correspondence shown in table 2 can be obtained, and it can be seen from table 2 that when the signal of the frequency division input signal CI < i > is 01010101, the frequency division output signal CO < i > output by the inverting output terminal of the first flip-flop DFF1 should be 100001100001100001, where the period of the frequency division output signal CO < i > is three times that of the frequency division input signal CI < i >, and the frequency is one third that of the frequency division input signal CI < i >, thereby realizing the function of three frequency divisions.
Thus, in combination with the above, the frequency dividing unit divides the frequency division input signal CI < i > to output the frequency division output signal CO < i > mainly based on the frequency division control signal P < i > and the carry input signal MODOUT < i > received by the frequency dividing unit, and the frequency division output signals CO < i > with different frequency division ratios can be obtained by adjusting the values of the frequency division control signal P < i > and the carry input signal MODOUT < i >.
It should be noted that, for the frequency dividing unit provided in fig. 6 in the first embodiment, even if there is a certain delay in outputting the signal from the Latch, there is only a delay between the rising edge of the divided input signal CI < i > received by the first Latch D Latch1 and the rising edge of the carry output signal MODOUT < i > output by the first Latch D Latch 1. Thus, when the frequency dividing unit provided in the first embodiment is applied to the multi-mode frequency divider, the frequency dividing output signal MODOUT < i > outputted by the frequency dividing unit is free from glitches, so that the accuracy of frequency division is ensured, wherein the explanation about the accuracy of frequency division when the frequency dividing unit provided in the first embodiment is applied to the multi-mode frequency divider can be specifically referred to the description in the third embodiment.
In addition, the frequency dividing unit provided in the first embodiment of the present invention includes one flip-flop (i.e., the first flip-flop DFF 1) and two latches (i.e., the first latches D Latch1 and D Latch 2), so that the frequency dividing unit has a simple structure and a small occupied area. And, since the first flip-flop DFF1 is a TSPC type D flip-flop, its delay is low, efficiency is high, and power consumption is low.
In summary, when the frequency dividing unit provided in fig. 6 in the first embodiment of the present invention is applied to the multi-mode frequency divider, the multi-mode frequency divider can be ensured to be able to correctly divide frequency, and the frequency dividing unit provided in fig. 6 has lower delay, lower power consumption, higher efficiency and smaller occupied area.
Example two
Further, in the second embodiment, fig. 11 is a schematic diagram of a frequency dividing unit according to the second embodiment of the present invention, and as shown in fig. 11, the frequency dividing unit may include a second flip-flop DFF2, a third flip-flop DFF3, a fourth NAND gate NAND4, a fifth NAND gate NAND5, a sixth NAND gate NAND6, a fifth inverter INV5, and a sixth inverter INV6.
The first input end of the fourth NAND gate NAND4 is connected to the inverted output end-Q of the third flip-flop DFF3, the second input end of the fourth NAND gate NAND4 is configured to receive the frequency division control signal P < i >, and the output end of the fourth NAND gate NAND4 is connected to the first input end of the sixth NAND gate NAND 6. The second input end of the sixth NAND gate NAND6 is connected to the output end of the fifth inverter INV5, the output end of the sixth NAND gate NAND6 is connected to the signal input end D of the second flip-flop DFF2, the inverted output end-Q of the second flip-flop DFF2 is connected to the input end of the fifth inverter INV5, so as to be used for outputting a frequency division output signal CO < i >, and the inverted output end-Q of the second flip-flop DFF2 is also connected to the first input end of the fifth NAND gate NAND 5. The second input end of the fifth NAND gate NAND5 is configured to receive a carry input signal, and the output end of the fifth NAND gate NAND5 is connected to the input end of the sixth inverter INV6, so as to output a carry output signal MODTOUT < i > through the sixth inverter INV 6. And the output end of the fifth NAND gate NAND5 is also connected with the signal input end of the third flip-flop DFF 3.
In the second embodiment, the structures of the second flip-flop DFF2 and the third flip-flop DFF3 are the same as those of the first flip-flop DFF1, and may be nine-tube TSPC-D flip-flops, and the conduction principle of the second flip-flop DFF2 and the third flip-flop DFF3 is the same as that of the first flip-flop DFF1, so the structures and conduction principle of the second flip-flop DFF2 and the third flip-flop DFF3 may be specifically referred to the description of the first flip-flop DFF1 in the first embodiment, and the second embodiment will not be described herein.
Further, referring to fig. 11, the frequency dividing unit may further include a second differential circuit 02, and the second differential circuit 02 may include: an eleventh inverter INV11, a twelfth inverter INV12, a thirteenth inverter INV13, a fourteenth inverter INV14, and a fourth clocked transmission gate TG4.
An input end of the eleventh inverter INV11 is connected to an output end of the fifth inverter INV5, an output end of the eleventh inverter INV11 is connected to an input end of the twelfth inverter INV12, and an output end of the twelfth inverter INV12 is connected to an input end of the thirteenth inverter IVN 13.
The signal input end of the fourth clock transmission gate TG4 is connected to the output end of the eleventh inverter INV11, and the output end of the fourth clock transmission gate TG4 is connected to the input end of the fourteenth inverter INV 14.
Still further, in the second embodiment, the second differential circuit 02 has a positive phase output terminal CO and a negative phase output terminal COB to output the divided output signal CO < i > and the inverted signal COB < i > of the divided output signal, respectively. Specifically, in the second differential circuit 02, the output end of the thirteenth inverter IVN13 is used as the non-inverting output end CO of the second differential circuit 02, and the output end of the fourteenth inverter INV14 is used as the inverting output end COB of the second differential circuit 02.
The input end of the second differential circuit 02 receives the frequency-divided output signal CO < i > provided by the inverting output end-Q of the second flip-flop DFF2 through the fifth inverter INV5, and outputs the frequency-divided output signal CO < i > through the positive phase output end CO of the second differential circuit 02, and outputs the inverting signal COB < i > of the frequency-divided output signal through the negative phase output end COB of the second differential circuit 02.
It should be noted that, the positive input terminal CK of the second flip-flop DFF2 and the positive input terminal CK of the third flip-flop DFF3 mentioned above may be used as the positive signal input terminal of the frequency dividing unit shown in fig. 11 for receiving the frequency dividing input signal CI < i >. The positive phase output terminal CO of the second differential circuit 02 may be used as the positive signal output terminal of the frequency dividing unit shown in fig. 11 to output the frequency-divided output signal CO < i >, and the negative phase output terminal COB of the second differential circuit 02 may be used as the negative signal output terminal of the frequency dividing unit shown in fig. 11 to output the inverted signal COB < i > of the frequency-divided output signal. Wherein the frequency-divided output signal CO < i > is a signal obtained after the frequency-dividing operation is performed on the frequency-divided input signal CI < i >.
Note that the frequency dividing unit shown in fig. 11 functions similarly to the frequency dividing unit shown in fig. 6. Specifically, the frequency dividing unit shown in fig. 11 may realize a frequency dividing function when it receives the frequency dividing control signal P < i > =0, or when it receives the frequency dividing control signal P < i > =1, modin < i > =0. When the frequency division control signal P < i > =1 and the modulus < i > =1 it receives, the frequency division unit shown in fig. 11 can realize the three frequency division function.
In view of the fact that the principle of the function of the frequency dividing unit shown in fig. 11 is similar to that of the frequency dividing unit shown in fig. 6, the principle of the function of the frequency dividing unit shown in fig. 11 may be specifically referred to the description of the principle of the function of the frequency dividing unit shown in fig. 6, and the second embodiment of the present invention is not described herein.
In summary, for the frequency dividing unit provided in fig. 11 of the present invention, since the carry output signal MODOUT < i > is directly output from the output end of the fifth NAND gate NAND5, the third flip-flop DFF3 is not needed, and thus, the output delay can be reduced and the working efficiency of the frequency dividing unit can be improved. Moreover, based on the fact that the second flip-flop DFF2 and the third flip-flop DFF3 in the frequency dividing unit provided in fig. 11 are all nine-tube TSPC-D flip-flops which are simpler to use, the structure is simple, and the occupied area is small. In addition, the frequency dividing unit shown in fig. 11 is a dual D flip-flop structure, which has a high processing speed and low power consumption.
In addition, in this embodiment, the inverters in the first differential circuit 01 and the second differential circuit 02 may specifically be used as buffers to reduce the rising and falling time of the frequency-divided output signal CO < i > and the inverted signal COB < i > of the frequency-divided output signal, thereby improving the working efficiency. And, the transmission gates in the first differential circuit 01 and the second differential circuit 02 can delay the inverted signal COB < i > of the frequency division output signal, so that the phase difference between the inverted signal COB < i > and the frequency division output signal CO < i > is about 180 degrees, and the frequency division unit can work correctly.
Example III
Fig. 12 is a schematic structural diagram of a multi-mode frequency divider according to the embodiment of the present invention, and as shown in fig. 12, the multi-mode frequency divider is formed by cascading a plurality of frequency dividing units. The first-stage frequency dividing unit of the multi-modulus frequency divider may include a frequency dividing unit shown in fig. 11 (i.e., a frequency dividing unit provided in the second embodiment), and the other-stage frequency dividing units of the multi-modulus frequency divider except the first-stage frequency dividing unit include frequency dividing units shown in fig. 6 (i.e., frequency dividing units provided in the first embodiment).
And, referring to fig. 12, the first stage frequency dividing unit may include:
a positive signal input CI for receiving a divided input signal CI < i >.
Carry input MODIN for receiving carry input signal MODIN < i >.
Carry output MODOUT for outputting carry output signal MODOUT < i >.
The frequency division control terminal P is used for receiving the frequency division control signal P < i >.
And the positive signal output end CO is used for outputting a frequency division output signal CO < i >, wherein the frequency division output signal CO < i > is a frequency division signal of the frequency division input signal CI < i >.
And a negative signal output terminal COB for outputting an inverted signal COB < i > of the frequency-divided output signal.
The positive input terminal CK of the second flip-flop DFF2 and the positive input terminal CK of the third flip-flop DFF3 in the first stage frequency dividing unit may be used as the positive signal input terminal CI of the first stage frequency dividing unit; the second input end of the fifth NAND gate NAND5 may be used as the carry input end MODIN of the first stage frequency dividing unit; the second input end of the fourth NAND gate NAND4 may be used as the frequency division control end P of the first stage frequency division unit; an output end of the sixth inverter INV6 may be used as the carry output end MODOUT of the first stage frequency dividing unit; the positive phase output end CO of the second differential circuit 02 in the first frequency dividing unit is used as the positive signal output end CO of the first-stage frequency dividing unit; the negative phase output terminal COB of the second differential circuit 02 in the first frequency dividing unit may be used as the negative signal output terminal COB of the first stage frequency dividing unit.
Optionally, the other frequency division unit may include:
a positive signal input CI for receiving a divided input signal CI < i >.
A negative signal input terminal CIB for receiving an inverted signal CIB < i > of the divided input signal.
Carry input MODIN for receiving carry input signal MODIN < i >.
Carry output MODOUT for outputting carry output signal MODOUT < i >.
The frequency division control terminal P is used for receiving the frequency division control signal P < i >.
And the positive signal output end CO is used for outputting a frequency division output signal CO < i >, and the frequency division output signal CO < i > is a frequency division signal corresponding to the frequency division input signal CI < i >.
And a negative signal output terminal COB for outputting an inverted signal COB < i > of the frequency-divided output signal.
The positive input end of the first Latch D Latch1, the positive input end of the second Latch D Latch2 and the positive input end CK of the first flip-flop DFF1 in the other frequency dividing units can be used as the positive signal input end CI of the other frequency dividing units; the negative phase input end of the first Latch D Latch1 and the negative phase input end of the second Latch D Latch2 in the other frequency division unit can be used as the negative signal input end CIB of the other frequency division unit; the second input end of the second NAND gate NAND2 may be used as the frequency division control end P of the other-stage frequency division unit; the second input end of the third NAND gate NAND3 may be used as the carry input end MODIN of the other-stage frequency dividing unit; the output end of the first inverter INV1 is used as the carry output end MODOUT of the other-stage frequency dividing unit; the positive phase output end CO of the first differential circuit 01 in the other frequency division unit can be used as the positive signal output end CO of the other frequency division unit; the negative phase output terminal COB of the first differential circuit 01 in the other stage frequency dividing unit may be used as the negative signal output terminal COB of the other stage frequency dividing unit.
Optionally, referring to fig. 12, the positive signal input terminal CI of the first stage frequency dividing unit is configured to receive an initial frequency dividing input signal CI <0>, the positive signal input terminal CI of each stage frequency dividing unit after the first stage frequency dividing unit is connected to the positive signal output terminal CO of the previous stage frequency dividing unit, and the negative signal input terminal CIB of each stage frequency dividing unit after the first stage frequency dividing unit is connected to the negative signal output terminal COB of the previous stage frequency dividing unit.
And, the carry input MODIN of the last stage of frequency dividing unit is used for receiving the initial carry input signal MODIN <0>, and the carry input MODIN of each stage of frequency dividing unit before the last stage of frequency dividing unit is connected with the carry output MODOUT of the next stage of frequency dividing unit.
As can be seen from the above, in the multi-mode frequency divider provided by the third embodiment, the frequency division input signal CI < i > of each stage of frequency division units except the first stage of frequency division unit is the frequency division output signal CO < i-1> of the previous stage of frequency division unit, that is, CI < i > =co < i-1>, and the carry output signal MODOUT < i > of each stage of frequency division unit except the last stage of frequency division unit is the carry input signal MODIN < i-1> of the previous stage of frequency division unit, that is, MODOUT < i > = MODIN < i-1>.
Based on this, whereas the multi-mode frequency divider according to the embodiment of the present invention includes the frequency dividing unit provided in the first embodiment, the carry output signal MODOUT < i > of each of the frequency dividing units other than the first frequency dividing unit has a delay of one latch from the falling edge of the frequency dividing input signal CI < i > of the current frequency dividing unit. That is, equivalently, there is a delay of one latch between the edge of the carry input signal MODIN < i > of each stage of the frequency dividing units except the first stage of the frequency dividing unit and the falling edge of the frequency dividing input signal CI < i > of the present stage of the frequency dividing unit (for example, refer to fig. 8). At this time, when the third NAND gate NAND3 in each stage of the frequency dividing units except the first stage of the frequency dividing unit performs the and processing on the carry input signal MODIN < i > and the frequency dividing input signal CI < i > received thereto, a glitch signal does not occur in the signal obtained after the and processing, for example, refer to fig. 8. Therefore, no glitch exists in the signal output by the third NAND gate NAND3 to the first Latch D Latch1, and further no glitch exists in the carry output signal MODOUT < i > output by the carry output end MODOUT of each stage of frequency dividing unit except the first stage of frequency dividing unit, so that the phenomenon of "glitch exists in the carry output signal output by the frequency dividing unit" in the related art is avoided, and the frequency dividing accuracy of the multi-mode frequency divider is ensured.
In addition, since the first stage frequency dividing unit of the multi-modulus frequency divider performs the first frequency division on the initial frequency division input signal, the frequency requirement is high, and thus when the first stage frequency dividing unit is set as the frequency dividing unit shown in fig. 11, the processing speed based on the frequency dividing unit shown in fig. 11 is high, the working efficiency is high, and the frequency dividing efficiency of the multi-modulus frequency divider can be improved.
Note that, since the carry output signal MODOUT <0> of the first stage frequency dividing unit is not input to the other stage frequency dividing units, even if there is a glitch signal in the carry output signal MODOUT <0> of the first stage frequency dividing unit, the frequency dividing effect of the multi-mode frequency divider is not affected.
In summary, in the multi-mode frequency divider provided by the present invention, the first stage frequency dividing unit of the multi-mode frequency divider includes the frequency dividing unit shown in fig. 11, and the processing speed is faster. Meanwhile, each stage of frequency dividing units except the first stage of frequency dividing unit in the multi-mode frequency divider comprises the frequency dividing unit shown in fig. 6, so that no burr signal exists in carry output signals output by each stage of frequency dividing units except the first stage of frequency dividing unit, and the multi-mode frequency divider can normally divide signals. The multi-mode frequency divider ensures the frequency dividing speed, the frequency dividing accuracy and lower power consumption.
Meanwhile, the multi-mode frequency divider has smaller delay, smaller occupied area, layout space saving and higher portability.
Finally, in the invention, the working frequency of the front simulation and the working frequency of the rear simulation of the multi-mode frequency divider are higher under the worst process angle, wherein the front simulation can reach 6.6GHz, and the rear simulation can also reach 4.2GHz, thereby further improving the accuracy of frequency division processing.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the system disclosed in the embodiment, the description is relatively simple because of corresponding to the method disclosed in the embodiment, and the relevant points refer to the description of the method section.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (12)
1. A frequency dividing unit, which is characterized by comprising a first latch, a second latch, a first trigger, a first NAND gate, a second NAND gate, a third NAND gate, a first inverter and a second inverter;
The first input end of the second NAND gate is connected with the inverting output end of the first latch, the second input end of the second NAND gate is used for receiving a frequency division control signal, and the output end of the second NAND gate is connected with the signal input end of the second latch; the non-inverting output end of the second latch is connected with the first input end of the first NAND gate; the second input end of the first NAND gate is connected with the output end of the second inverter, and the output end of the first NAND gate is connected with the signal input end of the first trigger; the inverting output end of the first trigger is connected with the input end of the second inverter and the first input end of the third NAND gate, the inverting output end of the first trigger is used for outputting a frequency division output signal, the second input end of the third NAND gate is used for receiving a carry input signal, and the output end of the third NAND gate is connected with the signal input end of the first latch; the non-inverting output end of the first latch is connected with the input end of the first inverter and outputs a carry output signal through the output end of the first inverter;
The first latch is provided with a normal phase input end and is used for receiving a frequency division input signal, and when the frequency division input signal is a low level signal, the first latch is conducted, and the normal phase output end of the first latch starts to output the signal received by the signal input end of the first latch and is output through the first inverter so as to form a carry output signal.
2. The frequency dividing unit of claim 1, wherein the first latch further has a negative phase input for receiving an inverse of the frequency divided input signal;
The second latch is provided with a positive phase input end and a negative phase input end, and the positive phase input end of the second latch is used for receiving a frequency division input signal; the negative phase input end of the second latch is used for receiving an inverted signal of the frequency division input signal, wherein when the frequency division input signal is a high level signal, the second latch is conducted;
the first flip-flop is provided with a non-inverting input terminal for receiving a frequency-divided input signal, wherein the first flip-flop is turned on when the frequency-divided input signal changes from a low level signal to a high level signal.
3. The frequency dividing unit of claim 2, wherein the first latch comprises a first clocked transmission gate, a first clocked inverter, and a third inverter;
The first input end of the first clock control transmission gate is connected with the output end of the third NAND gate, the output end of the first clock control transmission gate is respectively connected with the input end of the first inverter, the input end of the third inverter and the output end of the first clock control inverter, and the output end of the third inverter is respectively connected with the first input end of the second NAND gate and the first input end of the first clock control inverter;
The first clock transmission gate is provided with a second input end and a third input end, wherein the second input end of the first clock transmission gate is used as a positive phase input end of the first latch and is used for receiving a frequency division input signal, and the third input end of the first clock transmission gate is used as a negative phase input end of the first latch and is used for receiving an inverse signal of the frequency division input signal;
The first clocked inverter is provided with a second input end and a third input end, wherein the second input end of the first clocked inverter is used as a negative phase input end of the first latch and is used for receiving an inverted signal of a frequency division input signal, and the third input end of the first clocked inverter is used as a positive phase input end of the first latch and is used for receiving the frequency division input signal;
and when the frequency division input signal is a low level signal, the first clock control transmission gate is conducted; when the frequency division input signal is a high level signal, the first clocked inverter is turned on.
4. The frequency dividing unit of claim 2, wherein the second latch comprises a second clocked transmission gate, a second clocked inverter, and a fourth inverter;
The first input end of the second clock control transmission gate is connected with the output end of the second NAND gate, the output end of the second clock control transmission gate is respectively connected with the first input end of the first NAND gate, the input end of the fourth inverter and the output end of the second clock control inverter, and the output end of the fourth inverter is connected with the first input end of the second clock control inverter;
the second clock transmission gate is further provided with a second input end and a third input end, wherein the second input end of the second clock transmission gate is used as a negative phase input end of the second latch and is used for receiving an inverted signal of a frequency division input signal, and the third input end of the second clock transmission gate is used as a positive phase input end of the second latch and is used for receiving the frequency division input signal;
the second clocked inverter is further provided with a second input end and a third input end, wherein the second input end of the second clocked inverter is used as a positive phase input end of the second latch and is used for receiving a frequency division input signal, and the third input end of the second clocked inverter is used as a negative phase input end of the second latch and is used for receiving an inversion signal of the frequency division input signal;
And when the frequency division input signal is a high level signal, the second clock control transmission gate is conducted; when the frequency division input signal is a low level signal, the second clocked inverter is turned on.
5. The frequency dividing unit according to claim 1, further comprising a first differential circuit having a positive phase output terminal and a negative phase output terminal;
The input end of the first differential circuit is connected with the output end of the second inverter, so that the frequency division output signal provided by the inverted output end of the first trigger is received through the second inverter, the frequency division output signal is output through the positive phase output end of the first differential circuit, and the inverted signal of the frequency division output signal is output through the negative phase output end of the first differential circuit.
6. The multi-mode frequency divider is characterized by being formed by cascading a plurality of frequency dividing units;
wherein the frequency dividing units of any one of claims 1 to 5 are included in the multi-modulus frequency divider except the first-stage frequency dividing unit;
The first-stage frequency dividing unit of the multi-mode frequency divider comprises a second trigger, a third trigger, a fourth NAND gate, a fifth NAND gate, a sixth NAND gate, a fifth inverter and a sixth inverter;
The first input end of the fourth NAND gate is connected with the inverting output end of the third trigger, the second input end of the fourth NAND gate is used for receiving a frequency division control signal, and the output end of the fourth NAND gate is connected with the first input end of the sixth NAND gate; the second input end of the sixth NAND gate is connected with the output end of the fifth inverter, the output end of the sixth NAND gate is connected with the signal input end of the second trigger, the inverting output end of the second trigger is connected with the input end of the fifth inverter, the inverting output end of the second trigger is used for outputting a frequency division output signal, and the inverting output end of the second trigger is also connected with the first input end of the fifth NAND gate; the second input end of the fifth NAND gate is used for receiving a carry input signal, and the output end of the fifth NAND gate is connected with the input end of the sixth inverter so as to output a carry output signal through the sixth inverter; and the output end of the fifth NAND gate is also connected with the signal input end of the third trigger.
7. The multi-modulus divider of claim 6, wherein the second flip-flop and the third flip-flop each have a non-inverting input for receiving a divided input signal, and wherein the second flip-flop and the third flip-flop are turned on when the divided input signal changes from a low level signal to a high level signal.
8. The multi-modulus divider of claim 6, wherein the dividing unit further comprises a second differential circuit having a positive phase output and a negative phase output;
The input end of the second differential circuit is connected with the output end of the fifth inverter, so that the frequency division output signal provided by the inverting output end of the second trigger is received through the fifth inverter, the frequency division output signal is output through the positive phase output end of the second differential circuit, and the inverted signal of the frequency division output signal is output through the negative phase output end of the second differential circuit.
9. The multi-modulus divider according to any of claims 6-8, wherein the first stage divider block comprises:
a positive signal input for receiving a divided input signal;
The carry input end is used for receiving a carry input signal;
the carry output end is used for outputting a carry output signal;
the frequency division control end is used for receiving the frequency division control signal;
the positive signal output end is used for outputting a frequency division output signal, and the frequency division output signal is a frequency division signal corresponding to the frequency division input signal;
the negative signal output end is used for outputting an inverted signal of the frequency division output signal;
The positive input end of the second trigger and the positive input end of the third trigger in the first-stage frequency dividing unit are used as positive signal input ends of the first-stage frequency dividing unit; the second input end of the fifth NAND gate is used as the carry input end of the first-stage frequency dividing unit; the second input end of the fourth NAND gate is used as a frequency division control end of the first-stage frequency division unit; the output end of the sixth inverter is used as the carry output end of the first-stage frequency dividing unit; the positive phase output end of the second differential circuit is used as the positive signal output end of the first-stage frequency dividing unit; the negative phase output end of the second differential circuit is used as the negative signal output end of the first-stage frequency dividing unit.
10. The multi-modulus divider of claim 6, wherein the other fractional frequency element comprises:
a positive signal input for receiving a divided input signal;
a negative signal input for receiving an inverse of the divided input signal;
The carry input end is used for receiving a carry input signal;
the carry output end is used for outputting a carry output signal;
the frequency division control end is used for receiving the frequency division control signal;
the positive signal output end is used for outputting a frequency division output signal, and the frequency division output signal is a frequency division signal corresponding to the frequency division input signal;
the negative signal output end is used for outputting an inverted signal of the frequency division output signal;
The positive input end of the first latch, the positive input end of the second latch and the positive input end of the first trigger in the other frequency dividing units serve as positive signal input ends of the other frequency dividing units; the negative phase input end of the first latch and the negative phase input end of the second latch are used as negative signal input ends of the other frequency division units; the second input end of the second NAND gate is used as a frequency division control end of the other-stage frequency division unit; the second input end of the third NAND gate is used as the carry input end of the other-stage frequency dividing unit; the output end of the first inverter is used as the carry output end of the other-stage frequency dividing unit; the positive phase output end of the first differential circuit in the other frequency dividing unit is used as the positive signal output end of the other frequency dividing unit; the negative phase output end of the first differential circuit is used as the negative signal output end of the other-stage frequency dividing unit.
11. The multi-modulus divider of claim 10,
The positive signal input end of the first-stage frequency dividing unit is used for receiving an initial frequency dividing input signal, the positive signal input end of each stage of frequency dividing unit behind the first-stage frequency dividing unit is connected with the positive signal output end of the previous stage of frequency dividing unit, and the negative signal input end of each stage of frequency dividing unit behind the first-stage frequency dividing unit is connected with the negative signal output end of the previous stage of frequency dividing unit;
and the carry input end of the last stage frequency dividing unit is used for receiving an initial carry input signal, and the carry input end of each stage frequency dividing unit before the last stage frequency dividing unit is connected with the carry output end of the next stage frequency dividing unit.
12. The multi-modulus divider of claim 6, wherein the divided input signal comprises a clock signal.
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| CN117674824B (en) * | 2024-02-01 | 2024-04-09 | 成都铭科思微电子技术有限责任公司 | Low-jitter clock frequency division implementation circuit |
| CN120128164A (en) * | 2025-05-13 | 2025-06-10 | 合肥集创微电子科技有限公司 | High-speed frequency divider, multi-mode frequency divider, phase-locked loop circuit, chip and electronic equipment |
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