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CN111919296A - Power module and method of manufacturing power module - Google Patents

Power module and method of manufacturing power module Download PDF

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Publication number
CN111919296A
CN111919296A CN201980022355.1A CN201980022355A CN111919296A CN 111919296 A CN111919296 A CN 111919296A CN 201980022355 A CN201980022355 A CN 201980022355A CN 111919296 A CN111919296 A CN 111919296A
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China
Prior art keywords
power
prepackaged
conductive material
layer
substrate
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Granted
Application number
CN201980022355.1A
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Chinese (zh)
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CN111919296B (en
Inventor
J·莫兰德
R·佩林
R·姆莱德
J·万楚克
S·莫洛夫
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Publication of CN111919296A publication Critical patent/CN111919296A/en
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Publication of CN111919296B publication Critical patent/CN111919296B/en
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Abstract

Disclosed is a power module (1), the power module (1) comprising: -a first and a second substrate (10), each substrate comprising a patterned layer (12) of electrically conductive material; -a plurality of prepackaged power cells (20) positioned between the substrates, each cell comprising: -an electrically insulating core (21) in which at least one power die (21) is embedded, and-two outer layers (23) of electrically conductive material on opposite sides of the electrically insulating core (21), said outer layers being connected to respective patterned layers of the substrate, respectively, wherein each outer layer of the pre-packaged power unit comprises a contact pad (230) connected to a respective contact (220) of the power die by a connection arranged in the electrically insulating core (21), said contact pad having a surface area larger than the surface area of the power die electrical contact connected thereto.

Description

功率模块以及制造功率模块的方法Power module and method of manufacturing power module

技术领域technical field

本发明涉及一种包括两个基板以及定位在基板之间的多个预包装功率单元的功率模块,各个预包装功率单元包括至少一个功率管芯。本发明还涉及这种功率模块的制造方法。The present invention relates to a power module comprising two substrates and a plurality of prepackaged power cells positioned between the substrates, each prepackaged power cell comprising at least one power die. The invention also relates to a method of manufacturing such a power module.

背景技术Background technique

例如在许多不同的领域中(例如,汽车、航空、铁路工业中),诸如二极管或各种类型的功率晶体管(MOSFET、JFET、IGBT、HEMT)的功率管芯是用于电功率的控制和转换的功率模块的基本组件。与通常以横向方式构建的信号调理管芯相反垂直构造功率管芯。结果,管芯在其各侧具有电连接。For example in many different fields (eg in the automotive, aviation, railway industry) power dies such as diodes or various types of power transistors (MOSFET, JFET, IGBT, HEMT) are used for the control and conversion of electrical power Basic components of a power module. The power die is constructed vertically as opposed to the signal conditioning die, which is typically constructed in a lateral manner. As a result, the die has electrical connections on its sides.

目前将功率管芯连接到其它组件(例如,在功率模块中)的最常见方式是通过使用诸如直接接合铜(DBC)基板的基板,其包括至少一侧覆盖有铜层的陶瓷板。功率管芯的一侧被焊接或烧结在基板上,在管芯的另一侧通过超声焊接在管芯金属化上的引线接合或带连接。The most common way to connect power dies to other components (eg, in power modules) today is through the use of a substrate such as a direct bond copper (DBC) substrate, which includes a ceramic board covered with a copper layer on at least one side. One side of the power die is soldered or sintered to the substrate, and the other side of the die is connected by wire bonds or ribbons ultrasonically soldered onto the die metallization.

开关频率的不断增加允许整个转换器的体积减小。这种小型化导致功率集中在减小的体积中。因此,热密度进一步增加。所有这些演变会聚为需要功率模块的可靠性增加以及热增强。The ever-increasing switching frequency allows the overall converter to be reduced in size. This miniaturization results in the concentration of power in a reduced volume. Therefore, the heat density is further increased. All of these evolutions converge to require increased reliability and thermal enhancement of power modules.

为了增强包括多个功率管芯的功率模块中的热耗散,已经提出了包括两个冷却基板(例如,DBC)的功率模块,功率管芯被夹在这两个冷却基板之间。例如文献US6,072,240中就是这种情况,其公开了定位在两个基板之间的多个IGBT管芯。To enhance heat dissipation in power modules including multiple power dies, power modules have been proposed that include two cooling substrates (eg, DBCs) between which the power dies are sandwiched. This is the case, for example, in document US 6,072,240, which discloses a plurality of IGBT dies positioned between two substrates.

这些功率模块的主要优点是其通过双面冷却来散热的良好能力。The main advantage of these power modules is their good ability to dissipate heat through double-sided cooling.

然而,现有双面冷却解决方案并非没有缺点。首先,使用烧结技术,将管芯接合在两个基板之间需要在基板上和管芯上施加压力。由于管芯非常脆弱,所以必须小心地使压力在基板的表面上适当分布,以免破坏定位在其间的任何管芯。However, existing double-sided cooling solutions are not without drawbacks. First, using sintering techniques, bonding the die between two substrates requires applying pressure on the substrate and on the die. Since the dies are very fragile, care must be taken to properly distribute the pressure over the surface of the substrate so as not to damage any dies positioned in between.

其次,在各种类型的功率管芯之间(例如,在二极管和功率开关之间)管芯厚度通常不同。由于该厚度差异,第二基板无法直接接合到管芯的上侧。为了适应这些厚度变化,已提出了一些解决方案,其中基板非平面并且表现出凸出的区域或柱(例如文献US2011/0254177中)。然而,由于各个零件的尺寸公差,这种模块的设计和制造复杂。Second, die thickness typically varies between various types of power dies (eg, between diodes and power switches). Due to this thickness difference, the second substrate cannot be directly bonded to the upper side of the die. To accommodate these thickness variations, solutions have been proposed in which the substrate is non-planar and exhibits raised areas or pillars (eg in document US2011/0254177). However, the design and manufacture of such modules is complicated due to the dimensional tolerances of the individual parts.

还提出了这样的功率模块:通过烧结在管芯和基板上的凸块来形成管芯与第二基板之间的界面,凸块的尺寸适应管芯之间的厚度变化。在这种解决方案中,凸块还充当间隔物以便确保功能性电绝缘。如果基板仅分离开管芯的厚度(平均约0.5mm),则无法确保功能绝缘。此外,添加的垫片需要被焊接在管芯上和基板上,从而增加了焊料层,这将增加热应力并使导热性劣化。Power modules are also proposed in which the interface between the die and the second substrate is formed by sintering bumps on the die and the substrate, the size of the bumps adapting to thickness variations between the dies. In this solution, the bumps also act as spacers in order to ensure functional electrical isolation. If the substrate is separated only by the thickness of the die (about 0.5mm on average), functional insulation cannot be ensured. Additionally, the added pads need to be soldered on the die and on the substrate, thereby increasing the solder layer, which increases thermal stress and degrades thermal conductivity.

然而,这些解决方案没有解决另一问题,该问题在于功率管芯电触点的非常有限的尺寸。例如,晶体管控制焊盘(栅极或基极)远小于功率焊盘。因此,将其连接到基板特别困难。特别是对于宽带隙器件,栅极连接需要高精度零件和准确对准,这又涉及昂贵的设备并带来高产风险。However, these solutions do not address another problem, which is the very limited size of the electrical contacts of the power die. For example, transistor control pads (gate or base) are much smaller than power pads. Therefore, connecting it to the substrate is particularly difficult. Especially for wide-bandgap devices, gate connections require high-precision parts and accurate alignment, which in turn involves expensive equipment and risks high yields.

鉴于此问题,上述解决方案目前仍未商用,并且文献中可见的双面模块限于类似IGBT芯片或二极管的大特征尺寸,并且不适于任何类型的功率管芯。Given this problem, the above solutions are not currently commercially available, and the double-sided modules seen in the literature are limited to large feature sizes like IGBT chips or diodes, and are not suitable for any type of power die.

在C.DiMarino等人的出版物“Design of a novel,high-density,high-speed10kV SiC MOSFET module”(2017IEEE能源转换大会与展会(ECCE),2017年,第4003-4010页)中,通过扩大栅极焊盘以允许与钼垫片连接解决了SiC MOSFET的栅极焊盘的尺寸问题。然而,该解决方案需要对管芯金属化进行大量修改,由此有损高效热和电流传送。In the publication "Design of a novel, high-density, high-speed 10kV SiC MOSFET module" by C. DiMarino et al. (2017 IEEE Conference and Exhibition on Energy Conversion (ECCE), 2017, pp. 4003-4010), by expanding The gate pad to allow connection with the molybdenum pad solves the problem of the size of the gate pad of the SiC MOSFET. However, this solution requires extensive modifications to the die metallization, thereby compromising efficient heat and current transfer.

发明内容SUMMARY OF THE INVENTION

鉴于上文,本发明旨在提供一种具有高效冷却和高可靠性的功率模块。In view of the above, the present invention aims to provide a power module with efficient cooling and high reliability.

本发明的另一目的在于提供一种具有双面冷却的功率模块,其管芯附接更容易,同时确保相对基板之间的所需电绝缘。Another object of the present invention is to provide a power module with double-sided cooling whose die attach is easier while ensuring the required electrical isolation between opposing substrates.

本发明的另一目的在于提供一种比现有技术更易于制造的功率模块。Another object of the present invention is to provide a power module that is easier to manufacture than the prior art.

因此,公开了一种功率模块,该功率模块包括:Therefore, a power module is disclosed that includes:

-第一平面基板和第二平面基板,各个基板包括导热材料层和导电材料构图层,- a first planar substrate and a second planar substrate, each substrate comprising a layer of thermally conductive material and a patterned layer of electrically conductive material,

-定位在第一平面基板和第二平面基板之间的多个预包装功率单元,各个预包装功率单元包括:- a plurality of prepackaged power cells positioned between the first planar substrate and the second planar substrate, each prepackaged power cell comprising:

ο电绝缘芯,ο Electrically insulating cores,

ο嵌入在电绝缘芯中的至少一个功率管芯,各个功率管芯具有相对的电触点,以及o at least one power die embedded in an electrically insulating core, each power die having opposing electrical contacts, and

ο在电绝缘芯的相对侧的两个导电材料外层,所述外层分别连接到平面基板的各个导电材料构图层,o two outer layers of conductive material on opposite sides of the electrically insulating core, said outer layers being respectively connected to the respective patterned layers of conductive material of the planar substrate,

其中,预包装功率单元的各个导电材料外层包括通过布置在预包装功率单元的电绝缘芯中的连接来连接到功率管芯的相应电触点的接触焊盘,所述接触焊盘的表面积大于与之连接的功率管芯电触点的表面积。wherein each outer layer of conductive material of the prepackaged power cell includes contact pads connected to corresponding electrical contacts of the power die by connections arranged in the electrically insulating core of the prepackaged power cell, the surface area of the contact pads being greater than the surface area of the electrical contacts of the power die to which it is connected.

在实施方式中,各个预包装功率单元还包括嵌入在电绝缘芯中的两个导电材料内层,各个内层被定位在功率管芯与相应外层之间,外层的厚度大于内层的厚度,In an embodiment, each prepackaged power cell further includes two inner layers of conductive material embedded in the electrically insulating core, each inner layer being positioned between the power die and a corresponding outer layer, the outer layers having a thickness greater than that of the inner layer thickness,

并且外层的所述接触焊盘与功率管芯的相应电触点之间的连接包括外层的所述接触焊盘与相应内层的接触焊盘之间的第一连接以及相应内层的所述接触焊盘与功率管芯的相应电触点之间的第二连接。And the connection between the contact pads of the outer layer and the corresponding electrical contacts of the power die includes a first connection between the contact pads of the outer layer and the contact pads of the corresponding inner layer and the connection of the corresponding inner layer. A second connection between the contact pads and corresponding electrical contacts of the power die.

然后,导电材料内层的接触焊盘的表面积可大于与之连接的功率管芯电触点的表面积。The surface area of the contact pads of the inner layer of conductive material may then be greater than the surface area of the electrical contacts of the power die to which they are connected.

预包装功率单元的外层与内层之间的连接以及功率管芯的内层与电触点之间的连接可以是布置在电绝缘芯中的通孔。The connections between the outer and inner layers of the prepackaged power cells and the connections between the inner layers of the power die and the electrical contacts may be through holes arranged in the electrically insulating core.

在实施方式中,功率模块还在预包装功率单元的各个外层与基板的构图层之间包括导电和导热接合材料层,所述接合材料选自包括焊膏、烧结膏或导电膏的组。In an embodiment, the power module further includes a layer of electrically and thermally conductive bonding material selected from the group consisting of solder paste, sinter paste, or conductive paste between each outer layer of the prepackaged power cell and the patterned layer of the substrate.

根据实施方式,功率模块还可包括填充位于基板之间的空间以及位于预包装功率单元之间的空间的介电材料。According to an embodiment, the power module may further include a dielectric material filling the spaces between the substrates and the spaces between the prepackaged power cells.

优选地,包含在不同预包装功率单元中的至少两个功率管芯具有作为功率管芯的相对侧上的电触点之间的最大距离测量的不同厚度,并且对应预包装功率单元具有在其相应两个导电材料外层之间测量的相等厚度。平面基板可以是直接接合铜基板、绝缘金属基板或活性金属钎焊基板。Preferably, the at least two power dies contained in the different prepackaged power cells have different thicknesses measured as the maximum distance between electrical contacts on opposite sides of the power die, and the corresponding prepackaged power cells have in their Equal thickness measured between respective two outer layers of conductive material. The planar substrate may be a direct bonded copper substrate, an insulated metal substrate, or a reactive metal brazed substrate.

在实施方式中,功率模块还包括安装在基板之一的导电材料构图层上的至少一个无源组件。In an embodiment, the power module further includes at least one passive component mounted on the patterned layer of conductive material on one of the substrates.

基板还可包括功率管芯的功率端子、输出端子和控制端子,所述端子电连接到导电材料构图层。The substrate may also include power terminals, output terminals, and control terminals of the power die, the terminals being electrically connected to the patterned layer of conductive material.

还公开了一种根据以上描述的功率模块的制造方法,该方法包括以下步骤:Also disclosed is a method for manufacturing a power module according to the above description, the method comprising the following steps:

-提供两个基板,各个基板包括具有接触焊盘的导电材料构图层和导热材料层,- two substrates are provided, each comprising a patterned layer of conductive material with contact pads and a layer of thermally conductive material,

-将预包装功率单元放置在两个基板之间,其中,各个预包装单元包括嵌入在电绝缘芯中并且连接到具有接触焊盘的导电材料外层的功率管芯,使得各个预包装功率单元的外层的接触焊盘与基板的构图层的接触焊盘匹配,- placing prepackaged power cells between two substrates, wherein each prepackaged cell includes a power die embedded in an electrically insulating core and connected to an outer layer of conductive material with contact pads, such that each prepackaged power cell The contact pads of the outer layer match the contact pads of the patterned layer of the substrate,

其中,接合材料存在于功率单元的导电材料外层上或导电材料构图层上,Wherein, the bonding material is present on the outer layer of the conductive material of the power unit or on the patterned layer of the conductive material,

-将基板和预包装功率单元接合在一起。- Bond the base plate and the prepackaged power unit together.

该方法可包括通过介电材料填充基板之间的剩余空间以及预包装功率单元之间的剩余空间的另一步骤。The method may include the further step of filling the remaining space between the substrates and the remaining space between the prepackaged power cells with a dielectric material.

该方法还可包括在接合步骤之前,将至少一个无源组件安装在基板的导电材料构图层之一上的步骤。The method may further include the step of mounting the at least one passive component on one of the patterned layers of conductive material of the substrate prior to the step of bonding.

可通过丝网印刷或喷嘴沉积来施加接合材料。The bonding material can be applied by screen printing or nozzle deposition.

该方法还可包括制造预包装功率单元,使得所有预包装功率单元具有相同的厚度的初步步骤。The method may also include the preliminary step of manufacturing the prepackaged power cells such that all of the prepackaged power cells have the same thickness.

由于附接在预包装功率单元的相对侧的两个基板,根据本发明的功率模块提供了良好的热耗散。在基板之间并入预包装功率单元允许确保所需电绝缘,因为功率单元充当基板之间的间隔物,并且还因为它们包括电绝缘材料芯。The power module according to the invention provides good heat dissipation due to the two substrates attached on opposite sides of the prepackaged power unit. Incorporating prepackaged power cells between the substrates allows ensuring the required electrical isolation, since the power cells act as spacers between the substrates, and also because they comprise a core of electrically insulating material.

另外,使用预包装功率单元使得可连接到功率管芯的小电焊盘,因为基板的接触焊盘可连接到起到扇出封装的作用的功率单元的扩大的接触焊盘。Additionally, the use of prepackaged power cells enables connection to small electrical pads of the power die, as the contact pads of the substrate can be connected to enlarged contact pads of the power cells that function as fan-out packages.

为了进一步增强热耗散和电绝缘,功率模块在基板之间的空间以及预包装功率单元之间的空间也可由电绝缘和导热材料填充。To further enhance heat dissipation and electrical insulation, the spaces between the substrates of the power modules and the spaces between the prepackaged power cells can also be filled with electrically insulating and thermally conductive materials.

本发明的其它特征和优点将从以下参照附图作为非限制性示例给出的详细描述显而易见。Other features and advantages of the present invention will become apparent from the following detailed description, given by way of non-limiting example with reference to the accompanying drawings.

附图说明Description of drawings

[图1][figure 1]

图1是根据本发明的实施方式的功率模块的示意性表示。Figure 1 is a schematic representation of a power module according to an embodiment of the invention.

[图2a][Figure 2a]

图2a是根据本发明的另一实施方式的功率模块的示意性表示。Figure 2a is a schematic representation of a power module according to another embodiment of the invention.

[图2b][Figure 2b]

图2b是图2a的功率模块的一部分的放大图。Figure 2b is an enlarged view of a portion of the power module of Figure 2a.

[图3a][Figure 3a]

图3a是根据本发明的另一实施方式的功率模块的示意图。Figure 3a is a schematic diagram of a power module according to another embodiment of the present invention.

[图3b][Figure 3b]

图3b是根据本发明的另一实施方式的功率模块的示意图。Figure 3b is a schematic diagram of a power module according to another embodiment of the present invention.

[图4][Figure 4]

图4示意性地表示根据本发明的实施方式的制造方法的主要步骤。Figure 4 schematically represents the main steps of a manufacturing method according to an embodiment of the present invention.

具体实施方式Detailed ways

参照图1,现在将描述根据本发明的实施方式的功率模块1。Referring to Figure 1, a power module 1 according to an embodiment of the present invention will now be described.

功率模块1包括两个基板10,各个基板10至少包括导热材料层11(也是电绝缘材料),其上设置有导电材料构图层12。例如,基板10可以是直接接合铜(DBC)基板,其中铜构图层12布置在形成导热和电绝缘层的陶瓷板11(例如,由氧化铝制成)上。根据其它示例,基板10可以是绝缘金属基板(IMS)或活性金属钎焊(AMB)基板。The power module 1 includes two substrates 10 , each of which includes at least a thermally conductive material layer 11 (also an electrically insulating material) on which a conductive material patterned layer 12 is disposed. For example, the substrate 10 may be a direct bonded copper (DBC) substrate with a copper patterned layer 12 disposed on a ceramic plate 11 (eg, made of alumina) forming a thermally conductive and electrically insulating layer. According to other examples, the substrate 10 may be an insulated metal substrate (IMS) or an active metal braze (AMB) substrate.

功率模块1还包括定位在两个基板10之间的多个预包装功率单元20,其中,两个导电材料构图层12朝着彼此定位。各个预包装功率单元20至少包括电绝缘芯21,其中嵌入有至少一个功率管芯22。功率管芯可以是诸如MOSFET、JFET或IGBT、HEMT的二极管或晶体管。在实施方式中,功率管芯22由宽带隙半导体(即,带隙在2-4eV的范围内的半导体)制成。例如,功率管芯可在碳化硅SiC中或氮化镓GaN中制成。The power module 1 also includes a plurality of prepackaged power cells 20 positioned between the two substrates 10, wherein the two patterned layers 12 of conductive material are positioned towards each other. Each prepackaged power cell 20 includes at least an electrically insulating core 21 in which at least one power die 22 is embedded. The power die may be a diode or transistor such as a MOSFET, JFET or IGBT, HEMT. In an embodiment, the power die 22 is made of a wide band gap semiconductor (ie, a semiconductor with a band gap in the range of 2-4 eV). For example, the power die can be fabricated in silicon carbide SiC or gallium nitride GaN.

功率管芯在其相对侧具有电触点220(图2b)。在实施方式中,功率管芯22是二极管并且具有两个相对的电触点220。在另一实施方式中,功率管芯22是晶体管并且具有三个电触点220,根据晶体管的类型包括栅极、源极和漏极或者栅极、发射极和集电极。功率管芯22也可具有数量大于三个的电触点。The power die has electrical contacts 220 on opposite sides thereof (FIG. 2b). In an embodiment, the power die 22 is a diode and has two opposing electrical contacts 220 . In another embodiment, the power die 22 is a transistor and has three electrical contacts 220 including gate, source and drain or gate, emitter and collector depending on the type of transistor. Power die 22 may also have electrical contacts greater than three in number.

预包装功率单元20的电绝缘芯21优选具有低热阻以提供更好的热耗散。电绝缘芯21可由FR-4玻璃环氧树脂、聚酰亚胺或者诸如HTCC(高温共烧陶瓷)或LTCC(低温共烧陶瓷)的陶瓷制成。The electrically insulating core 21 of the prepackaged power unit 20 preferably has a low thermal resistance to provide better heat dissipation. The electrically insulating core 21 may be made of FR-4 glass epoxy, polyimide, or a ceramic such as HTCC (High Temperature Co-fired Ceramic) or LTCC (Low Temperature Co-fired Ceramic).

另外,预包装功率单元1还在电绝缘芯21的相对主表面上包括两个导电材料(例如,铜)外层23。因此,当单元1被定位在基板之间时,预包装功率单元1的两个外层23与基板10的相应导电层12接触。Additionally, the prepackaged power unit 1 also includes two outer layers 23 of conductive material (eg, copper) on opposing major surfaces of the electrically insulating core 21 . Thus, when the unit 1 is positioned between the substrates, the two outer layers 23 of the prepackaged power unit 1 are in contact with the corresponding conductive layers 12 of the substrate 10 .

通过蚀刻或铣削对各个外层23进行构图以与基板10的导电层12的图案匹配。为此,各个外层包括至少一个接触焊盘230,其被配置为当预包装功率单元被插入在基板10之间时与导电层之一的接触焊盘(未示出)匹配。此外,外层23的接触焊盘230或连接到第一接触焊盘并处于相同电位的同一层的另一接触焊盘也连接到功率管芯22的相应电触点220。Each outer layer 23 is patterned to match the pattern of the conductive layer 12 of the substrate 10 by etching or milling. To this end, each outer layer includes at least one contact pad 230 configured to mate with a contact pad (not shown) of one of the conductive layers when the prepackaged power cells are inserted between the substrates 10 . Furthermore, the contact pads 230 of the outer layer 23 or another contact pad of the same layer connected to the first contact pad and at the same potential are also connected to the corresponding electrical contacts 220 of the power die 22 .

因此,在基板10的构图导电层12与功率管芯22之间建立连接。Thus, a connection is established between the patterned conductive layer 12 of the substrate 10 and the power die 22 .

因此,功率模块可包括集成在相应功率单元中的多个功率管芯22(各个功率单元可包括一个或更多个功率管芯),并且根据功率模块的所需拓扑来连接功率单元。例如,功率模块可以是逆变器或DC/DC转换器。Thus, a power module may include a plurality of power dies 22 integrated in respective power cells (each power cell may include one or more power dies), and the power cells are connected according to the desired topology of the power module. For example, the power module may be an inverter or a DC/DC converter.

在图1中示意性地示出的实施方式中,预包装功率单元1的外层的接触焊盘230通过布置在电绝缘芯21中的通孔24连接到功率管芯的相应电触点。In the embodiment shown schematically in FIG. 1 , the contact pads 230 of the outer layers of the prepackaged power unit 1 are connected to the corresponding electrical contacts of the power die through vias 24 arranged in the electrically insulating core 21 .

在图2a和图2b中示意性地示出的另一实施方式中,预包装功率单元1还包括至少两个导电材料(例如,铜)内层25,各个层被嵌入在电绝缘芯21中并被定位在功率管芯与相应外层23之间。在这种情况下,各个内层25包括通过布置在电绝缘芯21中的通孔240连接到功率管芯的相应电触点的至少一个接触焊盘250,并且外层23的接触焊盘230通过布置在电绝缘芯21中的其它通孔241连接到相应内层25的接触焊盘。因此,外层23的接触焊盘230通过定位在其间的内层25连接到功率管芯的电触点。In another embodiment, shown schematically in FIGS. 2a and 2b , the prepackaged power unit 1 further comprises at least two inner layers 25 of conductive material (eg copper), each layer being embedded in the electrically insulating core 21 and is positioned between the power die and the corresponding outer layer 23 . In this case, each inner layer 25 comprises at least one contact pad 250 connected to the corresponding electrical contact of the power die through a via 240 arranged in the electrically insulating core 21 , and the contact pad 230 of the outer layer 23 Connections to the contact pads of the respective inner layers 25 are made through other vias 241 arranged in the electrically insulating core 21 . Thus, the contact pads 230 of the outer layer 23 are connected to the electrical contacts of the power die through the inner layer 25 positioned therebetween.

优选地,外层的接触焊盘230的表面积大于与其连接的功率管芯电触点220的表面积。因此,由于外层的扩大的接触焊盘230,使用预包装功率单元允许扩大功率管芯的接触表面积。Preferably, the surface area of the contact pads 230 of the outer layer is greater than the surface area of the power die electrical contacts 220 to which they are connected. Thus, the use of prepackaged power cells allows the contact surface area of the power die to be enlarged due to the enlarged contact pads 230 of the outer layers.

在预包装功率单元20还包括具有相应接触焊盘250的导电材料内层25的实施方式中,内层25的接触焊盘250的表面积大于与其连接的功率管芯的电触点的表面积,并且可小于也与其连接的外层的接触焊盘230的表面积或具有相同的表面积。In embodiments where the prepackaged power cell 20 also includes an inner layer 25 of conductive material with corresponding contact pads 250, the surface area of the contact pads 250 of the inner layer 25 is greater than the surface area of the electrical contacts of the power die to which it is connected, and It may be smaller or have the same surface area as the contact pads 230 of the outer layer to which it is also connected.

因此,在任何情况下功率管芯的电触点与外层23接触焊盘230之间的表面积增加。Thus, the surface area between the electrical contacts of the power die and the contact pads 230 of the outer layer 23 is increased in any case.

这使得预包装功率单元2与基板10的组装和连接更容易,并且还允许向管芯22传输高功率。This makes assembly and connection of the prepackaged power cell 2 to the substrate 10 easier, and also allows high power delivery to the die 22 .

在预包装功率单元20包括导电材料内层25的实施方式中,外层的厚度可大于内层25的厚度(例如,至少大五倍或十倍),以便增加向功率管芯的功率传输。根据非限制性实施方式,内层25可具有约30-35μm的厚度,外层23可具有约400μm的厚度。In embodiments where the prepackaged power cell 20 includes an inner layer 25 of conductive material, the thickness of the outer layer may be greater than the thickness of the inner layer 25 (eg, at least five or ten times greater) in order to increase power transfer to the power die. According to non-limiting embodiments, the inner layer 25 may have a thickness of about 30-35 μm and the outer layer 23 may have a thickness of about 400 μm.

为了适应足够的功率传输,将功率管芯电触点与内层接触焊盘连接的通孔240的密度可为至少20通孔/mm2(例如,30通孔/mm2),例如通孔深度与钻头直径之比为1:2.5。To accommodate adequate power transfer, the density of vias 240 connecting the power die electrical contacts to the inner layer contact pads may be at least 20 vias/mm 2 (eg, 30 vias/mm 2 ), such as vias The ratio of depth to drill diameter is 1:2.5.

由于外层的接触焊盘的表面积更重要,将内层的接触焊盘250与外层的接触焊盘连接的通孔241的密度可等于或低于30通孔/mm2;例如,通孔深度与钻头直径之比为1:1。Since the surface area of the contact pads of the outer layer is more important, the density of the vias 241 connecting the contact pads 250 of the inner layer and the contact pads of the outer layer may be equal to or lower than 30 vias/mm 2 ; for example, vias The ratio of depth to drill diameter is 1:1.

各个预包装功率单元通过烧结、焊接或液体扩散接合技术附接到模块1的基板10,如下面将更详细描述的。因此,模块1还在预包装功率单元1的各个外层23与基板的导电层12之间包括诸如焊膏、烧结膏(例如,银烧结膏)或导电膏的接合材料层30。The individual prepackaged power cells are attached to the base plate 10 of the module 1 by sintering, welding or liquid diffusion bonding techniques, as will be described in more detail below. Accordingly, the module 1 also includes a layer 30 of bonding material, such as solder paste, frit paste (eg, silver frit paste) or conductive paste, between the various outer layers 23 of the prepackaged power cells 1 and the conductive layer 12 of the substrate.

由于各种功率管芯的厚度可为可变的(该厚度是功率管芯的相对电触点之间的距离),所以同一功率模块1并且包含变化厚度的功率管芯的所有预包装功率单元优选具有相同的厚度(作为功率单元的外层23之间的距离测量)。为了适应功率管芯之间的厚度变化,功率单元可具有恒定厚度的电绝缘芯,其被确定为足以嵌入任何功率管芯并确保两个基板10之间的足够电隔离。Since the thickness of the various power dies may be variable (the thickness being the distance between opposing electrical contacts of the power dies), all prepackaged power cells of the same power module 1 and containing power dies of varying thickness It preferably has the same thickness (measured as the distance between the outer layers 23 of the power cells). To accommodate thickness variations between power dies, the power cells may have an electrically insulating core of constant thickness determined to be sufficient to embed any power die and ensure adequate electrical isolation between the two substrates 10 .

因此,电绝缘芯21的厚度被确定为嵌入最大厚度的功率管芯并在基板之间提供电隔离的最小厚度。因此,功率管芯的厚度变化由功率单元补偿,因此功率模块的设计和制造更容易。Accordingly, the thickness of the electrically insulating core 21 is determined to be the minimum thickness that embeds the maximum thickness of the power die and provides electrical isolation between the substrates. Therefore, the thickness variation of the power die is compensated by the power cell, so the design and manufacture of the power module is easier.

功率单元的厚度超过功率管芯还允许在基板10之间创建足够的空间以在它们之间提供所需电绝缘。The thickness of the power cells over the power dies also allows sufficient space to be created between the substrates 10 to provide the required electrical isolation between them.

如例如图3a和图3b中所示,功率模块1还可包括附加无源组件40(例如,去耦电容器或栅极电阻器),其可被限制到基板之一的一个导电层12。As shown eg in Figures 3a and 3b, the power module 1 may also include additional passive components 40 (eg decoupling capacitors or gate resistors), which may be confined to one conductive layer 12 of one of the substrates.

功率模块1还包括端子,所述端子可以是焊接在导电层12上的一个或更多个引线框架的一部分。所述端子包括管芯的功率端子50、输出端子51和控制端子52。驱动器可被焊接在导电层之一上并连接到控制端子,或者可连同它们意在控制的功率管芯一起被并入功率单元中以便减小驱动器与功率管芯之间的距离。The power module 1 also includes terminals, which may be part of one or more lead frames soldered on the conductive layer 12 . The terminals include a power terminal 50 , an output terminal 51 and a control terminal 52 of the die. The drivers can be soldered on one of the conductive layers and connected to the control terminals, or can be incorporated into the power cells along with the power dies they are intended to control in order to reduce the distance between the drivers and the power dies.

最后,功率模块1优选地还包括填充基板10之间的间隙以及功率单元与包含在模块中的其它组件之间的间隙的介电材料60。其可以是FR-4玻璃环氧树脂、聚对二甲苯或有机硅。优选地,介电材料具有大于至少1W/(m.K)的热导率,以便增强热耗散,同时还增加基板10之间的电绝缘。Finally, the power module 1 preferably also includes a dielectric material 60 filling the gaps between the substrates 10 and the gaps between the power cells and other components contained in the module. It can be FR-4 glass epoxy, parylene or silicone. Preferably, the dielectric material has a thermal conductivity greater than at least 1 W/(m.K) in order to enhance heat dissipation while also increasing electrical insulation between substrates 10 .

参照图4,现在将说明上述功率模块1的制造方法。Referring to FIG. 4 , a method of manufacturing the above-described power module 1 will now be described.

该方法包括:第一步骤100,提供具有电绝缘导热材料层11和导电材料构图层12的两个基板10。通过铣削或蚀刻来进行构图。在实施方式中,诸如电容器的至少一个无源组件可例如通过焊接附接到基板之一。还可在执行步骤200之后进行无源组件的安装。The method includes: a first step 100 , providing two substrates 10 having a layer 11 of electrically insulating thermally conductive material and a patterned layer 12 of conductive material. Patterning is done by milling or etching. In an embodiment, at least one passive component, such as a capacitor, may be attached to one of the substrates, eg, by soldering. The installation of passive components may also be performed after step 200 is performed.

在第二步骤200期间,根据以上描述的多个预包装功率单元20被定位在基板之间,使得基板10的各个构图层12面向功率单元的外层23,并且使得构图层的接触焊盘与外层23的接触焊盘匹配。During a second step 200, a plurality of prepackaged power cells 20 according to the above description are positioned between the substrates such that each patterned layer 12 of the substrate 10 faces the outer layer 23 of the power cells and the contact pads of the patterned layer are aligned with The contact pads of the outer layer 23 are matched.

与将功率管芯直接定位在基板上相比,此步骤更易于执行,因为预包装功率单元的外部接触焊盘(由外层的接触焊盘形成)比功率管芯的电触点大。This step is easier to perform than positioning the power die directly on the substrate because the external contact pads of the prepackaged power cells (formed by the contact pads of the outer layers) are larger than the electrical contacts of the power die.

优选地,在步骤200之前,将接合材料30施加在外层23和基板的构图层12中的至少一个的接触焊盘上。优选地,将接合材料施加在外层和构图层12二者的接触焊盘上。接合材料可以是焊膏或烧结膏或导电膏。其可通过丝网印刷或喷嘴沉积施加。Preferably, prior to step 200, a bonding material 30 is applied on the contact pads of at least one of the outer layer 23 and the patterned layer 12 of the substrate. Preferably, the bonding material is applied to the contact pads of both the outer layer and the patterned layer 12 . The bonding material may be solder paste or frit paste or conductive paste. It can be applied by screen printing or nozzle deposition.

然后,该方法包括步骤300:将基板与预包装功率单元20接合。在烧结的情况下,可通过热将两个基板压在一起。由于通过预封装单元来确保两个基板之间的距离,所以不存在倾斜或表面上压力不平衡的风险。Then, the method includes the step 300 of bonding the substrate with the prepackaged power unit 20 . In the case of sintering, the two substrates can be pressed together by heat. Since the distance between the two substrates is ensured by the pre-packaged unit, there is no risk of tilting or pressure imbalance on the surface.

在焊接的情况下,由焊膏的相变导致的表面张力可能破坏基板关于预包装功率单元的各个接触焊盘的定位。在这种情况下,可使用附加定位销(未示出)来将基板和功率单元的组装保持就位。In the case of soldering, the surface tension caused by the phase transition of the solder paste can disrupt the positioning of the substrate with respect to the various contact pads of the prepackaged power cells. In this case, additional alignment pins (not shown) may be used to hold the assembly of the base plate and power unit in place.

支撑至少一个端子的引线框架也可通过焊接或烧结附接到至少一个基板,以用于提供至少一些模块端子。也可在预包装功率单元与基板接合之前执行该引线框架的接合。A lead frame supporting the at least one terminal may also be attached to the at least one substrate by soldering or sintering for providing at least some of the module terminals. Bonding of the lead frame may also be performed before the prepackaged power cells are bonded to the substrate.

可选地,在步骤400期间,可通过插入介电填充材料来填充基板之间的剩余间隙以及组件(功率单元和/或无源组件)之间的剩余间隙,以便增强基板之间的电绝缘和热耗散。Optionally, during step 400, the remaining gaps between the substrates and the remaining gaps between components (power cells and/or passive components) may be filled by inserting a dielectric filler material in order to enhance electrical isolation between the substrates and heat dissipation.

Claims (15)

1.一种功率模块,该功率模块包括:1. A power module comprising: -第一平面基板和第二平面基板,各个基板包括导热材料的层和导电材料的构图层,- a first planar substrate and a second planar substrate, each substrate comprising a layer of thermally conductive material and a patterned layer of electrically conductive material, -定位在所述第一平面基板和所述第二平面基板之间的多个预包装功率单元,各个预包装功率单元包括:- a plurality of prepackaged power cells positioned between said first planar substrate and said second planar substrate, each prepackaged power cell comprising: ○电绝缘芯,○ Electrically insulating core, ○嵌入在所述电绝缘芯中的至少一个功率管芯,各个功率管芯具有相对的电触点,以及o at least one power die embedded in said electrically insulating core, each power die having opposing electrical contacts, and ○在所述电绝缘芯的相对侧的导电材料的两个外层,所述外层分别连接到平面基板的导电材料的各个构图层,o two outer layers of conductive material on opposite sides of the electrically insulating core, the outer layers being connected to respective patterned layers of conductive material of the planar substrate, 其中,预包装功率单元的导电材料的各个外层包括通过布置在所述预包装功率单元的所述电绝缘芯中的连接来连接到所述功率管芯的相应电触点的接触焊盘,所述接触焊盘的表面积大于与其连接的功率管芯电触点的表面积。wherein each outer layer of conductive material of the prepackaged power cell includes contact pads connected to corresponding electrical contacts of the power die through connections arranged in the electrically insulating core of the prepackaged power cell, The surface area of the contact pads is greater than the surface area of the electrical contacts of the power die to which they are connected. 2.根据权利要求1所述的功率模块,其中,各个预包装功率单元还包括嵌入在所述电绝缘芯中的导电材料的两个内层,各个内层被定位在所述功率管芯与相应的外层之间,所述外层的厚度大于所述内层的厚度,2. The power module of claim 1, wherein each prepackaged power cell further comprises two inner layers of conductive material embedded in the electrically insulating core, each inner layer positioned between the power die and the Between the corresponding outer layers, the thickness of the outer layer is greater than the thickness of the inner layer, 并且外层的所述接触焊盘与所述功率管芯的相应电触点之间的连接包括所述外层的所述接触焊盘与相应内层的接触焊盘之间的第一连接以及相应内层的所述接触焊盘与所述功率管芯的相应电触点之间的第二连接。And the connection between the contact pads of the outer layer and the corresponding electrical contacts of the power die includes a first connection between the contact pads of the outer layer and the contact pads of the corresponding inner layer and A second connection between the contact pads of the respective inner layers and the respective electrical contacts of the power die. 3.根据权利要求2所述的功率模块,其中,导电材料的所述内层的所述接触焊盘的表面积大于与其连接的功率管芯电触点的表面积。3. The power module of claim 2, wherein the surface area of the contact pads of the inner layer of conductive material is greater than the surface area of a power die electrical contact to which it is connected. 4.根据权利要求1或2所述的功率模块,其中,预包装功率单元的外层与内层之间的连接以及功率管芯的内层与电触点之间的连接是布置在所述电绝缘芯中的通孔。4. The power module of claim 1 or 2, wherein the connection between the outer layer and the inner layer of the prepackaged power cell and the connection between the inner layer of the power die and the electrical contacts are arranged in the Through holes in the electrically insulating core. 5.根据前述权利要求中的任一项所述的功率模块,该功率模块还包括预包装功率单元的各个外层与基板的所述构图层之间的导电和导热接合材料的层,所述接合材料选自包括焊膏、烧结膏或导电膏的组。5. The power module of any preceding claim, further comprising a layer of electrically and thermally conductive bonding material between each outer layer of the prepackaged power cell and the patterned layer of the substrate, the The bonding material is selected from the group consisting of solder paste, frit paste or conductive paste. 6.根据前述权利要求中的任一项所述的功率模块,该功率模块还包括填充位于所述基板之间的空间以及位于所述预包装功率单元之间的空间的介电材料。6. The power module of any preceding claim, further comprising a dielectric material filling the spaces between the substrates and the spaces between the prepackaged power cells. 7.根据前述权利要求中的任一项所述的功率模块,其中,包含在不同预包装功率单元中的至少两个功率管芯具有作为所述功率管芯的相对侧上的电触点之间的最大距离测量的不同厚度,并且对应的预包装功率单元具有在其相应的导电材料的两个外层之间测量的相等厚度。7. The power module of any preceding claim, wherein at least two power dies contained in different prepackaged power cells have as one of the electrical contacts on opposite sides of the power dies Different thicknesses measured at the maximum distance between and the corresponding prepackaged power cells have equal thicknesses measured between their respective two outer layers of conductive material. 8.根据前述权利要求中的任一项所述的功率模块,其中,平面基板是直接接合铜基板、绝缘金属基板或活性金属钎焊基板。8. A power module according to any preceding claim, wherein the planar substrate is a direct bonded copper substrate, an insulated metal substrate or a reactive metal brazed substrate. 9.根据前述权利要求中的任一项所述的功率模块,该功率模块还包括安装在所述基板之一的导电材料的所述构图层上的至少一个无源组件。9. The power module of any preceding claim, further comprising at least one passive component mounted on the patterned layer of conductive material of one of the substrates. 10.根据前述权利要求中的任一项所述的功率模块,其中,所述基板还包括所述功率管芯的功率端子、输出端子和控制端子,所述端子电连接到导电材料的所述构图层。10. The power module of any preceding claim, wherein the substrate further comprises power, output and control terminals of the power die, the terminals being electrically connected to the conductive material Composition layers. 11.一种用于制造根据前述权利要求中的任一项所述的功率模块的方法,该方法包括以下步骤:11. A method for manufacturing a power module according to any preceding claim, the method comprising the steps of: -提供两个基板,各个基板包括具有接触焊盘的导电材料的构图层和导热材料的层,- providing two substrates, each comprising a patterned layer of electrically conductive material with contact pads and a layer of thermally conductive material, -将预包装功率单元放置在所述两个基板之间,其中,各个预包装单元包括嵌入在电绝缘芯中并且连接到具有接触焊盘的导电材料的外层的功率管芯,使得各个预包装功率单元的外层的所述接触焊盘与所述基板的构图层的接触焊盘匹配,- placing a prepackaged power unit between the two substrates, wherein each prepackaged unit comprises a power die embedded in an electrically insulating core and connected to an outer layer of conductive material with contact pads, such that each prepackaged unit the contact pads of the outer layer of the packaging power unit are matched with the contact pads of the patterned layer of the substrate, 其中,接合材料存在于所述功率单元的导电材料的所述外层上或导电材料的所述构图层上,wherein the bonding material is present on the outer layer of the conductive material of the power unit or on the patterned layer of the conductive material, -将所述基板和预包装功率单元接合在一起。- Bonding the base plate and the prepackaged power unit together. 12.根据权利要求11所述的方法,该方法还包括通过介电材料填充所述基板之间的剩余空间以及所述预包装功率单元之间的剩余空间的步骤。12. The method of claim 11, further comprising the step of filling the remaining space between the substrates and the remaining space between the prepackaged power cells with a dielectric material. 13.根据权利要求11或12所述的方法,该方法还包括在接合步骤之前,将至少一个无源组件安装在所述基板的导电材料的所述构图层之一上的步骤。13. The method of claim 11 or 12, further comprising the step of mounting at least one passive component on one of the patterned layers of conductive material of the substrate prior to the bonding step. 14.根据权利要求11至13中的任一项所述的方法,其中,通过丝网印刷或喷嘴沉积来施加所述接合材料。14. The method of any one of claims 11 to 13, wherein the bonding material is applied by screen printing or nozzle deposition. 15.根据权利要求11至14中的任一项所述的方法,该方法还包括制造所述预包装功率单元以使得所有所述预包装功率单元具有相同的厚度的初步步骤。15. The method of any one of claims 11 to 14, further comprising the preliminary step of manufacturing the prepackaged power cells such that all of the prepackaged power cells have the same thickness.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116169106A (en) * 2023-03-06 2023-05-26 上海狮门半导体有限公司 A double-sided heat dissipation power module and its preparation method

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3153696A1 (en) * 2023-10-03 2025-04-04 Pellenc Energy Method of associating a microcircuit with a battery cell

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101136396A (en) * 2006-08-30 2008-03-05 株式会社电装 Power electronics package consisting of two substrates with multiple semiconductor chips and electronic components
US20080054425A1 (en) * 2006-08-29 2008-03-06 Denso Corporation Power electronic package having two substrates with multiple electronic components
US20090160046A1 (en) * 2007-12-21 2009-06-25 Infineon Technologies Ag Electronic device and method
US20090236749A1 (en) * 2008-03-18 2009-09-24 Infineon Technologies Ag Electronic device and manufacturing thereof
DE102008040906A1 (en) * 2008-07-31 2010-02-04 Robert Bosch Gmbh Printed circuit board with electronic component
CN101989582A (en) * 2009-07-31 2011-03-23 全懋精密科技股份有限公司 Packaging substrate embedded with semiconductor chip
JP2011222554A (en) * 2010-04-02 2011-11-04 Denso Corp Wiring board with built-in semiconductor chip
US20130307156A1 (en) * 2012-05-15 2013-11-21 Infineon Technologies Ag Reliable Area Joints for Power Semiconductors
US20160293579A1 (en) * 2015-04-03 2016-10-06 Globalfoundries Inc. Integration structures for high current applications
CN107039357A (en) * 2015-11-30 2017-08-11 英飞凌科技奥地利有限公司 Chip protects capsule and method
CN206595255U (en) * 2017-01-24 2017-10-27 比亚迪股份有限公司 A kind of power model

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2741697B2 (en) * 1990-07-17 1998-04-22 本田技研工業株式会社 Semiconductor device
US6072240A (en) 1998-10-16 2000-06-06 Denso Corporation Semiconductor chip package
DE10221082A1 (en) * 2002-05-11 2003-11-20 Bosch Gmbh Robert Semiconductor device
JP4385324B2 (en) * 2004-06-24 2009-12-16 富士電機システムズ株式会社 Semiconductor module and manufacturing method thereof
JP4409380B2 (en) * 2004-07-22 2010-02-03 本田技研工業株式会社 Electronic circuit equipment
US7999369B2 (en) 2006-08-29 2011-08-16 Denso Corporation Power electronic package having two substrates with multiple semiconductor chips and electronic components
FR2956423B1 (en) * 2010-02-16 2014-01-10 Soprema DEVICE FOR FASTENING PLATES OR PANELS ON A COVER AND RESULTING COMPOSITE COVER
JP5732880B2 (en) * 2011-02-08 2015-06-10 株式会社デンソー Semiconductor device and manufacturing method thereof
US9041183B2 (en) * 2011-07-19 2015-05-26 Ut-Battelle, Llc Power module packaging with double sided planar interconnection and heat exchangers
EP3226014B1 (en) * 2016-03-30 2024-01-10 Mitsubishi Electric R&D Centre Europe B.V. Method for estimating a level of damage or a lifetime expectation of a power semiconductor module comprising at least one die
JP6643481B2 (en) * 2016-07-27 2020-02-12 株式会社日立製作所 Semiconductor module and method of manufacturing semiconductor module
EP3547538B1 (en) * 2018-03-26 2021-08-11 Mitsubishi Electric R & D Centre Europe B.V. A device and a method for controlling the switching of at least a first power semiconductor switch
EP3584833B1 (en) * 2018-06-19 2021-09-01 Mitsubishi Electric R&D Centre Europe B.V. Power module with improved alignment
US11515273B2 (en) * 2019-07-26 2022-11-29 Sandisk Technologies Llc Bonded assembly containing oxidation barriers, hybrid bonding, or air gap, and methods of forming the same
US11393780B2 (en) * 2019-07-26 2022-07-19 Sandisk Technologies Llc Bonded assembly containing oxidation barriers, hybrid bonding, or air gap, and methods of forming the same
US11270963B2 (en) * 2020-01-14 2022-03-08 Sandisk Technologies Llc Bonding pads including interfacial electromigration barrier layers and methods of making the same
US11171097B2 (en) * 2020-01-28 2021-11-09 Sandisk Technologies Llc Bonded assembly containing metal-organic framework bonding dielectric and methods of forming the same

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080054425A1 (en) * 2006-08-29 2008-03-06 Denso Corporation Power electronic package having two substrates with multiple electronic components
CN101136396A (en) * 2006-08-30 2008-03-05 株式会社电装 Power electronics package consisting of two substrates with multiple semiconductor chips and electronic components
US20090160046A1 (en) * 2007-12-21 2009-06-25 Infineon Technologies Ag Electronic device and method
US20090236749A1 (en) * 2008-03-18 2009-09-24 Infineon Technologies Ag Electronic device and manufacturing thereof
DE102008040906A1 (en) * 2008-07-31 2010-02-04 Robert Bosch Gmbh Printed circuit board with electronic component
CN101989582A (en) * 2009-07-31 2011-03-23 全懋精密科技股份有限公司 Packaging substrate embedded with semiconductor chip
JP2011222554A (en) * 2010-04-02 2011-11-04 Denso Corp Wiring board with built-in semiconductor chip
US20130307156A1 (en) * 2012-05-15 2013-11-21 Infineon Technologies Ag Reliable Area Joints for Power Semiconductors
US20160293579A1 (en) * 2015-04-03 2016-10-06 Globalfoundries Inc. Integration structures for high current applications
CN107039357A (en) * 2015-11-30 2017-08-11 英飞凌科技奥地利有限公司 Chip protects capsule and method
CN206595255U (en) * 2017-01-24 2017-10-27 比亚迪股份有限公司 A kind of power model

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116169106A (en) * 2023-03-06 2023-05-26 上海狮门半导体有限公司 A double-sided heat dissipation power module and its preparation method

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